imxdi.c 4.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009-2012 ADVANSEE
  4. * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
  5. *
  6. * Based on the Linux rtc-imxdi.c driver, which is:
  7. * Copyright 2008-2009 Freescale Semiconductor, Inc. All Rights Reserved.
  8. * Copyright 2010 Orex Computed Radiography
  9. */
  10. /*
  11. * Date & Time support for Freescale i.MX DryIce RTC
  12. */
  13. #include <common.h>
  14. #include <command.h>
  15. #include <linux/compat.h>
  16. #include <rtc.h>
  17. #include <linux/delay.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/imx-regs.h>
  20. /* DryIce Register Definitions */
  21. struct imxdi_regs {
  22. u32 dtcmr; /* Time Counter MSB Reg */
  23. u32 dtclr; /* Time Counter LSB Reg */
  24. u32 dcamr; /* Clock Alarm MSB Reg */
  25. u32 dcalr; /* Clock Alarm LSB Reg */
  26. u32 dcr; /* Control Reg */
  27. u32 dsr; /* Status Reg */
  28. u32 dier; /* Interrupt Enable Reg */
  29. };
  30. #define DCAMR_UNSET 0xFFFFFFFF /* doomsday - 1 sec */
  31. #define DCR_TCE (1 << 3) /* Time Counter Enable */
  32. #define DSR_WBF (1 << 10) /* Write Busy Flag */
  33. #define DSR_WNF (1 << 9) /* Write Next Flag */
  34. #define DSR_WCF (1 << 8) /* Write Complete Flag */
  35. #define DSR_WEF (1 << 7) /* Write Error Flag */
  36. #define DSR_CAF (1 << 4) /* Clock Alarm Flag */
  37. #define DSR_NVF (1 << 1) /* Non-Valid Flag */
  38. #define DSR_SVF (1 << 0) /* Security Violation Flag */
  39. #define DIER_WNIE (1 << 9) /* Write Next Interrupt Enable */
  40. #define DIER_WCIE (1 << 8) /* Write Complete Interrupt Enable */
  41. #define DIER_WEIE (1 << 7) /* Write Error Interrupt Enable */
  42. #define DIER_CAIE (1 << 4) /* Clock Alarm Interrupt Enable */
  43. /* Driver Private Data */
  44. struct imxdi_data {
  45. struct imxdi_regs __iomem *regs;
  46. int init_done;
  47. };
  48. static struct imxdi_data data;
  49. /*
  50. * This function attempts to clear the dryice write-error flag.
  51. *
  52. * A dryice write error is similar to a bus fault and should not occur in
  53. * normal operation. Clearing the flag requires another write, so the root
  54. * cause of the problem may need to be fixed before the flag can be cleared.
  55. */
  56. static void clear_write_error(void)
  57. {
  58. int cnt;
  59. puts("### Warning: RTC - Register write error!\n");
  60. /* clear the write error flag */
  61. __raw_writel(DSR_WEF, &data.regs->dsr);
  62. /* wait for it to take effect */
  63. for (cnt = 0; cnt < 1000; cnt++) {
  64. if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0)
  65. return;
  66. udelay(10);
  67. }
  68. puts("### Error: RTC - Cannot clear write-error flag!\n");
  69. }
  70. /*
  71. * Write a dryice register and wait until it completes.
  72. *
  73. * Use interrupt flags to determine when the write has completed.
  74. */
  75. #define DI_WRITE_WAIT(val, reg) \
  76. ( \
  77. /* do the register write */ \
  78. __raw_writel((val), &data.regs->reg), \
  79. \
  80. di_write_wait((val), #reg) \
  81. )
  82. static int di_write_wait(u32 val, const char *reg)
  83. {
  84. int cnt;
  85. int ret = 0;
  86. int rc = 0;
  87. /* wait for the write to finish */
  88. for (cnt = 0; cnt < 100; cnt++) {
  89. if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) {
  90. ret = 1;
  91. break;
  92. }
  93. udelay(10);
  94. }
  95. if (ret == 0)
  96. printf("### Warning: RTC - Write-wait timeout "
  97. "val = 0x%.8x reg = %s\n", val, reg);
  98. /* check for write error */
  99. if (__raw_readl(&data.regs->dsr) & DSR_WEF) {
  100. clear_write_error();
  101. rc = -1;
  102. }
  103. return rc;
  104. }
  105. /*
  106. * Initialize dryice hardware
  107. */
  108. static int di_init(void)
  109. {
  110. int rc = 0;
  111. data.regs = (struct imxdi_regs __iomem *)IMX_DRYICE_BASE;
  112. /* mask all interrupts */
  113. __raw_writel(0, &data.regs->dier);
  114. /* put dryice into valid state */
  115. if (__raw_readl(&data.regs->dsr) & DSR_NVF) {
  116. rc = DI_WRITE_WAIT(DSR_NVF | DSR_SVF, dsr);
  117. if (rc)
  118. goto err;
  119. }
  120. /* initialize alarm */
  121. rc = DI_WRITE_WAIT(DCAMR_UNSET, dcamr);
  122. if (rc)
  123. goto err;
  124. rc = DI_WRITE_WAIT(0, dcalr);
  125. if (rc)
  126. goto err;
  127. /* clear alarm flag */
  128. if (__raw_readl(&data.regs->dsr) & DSR_CAF) {
  129. rc = DI_WRITE_WAIT(DSR_CAF, dsr);
  130. if (rc)
  131. goto err;
  132. }
  133. /* the timer won't count if it has never been written to */
  134. if (__raw_readl(&data.regs->dtcmr) == 0) {
  135. rc = DI_WRITE_WAIT(0, dtcmr);
  136. if (rc)
  137. goto err;
  138. }
  139. /* start keeping time */
  140. if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) {
  141. rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr);
  142. if (rc)
  143. goto err;
  144. }
  145. data.init_done = 1;
  146. return 0;
  147. err:
  148. return rc;
  149. }
  150. int rtc_get(struct rtc_time *tmp)
  151. {
  152. unsigned long now;
  153. int rc = 0;
  154. if (!data.init_done) {
  155. rc = di_init();
  156. if (rc)
  157. goto err;
  158. }
  159. now = __raw_readl(&data.regs->dtcmr);
  160. rtc_to_tm(now, tmp);
  161. err:
  162. return rc;
  163. }
  164. int rtc_set(struct rtc_time *tmp)
  165. {
  166. unsigned long now;
  167. int rc;
  168. if (!data.init_done) {
  169. rc = di_init();
  170. if (rc)
  171. goto err;
  172. }
  173. now = rtc_mktime(tmp);
  174. /* zero the fractional part first */
  175. rc = DI_WRITE_WAIT(0, dtclr);
  176. if (rc == 0)
  177. rc = DI_WRITE_WAIT(now, dtcmr);
  178. err:
  179. return rc;
  180. }
  181. void rtc_reset(void)
  182. {
  183. di_init();
  184. }