mpc83xx_sdram.c 32 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2018
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <init.h>
  9. #include <log.h>
  10. #include <ram.h>
  11. #include <asm/bitops.h>
  12. #include <dt-bindings/memory/mpc83xx-sdram.h>
  13. DECLARE_GLOBAL_DATA_PTR;
  14. /* Masks for the CS config register */
  15. static const u32 CSCONFIG_ENABLE = 0x80000000;
  16. static const u32 BANK_BITS_2;
  17. static const u32 BANK_BITS_3 = 0x00004000;
  18. static const u32 ROW_BITS_12;
  19. static const u32 ROW_BITS_13 = 0x00000100;
  20. static const u32 ROW_BITS_14 = 0x00000200;
  21. static const u32 COL_BITS_8;
  22. static const u32 COL_BITS_9 = 0x00000001;
  23. static const u32 COL_BITS_10 = 0x00000002;
  24. static const u32 COL_BITS_11 = 0x00000003;
  25. /* Shifts for the DDR SDRAM Timing Configuration 3 register */
  26. static const uint TIMING_CFG3_EXT_REFREC_SHIFT = (31 - 15);
  27. /* Shifts for the DDR SDRAM Timing Configuration 0 register */
  28. static const uint TIMING_CFG0_RWT_SHIFT = (31 - 1);
  29. static const uint TIMING_CFG0_WRT_SHIFT = (31 - 3);
  30. static const uint TIMING_CFG0_RRT_SHIFT = (31 - 5);
  31. static const uint TIMING_CFG0_WWT_SHIFT = (31 - 7);
  32. static const uint TIMING_CFG0_ACT_PD_EXIT_SHIFT = (31 - 11);
  33. static const uint TIMING_CFG0_PRE_PD_EXIT_SHIFT = (31 - 15);
  34. static const uint TIMING_CFG0_ODT_PD_EXIT_SHIFT = (31 - 23);
  35. static const uint TIMING_CFG0_MRS_CYC_SHIFT = (31 - 31);
  36. /* Shifts for the DDR SDRAM Timing Configuration 1 register */
  37. static const uint TIMING_CFG1_PRETOACT_SHIFT = (31 - 3);
  38. static const uint TIMING_CFG1_ACTTOPRE_SHIFT = (31 - 7);
  39. static const uint TIMING_CFG1_ACTTORW_SHIFT = (31 - 11);
  40. static const uint TIMING_CFG1_CASLAT_SHIFT = (31 - 15);
  41. static const uint TIMING_CFG1_REFREC_SHIFT = (31 - 19);
  42. static const uint TIMING_CFG1_WRREC_SHIFT = (31 - 23);
  43. static const uint TIMING_CFG1_ACTTOACT_SHIFT = (31 - 27);
  44. static const uint TIMING_CFG1_WRTORD_SHIFT = (31 - 31);
  45. /* Shifts for the DDR SDRAM Timing Configuration 2 register */
  46. static const uint TIMING_CFG2_CPO_SHIFT = (31 - 8);
  47. static const uint TIMING_CFG2_WR_DATA_DELAY_SHIFT = (31 - 21);
  48. static const uint TIMING_CFG2_ADD_LAT_SHIFT = (31 - 3);
  49. static const uint TIMING_CFG2_WR_LAT_DELAY_SHIFT = (31 - 12);
  50. static const uint TIMING_CFG2_RD_TO_PRE_SHIFT = (31 - 18);
  51. static const uint TIMING_CFG2_CKE_PLS_SHIFT = (31 - 25);
  52. static const uint TIMING_CFG2_FOUR_ACT_SHIFT;
  53. /* Shifts for the DDR SDRAM Control Configuration register */
  54. static const uint SDRAM_CFG_SREN_SHIFT = (31 - 1);
  55. static const uint SDRAM_CFG_ECC_EN_SHIFT = (31 - 2);
  56. static const uint SDRAM_CFG_RD_EN_SHIFT = (31 - 3);
  57. static const uint SDRAM_CFG_SDRAM_TYPE_SHIFT = (31 - 7);
  58. static const uint SDRAM_CFG_DYN_PWR_SHIFT = (31 - 10);
  59. static const uint SDRAM_CFG_DBW_SHIFT = (31 - 12);
  60. static const uint SDRAM_CFG_NCAP_SHIFT = (31 - 14);
  61. static const uint SDRAM_CFG_2T_EN_SHIFT = (31 - 16);
  62. static const uint SDRAM_CFG_BA_INTLV_CTL_SHIFT = (31 - 23);
  63. static const uint SDRAM_CFG_PCHB8_SHIFT = (31 - 27);
  64. static const uint SDRAM_CFG_HSE_SHIFT = (31 - 28);
  65. static const uint SDRAM_CFG_BI_SHIFT = (31 - 31);
  66. /* Shifts for the DDR SDRAM Control Configuration 2 register */
  67. static const uint SDRAM_CFG2_FRC_SR_SHIFT = (31 - 0);
  68. static const uint SDRAM_CFG2_DLL_RST_DIS = (31 - 2);
  69. static const uint SDRAM_CFG2_DQS_CFG = (31 - 5);
  70. static const uint SDRAM_CFG2_ODT_CFG = (31 - 10);
  71. static const uint SDRAM_CFG2_NUM_PR = (31 - 19);
  72. /* Shifts for the DDR SDRAM Mode register */
  73. static const uint SDRAM_MODE_ESD_SHIFT = (31 - 15);
  74. static const uint SDRAM_MODE_SD_SHIFT = (31 - 31);
  75. /* Shifts for the DDR SDRAM Mode 2 register */
  76. static const uint SDRAM_MODE2_ESD2_SHIFT = (31 - 15);
  77. static const uint SDRAM_MODE2_ESD3_SHIFT = (31 - 31);
  78. /* Shifts for the DDR SDRAM Interval Configuration register */
  79. static const uint SDRAM_INTERVAL_REFINT_SHIFT = (31 - 15);
  80. static const uint SDRAM_INTERVAL_BSTOPRE_SHIFT = (31 - 31);
  81. /* Mask for the DDR SDRAM Mode Control register */
  82. static const u32 SDRAM_CFG_MEM_EN = 0x80000000;
  83. int dram_init(void)
  84. {
  85. struct udevice *ram_ctrl;
  86. int ret;
  87. /* Current assumption: There is only one RAM controller */
  88. ret = uclass_first_device_err(UCLASS_RAM, &ram_ctrl);
  89. if (ret) {
  90. debug("%s: uclass_first_device_err failed: %d\n",
  91. __func__, ret);
  92. return ret;
  93. }
  94. /* FIXME(mario.six@gdsys.cc): Set gd->ram_size? */
  95. return 0;
  96. }
  97. phys_size_t get_effective_memsize(void)
  98. {
  99. if (!IS_ENABLED(CONFIG_VERY_BIG_RAM))
  100. return gd->ram_size;
  101. /* Limit stack to what we can reasonable map */
  102. return ((gd->ram_size > CONFIG_MAX_MEM_MAPPED) ?
  103. CONFIG_MAX_MEM_MAPPED : gd->ram_size);
  104. }
  105. /**
  106. * struct mpc83xx_sdram_priv - Private data for MPC83xx RAM controllers
  107. * @total_size: The total size of all RAM modules associated with this RAM
  108. * controller in bytes
  109. */
  110. struct mpc83xx_sdram_priv {
  111. ulong total_size;
  112. };
  113. /**
  114. * mpc83xx_sdram_static_init() - Statically initialize a RAM module.
  115. * @node: Device tree node associated with ths module in question
  116. * @cs: The chip select to use for this RAM module
  117. * @mapaddr: The address where the RAM module should be mapped
  118. * @size: The size of the RAM module to be mapped in bytes
  119. *
  120. * Return: 0 if OK, -ve on error
  121. */
  122. static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
  123. {
  124. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  125. u32 msize = size;
  126. u32 msize_log2 = __ilog2(msize);
  127. u32 auto_precharge, odt_rd_cfg, odt_wr_cfg, bank_bits, row_bits,
  128. col_bits;
  129. u32 bank_bits_mask, row_bits_mask, col_bits_mask;
  130. /* Configure the DDR local access window */
  131. out_be32(&im->sysconf.ddrlaw[cs].bar, mapaddr & 0xfffff000);
  132. out_be32(&im->sysconf.ddrlaw[cs].ar, LBLAWAR_EN | (msize_log2 - 1));
  133. out_be32(&im->ddr.csbnds[cs].csbnds, (msize - 1) >> 24);
  134. auto_precharge = ofnode_read_u32_default(node, "auto_precharge", 0);
  135. switch (auto_precharge) {
  136. case AUTO_PRECHARGE_ENABLE:
  137. case AUTO_PRECHARGE_DISABLE:
  138. break;
  139. default:
  140. debug("%s: auto_precharge value %d invalid.\n",
  141. ofnode_get_name(node), auto_precharge);
  142. return -EINVAL;
  143. }
  144. odt_rd_cfg = ofnode_read_u32_default(node, "odt_rd_cfg", 0);
  145. switch (odt_rd_cfg) {
  146. case ODT_RD_ONLY_OTHER_DIMM:
  147. if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
  148. !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
  149. debug("%s: odt_rd_cfg value %d invalid.\n",
  150. ofnode_get_name(node), odt_rd_cfg);
  151. return -EINVAL;
  152. }
  153. /* fall through */
  154. case ODT_RD_NEVER:
  155. case ODT_RD_ONLY_CURRENT:
  156. case ODT_RD_ONLY_OTHER_CS:
  157. if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
  158. !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
  159. !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
  160. !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
  161. debug("%s: odt_rd_cfg value %d invalid.\n",
  162. ofnode_get_name(node), odt_rd_cfg);
  163. return -EINVAL;
  164. }
  165. /* fall through */
  166. /* Only MPC832x knows this value */
  167. case ODT_RD_ALL:
  168. break;
  169. default:
  170. debug("%s: odt_rd_cfg value %d invalid.\n",
  171. ofnode_get_name(node), odt_rd_cfg);
  172. return -EINVAL;
  173. }
  174. odt_wr_cfg = ofnode_read_u32_default(node, "odt_wr_cfg", 0);
  175. switch (odt_wr_cfg) {
  176. case ODT_WR_ONLY_OTHER_DIMM:
  177. if (!IS_ENABLED(CONFIG_ARCH_MPC8360) &&
  178. !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
  179. debug("%s: odt_wr_cfg value %d invalid.\n",
  180. ofnode_get_name(node), odt_wr_cfg);
  181. return -EINVAL;
  182. }
  183. /* fall through */
  184. case ODT_WR_NEVER:
  185. case ODT_WR_ONLY_CURRENT:
  186. case ODT_WR_ONLY_OTHER_CS:
  187. if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
  188. !IS_ENABLED(CONFIG_ARCH_MPC831X) &&
  189. !IS_ENABLED(CONFIG_ARCH_MPC8360) &&
  190. !IS_ENABLED(CONFIG_ARCH_MPC837X)) {
  191. debug("%s: odt_wr_cfg value %d invalid.\n",
  192. ofnode_get_name(node), odt_wr_cfg);
  193. return -EINVAL;
  194. }
  195. /* fall through */
  196. /* MPC832x only knows this value */
  197. case ODT_WR_ALL:
  198. break;
  199. default:
  200. debug("%s: odt_wr_cfg value %d invalid.\n",
  201. ofnode_get_name(node), odt_wr_cfg);
  202. return -EINVAL;
  203. }
  204. bank_bits = ofnode_read_u32_default(node, "bank_bits", 0);
  205. switch (bank_bits) {
  206. case 2:
  207. bank_bits_mask = BANK_BITS_2;
  208. break;
  209. case 3:
  210. bank_bits_mask = BANK_BITS_3;
  211. break;
  212. default:
  213. debug("%s: bank_bits value %d invalid.\n",
  214. ofnode_get_name(node), bank_bits);
  215. return -EINVAL;
  216. }
  217. row_bits = ofnode_read_u32_default(node, "row_bits", 0);
  218. switch (row_bits) {
  219. case 12:
  220. row_bits_mask = ROW_BITS_12;
  221. break;
  222. case 13:
  223. row_bits_mask = ROW_BITS_13;
  224. break;
  225. case 14:
  226. row_bits_mask = ROW_BITS_14;
  227. break;
  228. default:
  229. debug("%s: row_bits value %d invalid.\n",
  230. ofnode_get_name(node), row_bits);
  231. return -EINVAL;
  232. }
  233. col_bits = ofnode_read_u32_default(node, "col_bits", 0);
  234. switch (col_bits) {
  235. case 8:
  236. col_bits_mask = COL_BITS_8;
  237. break;
  238. case 9:
  239. col_bits_mask = COL_BITS_9;
  240. break;
  241. case 10:
  242. col_bits_mask = COL_BITS_10;
  243. break;
  244. case 11:
  245. col_bits_mask = COL_BITS_11;
  246. break;
  247. default:
  248. debug("%s: col_bits value %d invalid.\n",
  249. ofnode_get_name(node), col_bits);
  250. return -EINVAL;
  251. }
  252. /* Write CS config value */
  253. out_be32(&im->ddr.cs_config[cs], CSCONFIG_ENABLE | auto_precharge |
  254. odt_rd_cfg | odt_wr_cfg |
  255. bank_bits_mask | row_bits_mask |
  256. col_bits_mask);
  257. return 0;
  258. }
  259. /**
  260. * mpc83xx_sdram_spd_init() - Initialize a RAM module using a SPD flash.
  261. * @node: Device tree node associated with ths module in question
  262. * @cs: The chip select to use for this RAM module
  263. * @mapaddr: The address where the RAM module should be mapped
  264. * @size: The size of the RAM module to be mapped in bytes
  265. *
  266. * Return: 0 if OK, -ve on error
  267. */
  268. static int mpc83xx_sdram_spd_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
  269. {
  270. /* TODO(mario.six@gdsys.cc): Implement */
  271. return 0;
  272. }
  273. static int mpc83xx_sdram_ofdata_to_platdata(struct udevice *dev)
  274. {
  275. return 0;
  276. }
  277. static int mpc83xx_sdram_probe(struct udevice *dev)
  278. {
  279. struct mpc83xx_sdram_priv *priv = dev_get_priv(dev);
  280. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  281. int ret = 0;
  282. ofnode subnode;
  283. /* DDR control driver register values */
  284. u32 dso, pz_override, nz_override, odt_term, ddr_type, mvref_sel, m_odr;
  285. u32 ddrcdr;
  286. /* DDR SDRAM Clock Control register values */
  287. u32 clock_adjust;
  288. /* DDR SDRAM Timing Configuration 3 register values */
  289. u32 ext_refresh_rec, ext_refresh_rec_mask;
  290. /* DDR SDRAM Timing Configuration 0 register values */
  291. u32 read_to_write, write_to_read, read_to_read, write_to_write,
  292. active_powerdown_exit, precharge_powerdown_exit,
  293. odt_powerdown_exit, mode_reg_set_cycle;
  294. u32 timing_cfg_0;
  295. /* DDR SDRAM Timing Configuration 1 register values */
  296. u32 precharge_to_activate, activate_to_precharge,
  297. activate_to_readwrite, mcas_latency, refresh_recovery,
  298. last_data_to_precharge, activate_to_activate,
  299. last_write_data_to_read;
  300. u32 timing_cfg_1;
  301. /* DDR SDRAM Timing Configuration 2 register values */
  302. u32 additive_latency, mcas_to_preamble_override, write_latency,
  303. read_to_precharge, write_cmd_to_write_data,
  304. minimum_cke_pulse_width, four_activates_window;
  305. u32 timing_cfg_2;
  306. /* DDR SDRAM Control Configuration register values */
  307. u32 self_refresh, ecc, registered_dram, sdram_type,
  308. dynamic_power_management, databus_width, nc_auto_precharge,
  309. timing_2t, bank_interleaving_ctrl, precharge_bit_8, half_strength,
  310. bypass_initialization;
  311. u32 sdram_cfg;
  312. /* DDR SDRAM Control Configuration 2 register values */
  313. u32 force_self_refresh, dll_reset, dqs_config, odt_config,
  314. posted_refreshes;
  315. u32 sdram_cfg2;
  316. /* DDR SDRAM Mode Configuration register values */
  317. u32 sdmode, esdmode;
  318. u32 sdram_mode;
  319. /* DDR SDRAM Mode Configuration 2 register values */
  320. u32 esdmode2, esdmode3;
  321. u32 sdram_mode2;
  322. /* DDR SDRAM Interval Configuration register values */
  323. u32 refresh_interval, precharge_interval;
  324. u32 sdram_interval;
  325. priv->total_size = 0;
  326. /* Disable both banks initially (might be re-enabled in loop below) */
  327. out_be32(&im->ddr.cs_config[0], 0);
  328. out_be32(&im->ddr.cs_config[1], 0);
  329. dso = dev_read_u32_default(dev, "driver_software_override", 0);
  330. if (dso > 1) {
  331. debug("%s: driver_software_override value %d invalid.\n",
  332. dev->name, dso);
  333. return -EINVAL;
  334. }
  335. pz_override = dev_read_u32_default(dev, "p_impedance_override", 0);
  336. switch (pz_override) {
  337. case DSO_P_IMPEDANCE_HIGHEST_Z:
  338. case DSO_P_IMPEDANCE_MUCH_HIGHER_Z:
  339. case DSO_P_IMPEDANCE_HIGHER_Z:
  340. case DSO_P_IMPEDANCE_NOMINAL:
  341. case DSO_P_IMPEDANCE_LOWER_Z:
  342. break;
  343. default:
  344. debug("%s: p_impedance_override value %d invalid.\n",
  345. dev->name, pz_override);
  346. return -EINVAL;
  347. }
  348. nz_override = dev_read_u32_default(dev, "n_impedance_override", 0);
  349. switch (nz_override) {
  350. case DSO_N_IMPEDANCE_HIGHEST_Z:
  351. case DSO_N_IMPEDANCE_MUCH_HIGHER_Z:
  352. case DSO_N_IMPEDANCE_HIGHER_Z:
  353. case DSO_N_IMPEDANCE_NOMINAL:
  354. case DSO_N_IMPEDANCE_LOWER_Z:
  355. break;
  356. default:
  357. debug("%s: n_impedance_override value %d invalid.\n",
  358. dev->name, nz_override);
  359. return -EINVAL;
  360. }
  361. odt_term = dev_read_u32_default(dev, "odt_termination_value", 0);
  362. if (odt_term > 1) {
  363. debug("%s: odt_termination_value value %d invalid.\n",
  364. dev->name, odt_term);
  365. return -EINVAL;
  366. }
  367. ddr_type = dev_read_u32_default(dev, "ddr_type", 0);
  368. if (ddr_type > 1) {
  369. debug("%s: ddr_type value %d invalid.\n",
  370. dev->name, ddr_type);
  371. return -EINVAL;
  372. }
  373. mvref_sel = dev_read_u32_default(dev, "mvref_sel", 0);
  374. if (mvref_sel > 1) {
  375. debug("%s: mvref_sel value %d invalid.\n",
  376. dev->name, mvref_sel);
  377. return -EINVAL;
  378. }
  379. m_odr = dev_read_u32_default(dev, "m_odr", 0);
  380. if (mvref_sel > 1) {
  381. debug("%s: m_odr value %d invalid.\n",
  382. dev->name, m_odr);
  383. return -EINVAL;
  384. }
  385. ddrcdr = dso << (31 - 1) |
  386. pz_override << (31 - 5) |
  387. nz_override << (31 - 9) |
  388. odt_term << (31 - 12) |
  389. ddr_type << (31 - 13) |
  390. mvref_sel << (31 - 29) |
  391. m_odr << (31 - 30) | 1;
  392. /* Configure the DDR control driver register */
  393. out_be32(&im->sysconf.ddrcdr, ddrcdr);
  394. dev_for_each_subnode(subnode, dev) {
  395. u32 val[3];
  396. u32 cs, addr, size;
  397. /* CS, map address, size -> three values */
  398. ofnode_read_u32_array(subnode, "reg", val, 3);
  399. cs = val[0];
  400. addr = val[1];
  401. size = val[2];
  402. if (cs > 1) {
  403. debug("%s: chip select value %d invalid.\n",
  404. dev->name, cs);
  405. return -EINVAL;
  406. }
  407. /* TODO(mario.six@gdsys.cc): Sanity check for size. */
  408. if (ofnode_read_bool(subnode, "read-spd"))
  409. ret = mpc83xx_sdram_spd_init(subnode, cs, addr, size);
  410. else
  411. ret = mpc83xx_sdram_static_init(subnode, cs, addr,
  412. size);
  413. if (ret) {
  414. debug("%s: RAM init failed.\n", dev->name);
  415. return ret;
  416. }
  417. };
  418. /*
  419. * TODO(mario.six@gdsys.cc): This should only occur for static
  420. * configuration
  421. */
  422. clock_adjust = dev_read_u32_default(dev, "clock_adjust", 0);
  423. switch (clock_adjust) {
  424. case CLOCK_ADJUST_025:
  425. case CLOCK_ADJUST_05:
  426. case CLOCK_ADJUST_075:
  427. case CLOCK_ADJUST_1:
  428. break;
  429. default:
  430. debug("%s: clock_adjust value %d invalid.\n",
  431. dev->name, clock_adjust);
  432. return -EINVAL;
  433. }
  434. /* Configure the DDR SDRAM Clock Control register */
  435. out_be32(&im->ddr.sdram_clk_cntl, clock_adjust);
  436. ext_refresh_rec = dev_read_u32_default(dev, "ext_refresh_rec", 0);
  437. switch (ext_refresh_rec) {
  438. case 0:
  439. ext_refresh_rec_mask = 0 << TIMING_CFG3_EXT_REFREC_SHIFT;
  440. break;
  441. case 16:
  442. ext_refresh_rec_mask = 1 << TIMING_CFG3_EXT_REFREC_SHIFT;
  443. break;
  444. case 32:
  445. ext_refresh_rec_mask = 2 << TIMING_CFG3_EXT_REFREC_SHIFT;
  446. break;
  447. case 48:
  448. ext_refresh_rec_mask = 3 << TIMING_CFG3_EXT_REFREC_SHIFT;
  449. break;
  450. case 64:
  451. ext_refresh_rec_mask = 4 << TIMING_CFG3_EXT_REFREC_SHIFT;
  452. break;
  453. case 80:
  454. ext_refresh_rec_mask = 5 << TIMING_CFG3_EXT_REFREC_SHIFT;
  455. break;
  456. case 96:
  457. ext_refresh_rec_mask = 6 << TIMING_CFG3_EXT_REFREC_SHIFT;
  458. break;
  459. case 112:
  460. ext_refresh_rec_mask = 7 << TIMING_CFG3_EXT_REFREC_SHIFT;
  461. break;
  462. default:
  463. debug("%s: ext_refresh_rec value %d invalid.\n",
  464. dev->name, ext_refresh_rec);
  465. return -EINVAL;
  466. }
  467. /* Configure the DDR SDRAM Timing Configuration 3 register */
  468. out_be32(&im->ddr.timing_cfg_3, ext_refresh_rec_mask);
  469. read_to_write = dev_read_u32_default(dev, "read_to_write", 0);
  470. if (read_to_write > 3) {
  471. debug("%s: read_to_write value %d invalid.\n",
  472. dev->name, read_to_write);
  473. return -EINVAL;
  474. }
  475. write_to_read = dev_read_u32_default(dev, "write_to_read", 0);
  476. if (write_to_read > 3) {
  477. debug("%s: write_to_read value %d invalid.\n",
  478. dev->name, write_to_read);
  479. return -EINVAL;
  480. }
  481. read_to_read = dev_read_u32_default(dev, "read_to_read", 0);
  482. if (read_to_read > 3) {
  483. debug("%s: read_to_read value %d invalid.\n",
  484. dev->name, read_to_read);
  485. return -EINVAL;
  486. }
  487. write_to_write = dev_read_u32_default(dev, "write_to_write", 0);
  488. if (write_to_write > 3) {
  489. debug("%s: write_to_write value %d invalid.\n",
  490. dev->name, write_to_write);
  491. return -EINVAL;
  492. }
  493. active_powerdown_exit =
  494. dev_read_u32_default(dev, "active_powerdown_exit", 0);
  495. if (active_powerdown_exit > 7) {
  496. debug("%s: active_powerdown_exit value %d invalid.\n",
  497. dev->name, active_powerdown_exit);
  498. return -EINVAL;
  499. }
  500. precharge_powerdown_exit =
  501. dev_read_u32_default(dev, "precharge_powerdown_exit", 0);
  502. if (precharge_powerdown_exit > 7) {
  503. debug("%s: precharge_powerdown_exit value %d invalid.\n",
  504. dev->name, precharge_powerdown_exit);
  505. return -EINVAL;
  506. }
  507. odt_powerdown_exit = dev_read_u32_default(dev, "odt_powerdown_exit", 0);
  508. if (odt_powerdown_exit > 15) {
  509. debug("%s: odt_powerdown_exit value %d invalid.\n",
  510. dev->name, odt_powerdown_exit);
  511. return -EINVAL;
  512. }
  513. mode_reg_set_cycle = dev_read_u32_default(dev, "mode_reg_set_cycle", 0);
  514. if (mode_reg_set_cycle > 15) {
  515. debug("%s: mode_reg_set_cycle value %d invalid.\n",
  516. dev->name, mode_reg_set_cycle);
  517. return -EINVAL;
  518. }
  519. timing_cfg_0 = read_to_write << TIMING_CFG0_RWT_SHIFT |
  520. write_to_read << TIMING_CFG0_WRT_SHIFT |
  521. read_to_read << TIMING_CFG0_RRT_SHIFT |
  522. write_to_write << TIMING_CFG0_WWT_SHIFT |
  523. active_powerdown_exit << TIMING_CFG0_ACT_PD_EXIT_SHIFT |
  524. precharge_powerdown_exit << TIMING_CFG0_PRE_PD_EXIT_SHIFT |
  525. odt_powerdown_exit << TIMING_CFG0_ODT_PD_EXIT_SHIFT |
  526. mode_reg_set_cycle << TIMING_CFG0_MRS_CYC_SHIFT;
  527. out_be32(&im->ddr.timing_cfg_0, timing_cfg_0);
  528. precharge_to_activate =
  529. dev_read_u32_default(dev, "precharge_to_activate", 0);
  530. if (precharge_to_activate > 7 || precharge_to_activate == 0) {
  531. debug("%s: precharge_to_activate value %d invalid.\n",
  532. dev->name, precharge_to_activate);
  533. return -EINVAL;
  534. }
  535. activate_to_precharge =
  536. dev_read_u32_default(dev, "activate_to_precharge", 0);
  537. if (activate_to_precharge > 19) {
  538. debug("%s: activate_to_precharge value %d invalid.\n",
  539. dev->name, activate_to_precharge);
  540. return -EINVAL;
  541. }
  542. activate_to_readwrite =
  543. dev_read_u32_default(dev, "activate_to_readwrite", 0);
  544. if (activate_to_readwrite > 7 || activate_to_readwrite == 0) {
  545. debug("%s: activate_to_readwrite value %d invalid.\n",
  546. dev->name, activate_to_readwrite);
  547. return -EINVAL;
  548. }
  549. mcas_latency = dev_read_u32_default(dev, "mcas_latency", 0);
  550. switch (mcas_latency) {
  551. case CASLAT_20:
  552. case CASLAT_25:
  553. if (!IS_ENABLED(CONFIG_ARCH_MPC8308)) {
  554. debug("%s: MCAS latency < 3.0 unsupported on MPC8308\n",
  555. dev->name);
  556. return -EINVAL;
  557. }
  558. /* fall through */
  559. case CASLAT_30:
  560. case CASLAT_35:
  561. case CASLAT_40:
  562. case CASLAT_45:
  563. case CASLAT_50:
  564. case CASLAT_55:
  565. case CASLAT_60:
  566. case CASLAT_65:
  567. case CASLAT_70:
  568. case CASLAT_75:
  569. case CASLAT_80:
  570. break;
  571. default:
  572. debug("%s: mcas_latency value %d invalid.\n",
  573. dev->name, mcas_latency);
  574. return -EINVAL;
  575. }
  576. refresh_recovery = dev_read_u32_default(dev, "refresh_recovery", 0);
  577. if (refresh_recovery > 23 || refresh_recovery < 8) {
  578. debug("%s: refresh_recovery value %d invalid.\n",
  579. dev->name, refresh_recovery);
  580. return -EINVAL;
  581. }
  582. last_data_to_precharge =
  583. dev_read_u32_default(dev, "last_data_to_precharge", 0);
  584. if (last_data_to_precharge > 7 || last_data_to_precharge == 0) {
  585. debug("%s: last_data_to_precharge value %d invalid.\n",
  586. dev->name, last_data_to_precharge);
  587. return -EINVAL;
  588. }
  589. activate_to_activate =
  590. dev_read_u32_default(dev, "activate_to_activate", 0);
  591. if (activate_to_activate > 7 || activate_to_activate == 0) {
  592. debug("%s: activate_to_activate value %d invalid.\n",
  593. dev->name, activate_to_activate);
  594. return -EINVAL;
  595. }
  596. last_write_data_to_read =
  597. dev_read_u32_default(dev, "last_write_data_to_read", 0);
  598. if (last_write_data_to_read > 7 || last_write_data_to_read == 0) {
  599. debug("%s: last_write_data_to_read value %d invalid.\n",
  600. dev->name, last_write_data_to_read);
  601. return -EINVAL;
  602. }
  603. timing_cfg_1 = precharge_to_activate << TIMING_CFG1_PRETOACT_SHIFT |
  604. (activate_to_precharge > 15 ?
  605. activate_to_precharge - 16 :
  606. activate_to_precharge) << TIMING_CFG1_ACTTOPRE_SHIFT |
  607. activate_to_readwrite << TIMING_CFG1_ACTTORW_SHIFT |
  608. mcas_latency << TIMING_CFG1_CASLAT_SHIFT |
  609. (refresh_recovery - 8) << TIMING_CFG1_REFREC_SHIFT |
  610. last_data_to_precharge << TIMING_CFG1_WRREC_SHIFT |
  611. activate_to_activate << TIMING_CFG1_ACTTOACT_SHIFT |
  612. last_write_data_to_read << TIMING_CFG1_WRTORD_SHIFT;
  613. /* Configure the DDR SDRAM Timing Configuration 1 register */
  614. out_be32(&im->ddr.timing_cfg_1, timing_cfg_1);
  615. additive_latency = dev_read_u32_default(dev, "additive_latency", 0);
  616. if (additive_latency > 5) {
  617. debug("%s: additive_latency value %d invalid.\n",
  618. dev->name, additive_latency);
  619. return -EINVAL;
  620. }
  621. mcas_to_preamble_override =
  622. dev_read_u32_default(dev, "mcas_to_preamble_override", 0);
  623. switch (mcas_to_preamble_override) {
  624. case READ_LAT_PLUS_1:
  625. case READ_LAT:
  626. case READ_LAT_PLUS_1_4:
  627. case READ_LAT_PLUS_1_2:
  628. case READ_LAT_PLUS_3_4:
  629. case READ_LAT_PLUS_5_4:
  630. case READ_LAT_PLUS_3_2:
  631. case READ_LAT_PLUS_7_4:
  632. case READ_LAT_PLUS_2:
  633. case READ_LAT_PLUS_9_4:
  634. case READ_LAT_PLUS_5_2:
  635. case READ_LAT_PLUS_11_4:
  636. case READ_LAT_PLUS_3:
  637. case READ_LAT_PLUS_13_4:
  638. case READ_LAT_PLUS_7_2:
  639. case READ_LAT_PLUS_15_4:
  640. case READ_LAT_PLUS_4:
  641. case READ_LAT_PLUS_17_4:
  642. case READ_LAT_PLUS_9_2:
  643. case READ_LAT_PLUS_19_4:
  644. break;
  645. default:
  646. debug("%s: mcas_to_preamble_override value %d invalid.\n",
  647. dev->name, mcas_to_preamble_override);
  648. return -EINVAL;
  649. }
  650. write_latency = dev_read_u32_default(dev, "write_latency", 0);
  651. if (write_latency > 7 || write_latency == 0) {
  652. debug("%s: write_latency value %d invalid.\n",
  653. dev->name, write_latency);
  654. return -EINVAL;
  655. }
  656. read_to_precharge = dev_read_u32_default(dev, "read_to_precharge", 0);
  657. if (read_to_precharge > 4 || read_to_precharge == 0) {
  658. debug("%s: read_to_precharge value %d invalid.\n",
  659. dev->name, read_to_precharge);
  660. return -EINVAL;
  661. }
  662. write_cmd_to_write_data =
  663. dev_read_u32_default(dev, "write_cmd_to_write_data", 0);
  664. switch (write_cmd_to_write_data) {
  665. case CLOCK_DELAY_0:
  666. case CLOCK_DELAY_1_4:
  667. case CLOCK_DELAY_1_2:
  668. case CLOCK_DELAY_3_4:
  669. case CLOCK_DELAY_1:
  670. case CLOCK_DELAY_5_4:
  671. case CLOCK_DELAY_3_2:
  672. break;
  673. default:
  674. debug("%s: write_cmd_to_write_data value %d invalid.\n",
  675. dev->name, write_cmd_to_write_data);
  676. return -EINVAL;
  677. }
  678. minimum_cke_pulse_width =
  679. dev_read_u32_default(dev, "minimum_cke_pulse_width", 0);
  680. if (minimum_cke_pulse_width > 4 || minimum_cke_pulse_width == 0) {
  681. debug("%s: minimum_cke_pulse_width value %d invalid.\n",
  682. dev->name, minimum_cke_pulse_width);
  683. return -EINVAL;
  684. }
  685. four_activates_window =
  686. dev_read_u32_default(dev, "four_activates_window", 0);
  687. if (four_activates_window > 20 || four_activates_window == 0) {
  688. debug("%s: four_activates_window value %d invalid.\n",
  689. dev->name, four_activates_window);
  690. return -EINVAL;
  691. }
  692. timing_cfg_2 = additive_latency << TIMING_CFG2_ADD_LAT_SHIFT |
  693. mcas_to_preamble_override << TIMING_CFG2_CPO_SHIFT |
  694. write_latency << TIMING_CFG2_WR_LAT_DELAY_SHIFT |
  695. read_to_precharge << TIMING_CFG2_RD_TO_PRE_SHIFT |
  696. write_cmd_to_write_data << TIMING_CFG2_WR_DATA_DELAY_SHIFT |
  697. minimum_cke_pulse_width << TIMING_CFG2_CKE_PLS_SHIFT |
  698. four_activates_window << TIMING_CFG2_FOUR_ACT_SHIFT;
  699. out_be32(&im->ddr.timing_cfg_2, timing_cfg_2);
  700. self_refresh = dev_read_u32_default(dev, "self_refresh", 0);
  701. switch (self_refresh) {
  702. case SREN_DISABLE:
  703. case SREN_ENABLE:
  704. break;
  705. default:
  706. debug("%s: self_refresh value %d invalid.\n",
  707. dev->name, self_refresh);
  708. return -EINVAL;
  709. }
  710. ecc = dev_read_u32_default(dev, "ecc", 0);
  711. switch (ecc) {
  712. case ECC_DISABLE:
  713. case ECC_ENABLE:
  714. break;
  715. default:
  716. debug("%s: ecc value %d invalid.\n", dev->name, ecc);
  717. return -EINVAL;
  718. }
  719. registered_dram = dev_read_u32_default(dev, "registered_dram", 0);
  720. switch (registered_dram) {
  721. case RD_DISABLE:
  722. case RD_ENABLE:
  723. break;
  724. default:
  725. debug("%s: registered_dram value %d invalid.\n",
  726. dev->name, registered_dram);
  727. return -EINVAL;
  728. }
  729. sdram_type = dev_read_u32_default(dev, "sdram_type", 0);
  730. switch (sdram_type) {
  731. case TYPE_DDR1:
  732. case TYPE_DDR2:
  733. break;
  734. default:
  735. debug("%s: sdram_type value %d invalid.\n",
  736. dev->name, sdram_type);
  737. return -EINVAL;
  738. }
  739. dynamic_power_management =
  740. dev_read_u32_default(dev, "dynamic_power_management", 0);
  741. switch (dynamic_power_management) {
  742. case DYN_PWR_DISABLE:
  743. case DYN_PWR_ENABLE:
  744. break;
  745. default:
  746. debug("%s: dynamic_power_management value %d invalid.\n",
  747. dev->name, dynamic_power_management);
  748. return -EINVAL;
  749. }
  750. databus_width = dev_read_u32_default(dev, "databus_width", 0);
  751. switch (databus_width) {
  752. case DATA_BUS_WIDTH_16:
  753. case DATA_BUS_WIDTH_32:
  754. break;
  755. default:
  756. debug("%s: databus_width value %d invalid.\n",
  757. dev->name, databus_width);
  758. return -EINVAL;
  759. }
  760. nc_auto_precharge = dev_read_u32_default(dev, "nc_auto_precharge", 0);
  761. switch (nc_auto_precharge) {
  762. case NCAP_DISABLE:
  763. case NCAP_ENABLE:
  764. break;
  765. default:
  766. debug("%s: nc_auto_precharge value %d invalid.\n",
  767. dev->name, nc_auto_precharge);
  768. return -EINVAL;
  769. }
  770. timing_2t = dev_read_u32_default(dev, "timing_2t", 0);
  771. switch (timing_2t) {
  772. case TIMING_1T:
  773. case TIMING_2T:
  774. break;
  775. default:
  776. debug("%s: timing_2t value %d invalid.\n",
  777. dev->name, timing_2t);
  778. return -EINVAL;
  779. }
  780. bank_interleaving_ctrl =
  781. dev_read_u32_default(dev, "bank_interleaving_ctrl", 0);
  782. switch (bank_interleaving_ctrl) {
  783. case INTERLEAVE_NONE:
  784. case INTERLEAVE_1_AND_2:
  785. break;
  786. default:
  787. debug("%s: bank_interleaving_ctrl value %d invalid.\n",
  788. dev->name, bank_interleaving_ctrl);
  789. return -EINVAL;
  790. }
  791. precharge_bit_8 = dev_read_u32_default(dev, "precharge_bit_8", 0);
  792. switch (precharge_bit_8) {
  793. case PRECHARGE_MA_10:
  794. case PRECHARGE_MA_8:
  795. break;
  796. default:
  797. debug("%s: precharge_bit_8 value %d invalid.\n",
  798. dev->name, precharge_bit_8);
  799. return -EINVAL;
  800. }
  801. half_strength = dev_read_u32_default(dev, "half_strength", 0);
  802. switch (half_strength) {
  803. case STRENGTH_FULL:
  804. case STRENGTH_HALF:
  805. break;
  806. default:
  807. debug("%s: half_strength value %d invalid.\n",
  808. dev->name, half_strength);
  809. return -EINVAL;
  810. }
  811. bypass_initialization =
  812. dev_read_u32_default(dev, "bypass_initialization", 0);
  813. switch (bypass_initialization) {
  814. case INITIALIZATION_DONT_BYPASS:
  815. case INITIALIZATION_BYPASS:
  816. break;
  817. default:
  818. debug("%s: bypass_initialization value %d invalid.\n",
  819. dev->name, bypass_initialization);
  820. return -EINVAL;
  821. }
  822. sdram_cfg = self_refresh << SDRAM_CFG_SREN_SHIFT |
  823. ecc << SDRAM_CFG_ECC_EN_SHIFT |
  824. registered_dram << SDRAM_CFG_RD_EN_SHIFT |
  825. sdram_type << SDRAM_CFG_SDRAM_TYPE_SHIFT |
  826. dynamic_power_management << SDRAM_CFG_DYN_PWR_SHIFT |
  827. databus_width << SDRAM_CFG_DBW_SHIFT |
  828. nc_auto_precharge << SDRAM_CFG_NCAP_SHIFT |
  829. timing_2t << SDRAM_CFG_2T_EN_SHIFT |
  830. bank_interleaving_ctrl << SDRAM_CFG_BA_INTLV_CTL_SHIFT |
  831. precharge_bit_8 << SDRAM_CFG_PCHB8_SHIFT |
  832. half_strength << SDRAM_CFG_HSE_SHIFT |
  833. bypass_initialization << SDRAM_CFG_BI_SHIFT;
  834. out_be32(&im->ddr.sdram_cfg, sdram_cfg);
  835. force_self_refresh = dev_read_u32_default(dev, "force_self_refresh", 0);
  836. switch (force_self_refresh) {
  837. case MODE_NORMAL:
  838. case MODE_REFRESH:
  839. break;
  840. default:
  841. debug("%s: force_self_refresh value %d invalid.\n",
  842. dev->name, force_self_refresh);
  843. return -EINVAL;
  844. }
  845. dll_reset = dev_read_u32_default(dev, "dll_reset", 0);
  846. switch (dll_reset) {
  847. case DLL_RESET_ENABLE:
  848. case DLL_RESET_DISABLE:
  849. break;
  850. default:
  851. debug("%s: dll_reset value %d invalid.\n",
  852. dev->name, dll_reset);
  853. return -EINVAL;
  854. }
  855. dqs_config = dev_read_u32_default(dev, "dqs_config", 0);
  856. switch (dqs_config) {
  857. case DQS_TRUE:
  858. break;
  859. default:
  860. debug("%s: dqs_config value %d invalid.\n",
  861. dev->name, dqs_config);
  862. return -EINVAL;
  863. }
  864. odt_config = dev_read_u32_default(dev, "odt_config", 0);
  865. switch (odt_config) {
  866. case ODT_ASSERT_NEVER:
  867. case ODT_ASSERT_WRITES:
  868. case ODT_ASSERT_READS:
  869. case ODT_ASSERT_ALWAYS:
  870. break;
  871. default:
  872. debug("%s: odt_config value %d invalid.\n",
  873. dev->name, odt_config);
  874. return -EINVAL;
  875. }
  876. posted_refreshes = dev_read_u32_default(dev, "posted_refreshes", 0);
  877. if (posted_refreshes > 8 || posted_refreshes == 0) {
  878. debug("%s: posted_refreshes value %d invalid.\n",
  879. dev->name, posted_refreshes);
  880. return -EINVAL;
  881. }
  882. sdram_cfg2 = force_self_refresh << SDRAM_CFG2_FRC_SR_SHIFT |
  883. dll_reset << SDRAM_CFG2_DLL_RST_DIS |
  884. dqs_config << SDRAM_CFG2_DQS_CFG |
  885. odt_config << SDRAM_CFG2_ODT_CFG |
  886. posted_refreshes << SDRAM_CFG2_NUM_PR;
  887. out_be32(&im->ddr.sdram_cfg2, sdram_cfg2);
  888. sdmode = dev_read_u32_default(dev, "sdmode", 0);
  889. if (sdmode > 0xFFFF) {
  890. debug("%s: sdmode value %d invalid.\n",
  891. dev->name, sdmode);
  892. return -EINVAL;
  893. }
  894. esdmode = dev_read_u32_default(dev, "esdmode", 0);
  895. if (esdmode > 0xFFFF) {
  896. debug("%s: esdmode value %d invalid.\n", dev->name, esdmode);
  897. return -EINVAL;
  898. }
  899. sdram_mode = sdmode << SDRAM_MODE_SD_SHIFT |
  900. esdmode << SDRAM_MODE_ESD_SHIFT;
  901. out_be32(&im->ddr.sdram_mode, sdram_mode);
  902. esdmode2 = dev_read_u32_default(dev, "esdmode2", 0);
  903. if (esdmode2 > 0xFFFF) {
  904. debug("%s: esdmode2 value %d invalid.\n", dev->name, esdmode2);
  905. return -EINVAL;
  906. }
  907. esdmode3 = dev_read_u32_default(dev, "esdmode3", 0);
  908. if (esdmode3 > 0xFFFF) {
  909. debug("%s: esdmode3 value %d invalid.\n", dev->name, esdmode3);
  910. return -EINVAL;
  911. }
  912. sdram_mode2 = esdmode2 << SDRAM_MODE2_ESD2_SHIFT |
  913. esdmode3 << SDRAM_MODE2_ESD3_SHIFT;
  914. out_be32(&im->ddr.sdram_mode2, sdram_mode2);
  915. refresh_interval = dev_read_u32_default(dev, "refresh_interval", 0);
  916. if (refresh_interval > 0xFFFF) {
  917. debug("%s: refresh_interval value %d invalid.\n",
  918. dev->name, refresh_interval);
  919. return -EINVAL;
  920. }
  921. precharge_interval = dev_read_u32_default(dev, "precharge_interval", 0);
  922. if (precharge_interval > 0x3FFF) {
  923. debug("%s: precharge_interval value %d invalid.\n",
  924. dev->name, precharge_interval);
  925. return -EINVAL;
  926. }
  927. sdram_interval = refresh_interval << SDRAM_INTERVAL_REFINT_SHIFT |
  928. precharge_interval << SDRAM_INTERVAL_BSTOPRE_SHIFT;
  929. out_be32(&im->ddr.sdram_interval, sdram_interval);
  930. sync();
  931. /* Enable DDR controller */
  932. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  933. sync();
  934. dev_for_each_subnode(subnode, dev) {
  935. u32 val[3];
  936. u32 addr, size;
  937. /* CS, map address, size -> three values */
  938. ofnode_read_u32_array(subnode, "reg", val, 3);
  939. addr = val[1];
  940. size = val[2];
  941. priv->total_size += get_ram_size((long int *)addr, size);
  942. };
  943. gd->ram_size = priv->total_size;
  944. return 0;
  945. }
  946. static int mpc83xx_sdram_get_info(struct udevice *dev, struct ram_info *info)
  947. {
  948. /* TODO(mario.six@gdsys.cc): Implement */
  949. return 0;
  950. }
  951. static struct ram_ops mpc83xx_sdram_ops = {
  952. .get_info = mpc83xx_sdram_get_info,
  953. };
  954. static const struct udevice_id mpc83xx_sdram_ids[] = {
  955. { .compatible = "fsl,mpc83xx-mem-controller" },
  956. { /* sentinel */ }
  957. };
  958. U_BOOT_DRIVER(mpc83xx_sdram) = {
  959. .name = "mpc83xx_sdram",
  960. .id = UCLASS_RAM,
  961. .of_match = mpc83xx_sdram_ids,
  962. .ops = &mpc83xx_sdram_ops,
  963. .ofdata_to_platdata = mpc83xx_sdram_ofdata_to_platdata,
  964. .probe = mpc83xx_sdram_probe,
  965. .priv_auto_alloc_size = sizeof(struct mpc83xx_sdram_priv),
  966. };