bmips_ram.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Álvaro Fernández Rojas <noltari@gmail.com>
  4. *
  5. * Derived from linux/arch/mips/bcm63xx/cpu.c:
  6. * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
  7. * Copyright (C) 2009 Florian Fainelli <florian@openwrt.org>
  8. */
  9. #include <common.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <init.h>
  13. #include <ram.h>
  14. #include <asm/io.h>
  15. #define SDRAM_CFG_REG 0x0
  16. #define SDRAM_CFG_COL_SHIFT 4
  17. #define SDRAM_CFG_COL_MASK (0x3 << SDRAM_CFG_COL_SHIFT)
  18. #define SDRAM_CFG_ROW_SHIFT 6
  19. #define SDRAM_CFG_ROW_MASK (0x3 << SDRAM_CFG_ROW_SHIFT)
  20. #define SDRAM_CFG_32B_SHIFT 10
  21. #define SDRAM_CFG_32B_MASK (1 << SDRAM_CFG_32B_SHIFT)
  22. #define SDRAM_CFG_BANK_SHIFT 13
  23. #define SDRAM_CFG_BANK_MASK (1 << SDRAM_CFG_BANK_SHIFT)
  24. #define SDRAM_6318_SPACE_SHIFT 4
  25. #define SDRAM_6318_SPACE_MASK (0xf << SDRAM_6318_SPACE_SHIFT)
  26. #define MEMC_CFG_REG 0x4
  27. #define MEMC_CFG_32B_SHIFT 1
  28. #define MEMC_CFG_32B_MASK (1 << MEMC_CFG_32B_SHIFT)
  29. #define MEMC_CFG_COL_SHIFT 3
  30. #define MEMC_CFG_COL_MASK (0x3 << MEMC_CFG_COL_SHIFT)
  31. #define MEMC_CFG_ROW_SHIFT 6
  32. #define MEMC_CFG_ROW_MASK (0x3 << MEMC_CFG_ROW_SHIFT)
  33. #define DDR_CSEND_REG 0x8
  34. struct bmips_ram_priv;
  35. struct bmips_ram_hw {
  36. ulong (*get_ram_size)(struct bmips_ram_priv *);
  37. };
  38. struct bmips_ram_priv {
  39. void __iomem *regs;
  40. u32 force_size;
  41. const struct bmips_ram_hw *hw;
  42. };
  43. static ulong bcm6318_get_ram_size(struct bmips_ram_priv *priv)
  44. {
  45. u32 val;
  46. val = readl_be(priv->regs + SDRAM_CFG_REG);
  47. val = (val & SDRAM_6318_SPACE_MASK) >> SDRAM_6318_SPACE_SHIFT;
  48. return (1 << (val + 20));
  49. }
  50. static ulong bcm6328_get_ram_size(struct bmips_ram_priv *priv)
  51. {
  52. return readl_be(priv->regs + DDR_CSEND_REG) << 24;
  53. }
  54. static ulong bmips_dram_size(unsigned int cols, unsigned int rows,
  55. unsigned int is_32b, unsigned int banks)
  56. {
  57. rows += 11; /* 0 => 11 address bits ... 2 => 13 address bits */
  58. cols += 8; /* 0 => 8 address bits ... 2 => 10 address bits */
  59. is_32b += 1;
  60. return 1 << (cols + rows + is_32b + banks);
  61. }
  62. static ulong bcm6338_get_ram_size(struct bmips_ram_priv *priv)
  63. {
  64. unsigned int cols = 0, rows = 0, is_32b = 0, banks = 0;
  65. u32 val;
  66. val = readl_be(priv->regs + SDRAM_CFG_REG);
  67. rows = (val & SDRAM_CFG_ROW_MASK) >> SDRAM_CFG_ROW_SHIFT;
  68. cols = (val & SDRAM_CFG_COL_MASK) >> SDRAM_CFG_COL_SHIFT;
  69. is_32b = (val & SDRAM_CFG_32B_MASK) ? 1 : 0;
  70. banks = (val & SDRAM_CFG_BANK_MASK) ? 2 : 1;
  71. return bmips_dram_size(cols, rows, is_32b, banks);
  72. }
  73. static ulong bcm6358_get_ram_size(struct bmips_ram_priv *priv)
  74. {
  75. unsigned int cols = 0, rows = 0, is_32b = 0;
  76. u32 val;
  77. val = readl_be(priv->regs + MEMC_CFG_REG);
  78. rows = (val & MEMC_CFG_ROW_MASK) >> MEMC_CFG_ROW_SHIFT;
  79. cols = (val & MEMC_CFG_COL_MASK) >> MEMC_CFG_COL_SHIFT;
  80. is_32b = (val & MEMC_CFG_32B_MASK) ? 0 : 1;
  81. return bmips_dram_size(cols, rows, is_32b, 2);
  82. }
  83. static int bmips_ram_get_info(struct udevice *dev, struct ram_info *info)
  84. {
  85. struct bmips_ram_priv *priv = dev_get_priv(dev);
  86. const struct bmips_ram_hw *hw = priv->hw;
  87. info->base = 0x80000000;
  88. if (priv->force_size)
  89. info->size = priv->force_size;
  90. else
  91. info->size = hw->get_ram_size(priv);
  92. return 0;
  93. }
  94. static const struct ram_ops bmips_ram_ops = {
  95. .get_info = bmips_ram_get_info,
  96. };
  97. static const struct bmips_ram_hw bmips_ram_bcm6318 = {
  98. .get_ram_size = bcm6318_get_ram_size,
  99. };
  100. static const struct bmips_ram_hw bmips_ram_bcm6328 = {
  101. .get_ram_size = bcm6328_get_ram_size,
  102. };
  103. static const struct bmips_ram_hw bmips_ram_bcm6338 = {
  104. .get_ram_size = bcm6338_get_ram_size,
  105. };
  106. static const struct bmips_ram_hw bmips_ram_bcm6358 = {
  107. .get_ram_size = bcm6358_get_ram_size,
  108. };
  109. static const struct udevice_id bmips_ram_ids[] = {
  110. {
  111. .compatible = "brcm,bcm6318-mc",
  112. .data = (ulong)&bmips_ram_bcm6318,
  113. }, {
  114. .compatible = "brcm,bcm6328-mc",
  115. .data = (ulong)&bmips_ram_bcm6328,
  116. }, {
  117. .compatible = "brcm,bcm6338-mc",
  118. .data = (ulong)&bmips_ram_bcm6338,
  119. }, {
  120. .compatible = "brcm,bcm6358-mc",
  121. .data = (ulong)&bmips_ram_bcm6358,
  122. }, { /* sentinel */ }
  123. };
  124. static int bmips_ram_probe(struct udevice *dev)
  125. {
  126. struct bmips_ram_priv *priv = dev_get_priv(dev);
  127. const struct bmips_ram_hw *hw =
  128. (const struct bmips_ram_hw *)dev_get_driver_data(dev);
  129. priv->regs = dev_remap_addr(dev);
  130. if (!priv->regs)
  131. return -EINVAL;
  132. dev_read_u32(dev, "force-size", &priv->force_size);
  133. priv->hw = hw;
  134. return 0;
  135. }
  136. U_BOOT_DRIVER(bmips_ram) = {
  137. .name = "bmips-mc",
  138. .id = UCLASS_RAM,
  139. .of_match = bmips_ram_ids,
  140. .probe = bmips_ram_probe,
  141. .priv_auto_alloc_size = sizeof(struct bmips_ram_priv),
  142. .ops = &bmips_ram_ops,
  143. };