tegra_pwm.c 2.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2016 Google Inc.
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <log.h>
  8. #include <pwm.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch/pwm.h>
  12. struct tegra_pwm_priv {
  13. struct pwm_ctlr *regs;
  14. };
  15. static int tegra_pwm_set_config(struct udevice *dev, uint channel,
  16. uint period_ns, uint duty_ns)
  17. {
  18. struct tegra_pwm_priv *priv = dev_get_priv(dev);
  19. struct pwm_ctlr *regs = priv->regs;
  20. uint pulse_width;
  21. u32 reg;
  22. if (channel >= 4)
  23. return -EINVAL;
  24. debug("%s: Configure '%s' channel %u\n", __func__, dev->name, channel);
  25. /* We ignore the period here and just use 32KHz */
  26. clock_start_periph_pll(PERIPH_ID_PWM, CLOCK_ID_SFROM32KHZ, 32768);
  27. pulse_width = duty_ns * 255 / period_ns;
  28. reg = pulse_width << PWM_WIDTH_SHIFT;
  29. reg |= 1 << PWM_DIVIDER_SHIFT;
  30. writel(reg, &regs[channel].control);
  31. debug("%s: pulse_width=%u\n", __func__, pulse_width);
  32. return 0;
  33. }
  34. static int tegra_pwm_set_enable(struct udevice *dev, uint channel, bool enable)
  35. {
  36. struct tegra_pwm_priv *priv = dev_get_priv(dev);
  37. struct pwm_ctlr *regs = priv->regs;
  38. if (channel >= 4)
  39. return -EINVAL;
  40. debug("%s: Enable '%s' channel %u\n", __func__, dev->name, channel);
  41. clrsetbits_le32(&regs[channel].control, PWM_ENABLE_MASK,
  42. enable ? PWM_ENABLE_MASK : 0);
  43. return 0;
  44. }
  45. static int tegra_pwm_ofdata_to_platdata(struct udevice *dev)
  46. {
  47. struct tegra_pwm_priv *priv = dev_get_priv(dev);
  48. priv->regs = (struct pwm_ctlr *)dev_read_addr(dev);
  49. return 0;
  50. }
  51. static const struct pwm_ops tegra_pwm_ops = {
  52. .set_config = tegra_pwm_set_config,
  53. .set_enable = tegra_pwm_set_enable,
  54. };
  55. static const struct udevice_id tegra_pwm_ids[] = {
  56. { .compatible = "nvidia,tegra124-pwm" },
  57. { .compatible = "nvidia,tegra20-pwm" },
  58. { }
  59. };
  60. U_BOOT_DRIVER(tegra_pwm) = {
  61. .name = "tegra_pwm",
  62. .id = UCLASS_PWM,
  63. .of_match = tegra_pwm_ids,
  64. .ops = &tegra_pwm_ops,
  65. .ofdata_to_platdata = tegra_pwm_ofdata_to_platdata,
  66. .priv_auto_alloc_size = sizeof(struct tegra_pwm_priv),
  67. };