meson-ee-pwrc.c 11 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2019 BayLibre, SAS
  4. * Author: Neil Armstrong <narmstrong@baylibre.com>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <log.h>
  9. #include <malloc.h>
  10. #include <power-domain-uclass.h>
  11. #include <regmap.h>
  12. #include <syscon.h>
  13. #include <reset.h>
  14. #include <clk.h>
  15. #include <dt-bindings/power/meson-g12a-power.h>
  16. #include <dt-bindings/power/meson-sm1-power.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <linux/err.h>
  20. /* AO Offsets */
  21. #define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
  22. #define AO_RTI_GEN_PWR_ISO0 (0x3b << 2)
  23. /* HHI Offsets */
  24. #define HHI_MEM_PD_REG0 (0x40 << 2)
  25. #define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
  26. #define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
  27. #define HHI_VPU_MEM_PD_REG3 (0x43 << 2)
  28. #define HHI_VPU_MEM_PD_REG4 (0x44 << 2)
  29. #define HHI_AUDIO_MEM_PD_REG0 (0x45 << 2)
  30. #define HHI_NANOQ_MEM_PD_REG0 (0x46 << 2)
  31. #define HHI_NANOQ_MEM_PD_REG1 (0x47 << 2)
  32. #define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
  33. struct meson_ee_pwrc;
  34. struct meson_ee_pwrc_domain;
  35. struct meson_ee_pwrc_mem_domain {
  36. unsigned int reg;
  37. unsigned int mask;
  38. };
  39. struct meson_ee_pwrc_top_domain {
  40. unsigned int sleep_reg;
  41. unsigned int sleep_mask;
  42. unsigned int iso_reg;
  43. unsigned int iso_mask;
  44. };
  45. struct meson_ee_pwrc_domain_desc {
  46. char *name;
  47. unsigned int reset_names_count;
  48. unsigned int clk_names_count;
  49. struct meson_ee_pwrc_top_domain *top_pd;
  50. unsigned int mem_pd_count;
  51. struct meson_ee_pwrc_mem_domain *mem_pd;
  52. bool (*get_power)(struct power_domain *power_domain);
  53. };
  54. struct meson_ee_pwrc_domain_data {
  55. unsigned int count;
  56. struct meson_ee_pwrc_domain_desc *domains;
  57. };
  58. /* TOP Power Domains */
  59. static struct meson_ee_pwrc_top_domain g12a_pwrc_vpu = {
  60. .sleep_reg = AO_RTI_GEN_PWR_SLEEP0,
  61. .sleep_mask = BIT(8),
  62. .iso_reg = AO_RTI_GEN_PWR_SLEEP0,
  63. .iso_mask = BIT(9),
  64. };
  65. #define SM1_EE_PD(__bit) \
  66. { \
  67. .sleep_reg = AO_RTI_GEN_PWR_SLEEP0, \
  68. .sleep_mask = BIT(__bit), \
  69. .iso_reg = AO_RTI_GEN_PWR_ISO0, \
  70. .iso_mask = BIT(__bit), \
  71. }
  72. static struct meson_ee_pwrc_top_domain sm1_pwrc_vpu = SM1_EE_PD(8);
  73. static struct meson_ee_pwrc_top_domain sm1_pwrc_nna = SM1_EE_PD(16);
  74. static struct meson_ee_pwrc_top_domain sm1_pwrc_usb = SM1_EE_PD(17);
  75. static struct meson_ee_pwrc_top_domain sm1_pwrc_pci = SM1_EE_PD(18);
  76. static struct meson_ee_pwrc_top_domain sm1_pwrc_ge2d = SM1_EE_PD(19);
  77. /* Memory PD Domains */
  78. #define VPU_MEMPD(__reg) \
  79. { __reg, GENMASK(1, 0) }, \
  80. { __reg, GENMASK(3, 2) }, \
  81. { __reg, GENMASK(5, 4) }, \
  82. { __reg, GENMASK(7, 6) }, \
  83. { __reg, GENMASK(9, 8) }, \
  84. { __reg, GENMASK(11, 10) }, \
  85. { __reg, GENMASK(13, 12) }, \
  86. { __reg, GENMASK(15, 14) }, \
  87. { __reg, GENMASK(17, 16) }, \
  88. { __reg, GENMASK(19, 18) }, \
  89. { __reg, GENMASK(21, 20) }, \
  90. { __reg, GENMASK(23, 22) }, \
  91. { __reg, GENMASK(25, 24) }, \
  92. { __reg, GENMASK(27, 26) }, \
  93. { __reg, GENMASK(29, 28) }, \
  94. { __reg, GENMASK(31, 30) }
  95. #define VPU_HHI_MEMPD(__reg) \
  96. { __reg, BIT(8) }, \
  97. { __reg, BIT(9) }, \
  98. { __reg, BIT(10) }, \
  99. { __reg, BIT(11) }, \
  100. { __reg, BIT(12) }, \
  101. { __reg, BIT(13) }, \
  102. { __reg, BIT(14) }, \
  103. { __reg, BIT(15) }
  104. static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_vpu[] = {
  105. VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
  106. VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
  107. VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
  108. VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
  109. };
  110. static struct meson_ee_pwrc_mem_domain g12a_pwrc_mem_eth[] = {
  111. { HHI_MEM_PD_REG0, GENMASK(3, 2) },
  112. };
  113. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_vpu[] = {
  114. VPU_MEMPD(HHI_VPU_MEM_PD_REG0),
  115. VPU_MEMPD(HHI_VPU_MEM_PD_REG1),
  116. VPU_MEMPD(HHI_VPU_MEM_PD_REG2),
  117. VPU_MEMPD(HHI_VPU_MEM_PD_REG3),
  118. { HHI_VPU_MEM_PD_REG4, GENMASK(1, 0) },
  119. { HHI_VPU_MEM_PD_REG4, GENMASK(3, 2) },
  120. { HHI_VPU_MEM_PD_REG4, GENMASK(5, 4) },
  121. { HHI_VPU_MEM_PD_REG4, GENMASK(7, 6) },
  122. VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
  123. };
  124. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_nna[] = {
  125. { HHI_NANOQ_MEM_PD_REG0, 0xff },
  126. { HHI_NANOQ_MEM_PD_REG1, 0xff },
  127. };
  128. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_usb[] = {
  129. { HHI_MEM_PD_REG0, GENMASK(31, 30) },
  130. };
  131. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_pcie[] = {
  132. { HHI_MEM_PD_REG0, GENMASK(29, 26) },
  133. };
  134. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_ge2d[] = {
  135. { HHI_MEM_PD_REG0, GENMASK(25, 18) },
  136. };
  137. static struct meson_ee_pwrc_mem_domain sm1_pwrc_mem_audio[] = {
  138. { HHI_MEM_PD_REG0, GENMASK(5, 4) },
  139. { HHI_AUDIO_MEM_PD_REG0, GENMASK(1, 0) },
  140. { HHI_AUDIO_MEM_PD_REG0, GENMASK(3, 2) },
  141. { HHI_AUDIO_MEM_PD_REG0, GENMASK(5, 4) },
  142. { HHI_AUDIO_MEM_PD_REG0, GENMASK(7, 6) },
  143. { HHI_AUDIO_MEM_PD_REG0, GENMASK(13, 12) },
  144. { HHI_AUDIO_MEM_PD_REG0, GENMASK(15, 14) },
  145. { HHI_AUDIO_MEM_PD_REG0, GENMASK(17, 16) },
  146. { HHI_AUDIO_MEM_PD_REG0, GENMASK(19, 18) },
  147. { HHI_AUDIO_MEM_PD_REG0, GENMASK(21, 20) },
  148. { HHI_AUDIO_MEM_PD_REG0, GENMASK(23, 22) },
  149. { HHI_AUDIO_MEM_PD_REG0, GENMASK(25, 24) },
  150. { HHI_AUDIO_MEM_PD_REG0, GENMASK(27, 26) },
  151. };
  152. #define VPU_PD(__name, __top_pd, __mem, __get_power, __resets, __clks) \
  153. { \
  154. .name = __name, \
  155. .reset_names_count = __resets, \
  156. .clk_names_count = __clks, \
  157. .top_pd = __top_pd, \
  158. .mem_pd_count = ARRAY_SIZE(__mem), \
  159. .mem_pd = __mem, \
  160. .get_power = __get_power, \
  161. }
  162. #define TOP_PD(__name, __top_pd, __mem, __get_power) \
  163. { \
  164. .name = __name, \
  165. .top_pd = __top_pd, \
  166. .mem_pd_count = ARRAY_SIZE(__mem), \
  167. .mem_pd = __mem, \
  168. .get_power = __get_power, \
  169. }
  170. #define MEM_PD(__name, __mem) \
  171. TOP_PD(__name, NULL, __mem, NULL)
  172. static bool pwrc_ee_get_power(struct power_domain *power_domain);
  173. static struct meson_ee_pwrc_domain_desc g12a_pwrc_domains[] = {
  174. [PWRC_G12A_VPU_ID] = VPU_PD("VPU", &g12a_pwrc_vpu, g12a_pwrc_mem_vpu,
  175. pwrc_ee_get_power, 11, 2),
  176. [PWRC_G12A_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
  177. };
  178. static struct meson_ee_pwrc_domain_desc sm1_pwrc_domains[] = {
  179. [PWRC_SM1_VPU_ID] = VPU_PD("VPU", &sm1_pwrc_vpu, sm1_pwrc_mem_vpu,
  180. pwrc_ee_get_power, 11, 2),
  181. [PWRC_SM1_NNA_ID] = TOP_PD("NNA", &sm1_pwrc_nna, sm1_pwrc_mem_nna,
  182. pwrc_ee_get_power),
  183. [PWRC_SM1_USB_ID] = TOP_PD("USB", &sm1_pwrc_usb, sm1_pwrc_mem_usb,
  184. pwrc_ee_get_power),
  185. [PWRC_SM1_PCIE_ID] = TOP_PD("PCI", &sm1_pwrc_pci, sm1_pwrc_mem_pcie,
  186. pwrc_ee_get_power),
  187. [PWRC_SM1_GE2D_ID] = TOP_PD("GE2D", &sm1_pwrc_ge2d, sm1_pwrc_mem_ge2d,
  188. pwrc_ee_get_power),
  189. [PWRC_SM1_AUDIO_ID] = MEM_PD("AUDIO", sm1_pwrc_mem_audio),
  190. [PWRC_SM1_ETH_ID] = MEM_PD("ETH", g12a_pwrc_mem_eth),
  191. };
  192. struct meson_ee_pwrc_priv {
  193. struct regmap *regmap_ao;
  194. struct regmap *regmap_hhi;
  195. struct reset_ctl_bulk resets;
  196. struct clk_bulk clks;
  197. const struct meson_ee_pwrc_domain_data *data;
  198. };
  199. static bool pwrc_ee_get_power(struct power_domain *power_domain)
  200. {
  201. struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
  202. struct meson_ee_pwrc_domain_desc *pwrc_domain;
  203. u32 reg;
  204. pwrc_domain = &priv->data->domains[power_domain->id];
  205. regmap_read(priv->regmap_ao,
  206. pwrc_domain->top_pd->sleep_reg, &reg);
  207. return (reg & pwrc_domain->top_pd->sleep_mask);
  208. }
  209. static int meson_ee_pwrc_request(struct power_domain *power_domain)
  210. {
  211. return 0;
  212. }
  213. static int meson_ee_pwrc_free(struct power_domain *power_domain)
  214. {
  215. return 0;
  216. }
  217. static int meson_ee_pwrc_off(struct power_domain *power_domain)
  218. {
  219. struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
  220. struct meson_ee_pwrc_domain_desc *pwrc_domain;
  221. int i;
  222. pwrc_domain = &priv->data->domains[power_domain->id];
  223. if (pwrc_domain->top_pd)
  224. regmap_update_bits(priv->regmap_ao,
  225. pwrc_domain->top_pd->sleep_reg,
  226. pwrc_domain->top_pd->sleep_mask,
  227. pwrc_domain->top_pd->sleep_mask);
  228. udelay(20);
  229. for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
  230. regmap_update_bits(priv->regmap_hhi,
  231. pwrc_domain->mem_pd[i].reg,
  232. pwrc_domain->mem_pd[i].mask,
  233. pwrc_domain->mem_pd[i].mask);
  234. udelay(20);
  235. if (pwrc_domain->top_pd)
  236. regmap_update_bits(priv->regmap_ao,
  237. pwrc_domain->top_pd->iso_reg,
  238. pwrc_domain->top_pd->iso_mask,
  239. pwrc_domain->top_pd->iso_mask);
  240. if (pwrc_domain->clk_names_count) {
  241. mdelay(20);
  242. clk_disable_bulk(&priv->clks);
  243. }
  244. return 0;
  245. }
  246. static int meson_ee_pwrc_on(struct power_domain *power_domain)
  247. {
  248. struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
  249. struct meson_ee_pwrc_domain_desc *pwrc_domain;
  250. int i, ret;
  251. pwrc_domain = &priv->data->domains[power_domain->id];
  252. if (pwrc_domain->top_pd)
  253. regmap_update_bits(priv->regmap_ao,
  254. pwrc_domain->top_pd->sleep_reg,
  255. pwrc_domain->top_pd->sleep_mask, 0);
  256. udelay(20);
  257. for (i = 0 ; i < pwrc_domain->mem_pd_count ; ++i)
  258. regmap_update_bits(priv->regmap_hhi,
  259. pwrc_domain->mem_pd[i].reg,
  260. pwrc_domain->mem_pd[i].mask, 0);
  261. udelay(20);
  262. if (pwrc_domain->reset_names_count) {
  263. ret = reset_assert_bulk(&priv->resets);
  264. if (ret)
  265. return ret;
  266. }
  267. if (pwrc_domain->top_pd)
  268. regmap_update_bits(priv->regmap_ao,
  269. pwrc_domain->top_pd->iso_reg,
  270. pwrc_domain->top_pd->iso_mask, 0);
  271. if (pwrc_domain->reset_names_count) {
  272. ret = reset_deassert_bulk(&priv->resets);
  273. if (ret)
  274. return ret;
  275. }
  276. if (pwrc_domain->clk_names_count)
  277. return clk_enable_bulk(&priv->clks);
  278. return 0;
  279. }
  280. static int meson_ee_pwrc_of_xlate(struct power_domain *power_domain,
  281. struct ofnode_phandle_args *args)
  282. {
  283. struct meson_ee_pwrc_priv *priv = dev_get_priv(power_domain->dev);
  284. /* #power-domain-cells is 1 */
  285. if (args->args_count < 1) {
  286. debug("Invalid args_count: %d\n", args->args_count);
  287. return -EINVAL;
  288. }
  289. power_domain->id = args->args[0];
  290. if (power_domain->id >= priv->data->count) {
  291. debug("Invalid domain ID: %lu\n", power_domain->id);
  292. return -EINVAL;
  293. }
  294. return 0;
  295. }
  296. struct power_domain_ops meson_ee_pwrc_ops = {
  297. .rfree = meson_ee_pwrc_free,
  298. .off = meson_ee_pwrc_off,
  299. .on = meson_ee_pwrc_on,
  300. .request = meson_ee_pwrc_request,
  301. .of_xlate = meson_ee_pwrc_of_xlate,
  302. };
  303. static struct meson_ee_pwrc_domain_data meson_ee_g12a_pwrc_data = {
  304. .count = ARRAY_SIZE(g12a_pwrc_domains),
  305. .domains = g12a_pwrc_domains,
  306. };
  307. static struct meson_ee_pwrc_domain_data meson_ee_sm1_pwrc_data = {
  308. .count = ARRAY_SIZE(sm1_pwrc_domains),
  309. .domains = sm1_pwrc_domains,
  310. };
  311. static const struct udevice_id meson_ee_pwrc_ids[] = {
  312. {
  313. .compatible = "amlogic,meson-g12a-pwrc",
  314. .data = (unsigned long)&meson_ee_g12a_pwrc_data,
  315. },
  316. {
  317. .compatible = "amlogic,meson-sm1-pwrc",
  318. .data = (unsigned long)&meson_ee_sm1_pwrc_data,
  319. },
  320. { }
  321. };
  322. static int meson_ee_pwrc_probe(struct udevice *dev)
  323. {
  324. struct meson_ee_pwrc_priv *priv = dev_get_priv(dev);
  325. u32 ao_phandle;
  326. ofnode ao_node;
  327. int ret;
  328. priv->data = (void *)dev_get_driver_data(dev);
  329. if (!priv->data)
  330. return -EINVAL;
  331. priv->regmap_hhi = syscon_node_to_regmap(dev_get_parent(dev)->node);
  332. if (IS_ERR(priv->regmap_hhi))
  333. return PTR_ERR(priv->regmap_hhi);
  334. ret = ofnode_read_u32(dev->node, "amlogic,ao-sysctrl",
  335. &ao_phandle);
  336. if (ret)
  337. return ret;
  338. ao_node = ofnode_get_by_phandle(ao_phandle);
  339. if (!ofnode_valid(ao_node))
  340. return -EINVAL;
  341. priv->regmap_ao = syscon_node_to_regmap(ao_node);
  342. if (IS_ERR(priv->regmap_ao))
  343. return PTR_ERR(priv->regmap_ao);
  344. ret = reset_get_bulk(dev, &priv->resets);
  345. if (ret)
  346. return ret;
  347. ret = clk_get_bulk(dev, &priv->clks);
  348. if (ret)
  349. return ret;
  350. return 0;
  351. }
  352. U_BOOT_DRIVER(meson_ee_pwrc) = {
  353. .name = "meson_ee_pwrc",
  354. .id = UCLASS_POWER_DOMAIN,
  355. .of_match = meson_ee_pwrc_ids,
  356. .probe = meson_ee_pwrc_probe,
  357. .ops = &meson_ee_pwrc_ops,
  358. .priv_auto_alloc_size = sizeof(struct meson_ee_pwrc_priv),
  359. };