pinctrl-servalt.c 6.0 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /*
  3. * Microsemi SoCs pinctrl driver
  4. *
  5. * Author: <horatiu.vultur@microchip.com>
  6. * Copyright (c) 2019 Microsemi Corporation
  7. */
  8. #include <common.h>
  9. #include <config.h>
  10. #include <dm.h>
  11. #include <dm/device-internal.h>
  12. #include <dm/lists.h>
  13. #include <dm/pinctrl.h>
  14. #include <dm/root.h>
  15. #include <errno.h>
  16. #include <fdtdec.h>
  17. #include <linux/io.h>
  18. #include <asm/gpio.h>
  19. #include <asm/system.h>
  20. #include "mscc-common.h"
  21. enum {
  22. FUNC_NONE,
  23. FUNC_GPIO,
  24. FUNC_IRQ0_IN,
  25. FUNC_IRQ0_OUT,
  26. FUNC_IRQ1_IN,
  27. FUNC_IRQ1_OUT,
  28. FUNC_MIIM1,
  29. FUNC_MIIM2,
  30. FUNC_PCI_WAKE,
  31. FUNC_PTP0,
  32. FUNC_PTP1,
  33. FUNC_PTP2,
  34. FUNC_PTP3,
  35. FUNC_PWM,
  36. FUNC_RCVRD_CLK0,
  37. FUNC_RCVRD_CLK1,
  38. FUNC_RCVRD_CLK2,
  39. FUNC_RCVRD_CLK3,
  40. FUNC_REF_CLK0,
  41. FUNC_REF_CLK1,
  42. FUNC_REF_CLK2,
  43. FUNC_REF_CLK3,
  44. FUNC_SFP0,
  45. FUNC_SFP1,
  46. FUNC_SFP2,
  47. FUNC_SFP3,
  48. FUNC_SFP4,
  49. FUNC_SFP5,
  50. FUNC_SFP6,
  51. FUNC_SFP7,
  52. FUNC_SFP8,
  53. FUNC_SFP9,
  54. FUNC_SFP10,
  55. FUNC_SFP11,
  56. FUNC_SFP12,
  57. FUNC_SFP13,
  58. FUNC_SFP14,
  59. FUNC_SFP15,
  60. FUNC_SIO,
  61. FUNC_SPI,
  62. FUNC_TACHO,
  63. FUNC_TWI,
  64. FUNC_TWI2,
  65. FUNC_TWI_SCL_M,
  66. FUNC_UART,
  67. FUNC_UART2,
  68. FUNC_MAX
  69. };
  70. static char * const servalt_function_names[] = {
  71. [FUNC_NONE] = "none",
  72. [FUNC_GPIO] = "gpio",
  73. [FUNC_IRQ0_IN] = "irq0_in",
  74. [FUNC_IRQ0_OUT] = "irq0_out",
  75. [FUNC_IRQ1_IN] = "irq1_in",
  76. [FUNC_IRQ1_OUT] = "irq1_out",
  77. [FUNC_MIIM1] = "miim1",
  78. [FUNC_MIIM2] = "miim2",
  79. [FUNC_PCI_WAKE] = "pci_wake",
  80. [FUNC_PTP0] = "ptp0",
  81. [FUNC_PTP1] = "ptp1",
  82. [FUNC_PTP2] = "ptp2",
  83. [FUNC_PTP3] = "ptp3",
  84. [FUNC_PWM] = "pwm",
  85. [FUNC_RCVRD_CLK0] = "rcvrd_clk0",
  86. [FUNC_RCVRD_CLK1] = "rcvrd_clk1",
  87. [FUNC_RCVRD_CLK2] = "rcvrd_clk2",
  88. [FUNC_RCVRD_CLK3] = "rcvrd_clk3",
  89. [FUNC_REF_CLK0] = "ref_clk0",
  90. [FUNC_REF_CLK1] = "ref_clk1",
  91. [FUNC_REF_CLK2] = "ref_clk2",
  92. [FUNC_REF_CLK3] = "ref_clk3",
  93. [FUNC_SFP0] = "sfp0",
  94. [FUNC_SFP1] = "sfp1",
  95. [FUNC_SFP2] = "sfp2",
  96. [FUNC_SFP3] = "sfp3",
  97. [FUNC_SFP4] = "sfp4",
  98. [FUNC_SFP5] = "sfp5",
  99. [FUNC_SFP6] = "sfp6",
  100. [FUNC_SFP7] = "sfp7",
  101. [FUNC_SFP8] = "sfp8",
  102. [FUNC_SFP9] = "sfp9",
  103. [FUNC_SFP10] = "sfp10",
  104. [FUNC_SFP11] = "sfp11",
  105. [FUNC_SFP12] = "sfp12",
  106. [FUNC_SFP13] = "sfp13",
  107. [FUNC_SFP14] = "sfp14",
  108. [FUNC_SFP15] = "sfp15",
  109. [FUNC_SIO] = "sio",
  110. [FUNC_SPI] = "spi",
  111. [FUNC_TACHO] = "tacho",
  112. [FUNC_TWI] = "twi",
  113. [FUNC_TWI2] = "twi2",
  114. [FUNC_TWI_SCL_M] = "twi_scl_m",
  115. [FUNC_UART] = "uart",
  116. [FUNC_UART2] = "uart2",
  117. };
  118. MSCC_P(0, SIO, NONE, NONE);
  119. MSCC_P(1, SIO, NONE, NONE);
  120. MSCC_P(2, SIO, NONE, NONE);
  121. MSCC_P(3, SIO, NONE, NONE);
  122. MSCC_P(4, IRQ0_IN, IRQ0_OUT, TWI_SCL_M);
  123. MSCC_P(5, IRQ1_IN, IRQ1_OUT, TWI_SCL_M);
  124. MSCC_P(6, UART, NONE, NONE);
  125. MSCC_P(7, UART, NONE, NONE);
  126. MSCC_P(8, SPI, SFP0, TWI_SCL_M);
  127. MSCC_P(9, PCI_WAKE, SFP1, SPI);
  128. MSCC_P(10, PTP0, SFP2, TWI_SCL_M);
  129. MSCC_P(11, PTP1, SFP3, TWI_SCL_M);
  130. MSCC_P(12, REF_CLK0, SFP4, TWI_SCL_M);
  131. MSCC_P(13, REF_CLK1, SFP5, TWI_SCL_M);
  132. MSCC_P(14, REF_CLK2, IRQ0_OUT, SPI);
  133. MSCC_P(15, REF_CLK3, IRQ1_OUT, SPI);
  134. MSCC_P(16, TACHO, SFP6, SPI);
  135. MSCC_P(17, PWM, NONE, TWI_SCL_M);
  136. MSCC_P(18, PTP2, SFP7, SPI);
  137. MSCC_P(19, PTP3, SFP8, SPI);
  138. MSCC_P(20, UART2, SFP9, SPI);
  139. MSCC_P(21, UART2, NONE, NONE);
  140. MSCC_P(22, MIIM1, SFP10, TWI2);
  141. MSCC_P(23, MIIM1, SFP11, TWI2);
  142. MSCC_P(24, TWI, NONE, NONE);
  143. MSCC_P(25, TWI, SFP12, TWI_SCL_M);
  144. MSCC_P(26, TWI_SCL_M, SFP13, SPI);
  145. MSCC_P(27, TWI_SCL_M, SFP14, SPI);
  146. MSCC_P(28, TWI_SCL_M, SFP15, SPI);
  147. MSCC_P(29, TWI_SCL_M, NONE, NONE);
  148. MSCC_P(30, TWI_SCL_M, NONE, NONE);
  149. MSCC_P(31, TWI_SCL_M, NONE, NONE);
  150. MSCC_P(32, TWI_SCL_M, NONE, NONE);
  151. MSCC_P(33, RCVRD_CLK0, NONE, NONE);
  152. MSCC_P(34, RCVRD_CLK1, NONE, NONE);
  153. MSCC_P(35, RCVRD_CLK2, NONE, NONE);
  154. MSCC_P(36, RCVRD_CLK3, NONE, NONE);
  155. #define SERVALT_PIN(n) { \
  156. .name = "GPIO_"#n, \
  157. .drv_data = &mscc_pin_##n \
  158. }
  159. static const struct mscc_pin_data servalt_pins[] = {
  160. SERVALT_PIN(0),
  161. SERVALT_PIN(1),
  162. SERVALT_PIN(2),
  163. SERVALT_PIN(3),
  164. SERVALT_PIN(4),
  165. SERVALT_PIN(5),
  166. SERVALT_PIN(6),
  167. SERVALT_PIN(7),
  168. SERVALT_PIN(8),
  169. SERVALT_PIN(9),
  170. SERVALT_PIN(10),
  171. SERVALT_PIN(11),
  172. SERVALT_PIN(12),
  173. SERVALT_PIN(13),
  174. SERVALT_PIN(14),
  175. SERVALT_PIN(15),
  176. SERVALT_PIN(16),
  177. SERVALT_PIN(17),
  178. SERVALT_PIN(18),
  179. SERVALT_PIN(19),
  180. SERVALT_PIN(20),
  181. SERVALT_PIN(21),
  182. SERVALT_PIN(22),
  183. SERVALT_PIN(23),
  184. SERVALT_PIN(24),
  185. SERVALT_PIN(25),
  186. SERVALT_PIN(26),
  187. SERVALT_PIN(27),
  188. SERVALT_PIN(28),
  189. SERVALT_PIN(29),
  190. SERVALT_PIN(30),
  191. SERVALT_PIN(31),
  192. SERVALT_PIN(32),
  193. SERVALT_PIN(33),
  194. SERVALT_PIN(34),
  195. SERVALT_PIN(35),
  196. SERVALT_PIN(36),
  197. };
  198. static const unsigned long servalt_gpios[] = {
  199. [MSCC_GPIO_OUT_SET] = 0x00,
  200. [MSCC_GPIO_OUT_CLR] = 0x08,
  201. [MSCC_GPIO_OUT] = 0x10,
  202. [MSCC_GPIO_IN] = 0x18,
  203. [MSCC_GPIO_OE] = 0x20,
  204. [MSCC_GPIO_INTR] = 0x28,
  205. [MSCC_GPIO_INTR_ENA] = 0x30,
  206. [MSCC_GPIO_INTR_IDENT] = 0x38,
  207. [MSCC_GPIO_ALT0] = 0x40,
  208. [MSCC_GPIO_ALT1] = 0x48,
  209. };
  210. static int servalt_gpio_probe(struct udevice *dev)
  211. {
  212. struct gpio_dev_priv *uc_priv;
  213. uc_priv = dev_get_uclass_priv(dev);
  214. uc_priv->bank_name = "servalt-gpio";
  215. uc_priv->gpio_count = ARRAY_SIZE(servalt_pins);
  216. return 0;
  217. }
  218. static struct driver servalt_gpio_driver = {
  219. .name = "servalt-gpio",
  220. .id = UCLASS_GPIO,
  221. .probe = servalt_gpio_probe,
  222. .ops = &mscc_gpio_ops,
  223. };
  224. static int servalt_pinctrl_probe(struct udevice *dev)
  225. {
  226. int ret;
  227. ret = mscc_pinctrl_probe(dev, FUNC_MAX, servalt_pins,
  228. ARRAY_SIZE(servalt_pins),
  229. servalt_function_names,
  230. servalt_gpios);
  231. if (ret)
  232. return ret;
  233. ret = device_bind(dev, &servalt_gpio_driver, "servalt-gpio", NULL,
  234. dev_of_offset(dev), NULL);
  235. if (ret)
  236. return ret;
  237. return 0;
  238. }
  239. static const struct udevice_id servalt_pinctrl_of_match[] = {
  240. { .compatible = "mscc,servalt-pinctrl" },
  241. {},
  242. };
  243. U_BOOT_DRIVER(servalt_pinctrl) = {
  244. .name = "servalt-pinctrl",
  245. .id = UCLASS_PINCTRL,
  246. .of_match = of_match_ptr(servalt_pinctrl_of_match),
  247. .probe = servalt_pinctrl_probe,
  248. .priv_auto_alloc_size = sizeof(struct mscc_pinctrl),
  249. .ops = &mscc_pinctrl_ops,
  250. };