phy-rockchip-typec.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0-only
  2. /*
  3. * ROCKCHIP Type-C PHY driver.
  4. *
  5. * Copyright (C) 2020 Amarula Solutions(India)
  6. * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
  7. * Author: Chris Zhong <zyw@rock-chips.com>
  8. * Kever Yang <kever.yang@rock-chips.com>
  9. */
  10. #include <common.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <dm/device_compat.h>
  14. #include <dm/lists.h>
  15. #include <generic-phy.h>
  16. #include <reset.h>
  17. #include <syscon.h>
  18. #include <asm/gpio.h>
  19. #include <asm/io.h>
  20. #include <linux/iopoll.h>
  21. #include <asm/arch-rockchip/clock.h>
  22. DECLARE_GLOBAL_DATA_PTR;
  23. #define usleep_range(a, b) udelay((b))
  24. #define CMN_SSM_BANDGAP (0x21 << 2)
  25. #define CMN_SSM_BIAS (0x22 << 2)
  26. #define CMN_PLLSM0_PLLEN (0x29 << 2)
  27. #define CMN_PLLSM0_PLLPRE (0x2a << 2)
  28. #define CMN_PLLSM0_PLLVREF (0x2b << 2)
  29. #define CMN_PLLSM0_PLLLOCK (0x2c << 2)
  30. #define CMN_PLLSM1_PLLEN (0x31 << 2)
  31. #define CMN_PLLSM1_PLLPRE (0x32 << 2)
  32. #define CMN_PLLSM1_PLLVREF (0x33 << 2)
  33. #define CMN_PLLSM1_PLLLOCK (0x34 << 2)
  34. #define CMN_PLLSM1_USER_DEF_CTRL (0x37 << 2)
  35. #define CMN_ICAL_OVRD (0xc1 << 2)
  36. #define CMN_PLL0_VCOCAL_OVRD (0x83 << 2)
  37. #define CMN_PLL0_VCOCAL_INIT (0x84 << 2)
  38. #define CMN_PLL0_VCOCAL_ITER (0x85 << 2)
  39. #define CMN_PLL0_LOCK_REFCNT_START (0x90 << 2)
  40. #define CMN_PLL0_LOCK_PLLCNT_START (0x92 << 2)
  41. #define CMN_PLL0_LOCK_PLLCNT_THR (0x93 << 2)
  42. #define CMN_PLL0_INTDIV (0x94 << 2)
  43. #define CMN_PLL0_FRACDIV (0x95 << 2)
  44. #define CMN_PLL0_HIGH_THR (0x96 << 2)
  45. #define CMN_PLL0_DSM_DIAG (0x97 << 2)
  46. #define CMN_PLL0_SS_CTRL1 (0x98 << 2)
  47. #define CMN_PLL0_SS_CTRL2 (0x99 << 2)
  48. #define CMN_PLL1_VCOCAL_START (0xa1 << 2)
  49. #define CMN_PLL1_VCOCAL_OVRD (0xa3 << 2)
  50. #define CMN_PLL1_VCOCAL_INIT (0xa4 << 2)
  51. #define CMN_PLL1_VCOCAL_ITER (0xa5 << 2)
  52. #define CMN_PLL1_LOCK_REFCNT_START (0xb0 << 2)
  53. #define CMN_PLL1_LOCK_PLLCNT_START (0xb2 << 2)
  54. #define CMN_PLL1_LOCK_PLLCNT_THR (0xb3 << 2)
  55. #define CMN_PLL1_INTDIV (0xb4 << 2)
  56. #define CMN_PLL1_FRACDIV (0xb5 << 2)
  57. #define CMN_PLL1_HIGH_THR (0xb6 << 2)
  58. #define CMN_PLL1_DSM_DIAG (0xb7 << 2)
  59. #define CMN_PLL1_SS_CTRL1 (0xb8 << 2)
  60. #define CMN_PLL1_SS_CTRL2 (0xb9 << 2)
  61. #define CMN_RXCAL_OVRD (0xd1 << 2)
  62. #define CMN_TXPUCAL_CTRL (0xe0 << 2)
  63. #define CMN_TXPUCAL_OVRD (0xe1 << 2)
  64. #define CMN_TXPDCAL_CTRL (0xf0 << 2)
  65. #define CMN_TXPDCAL_OVRD (0xf1 << 2)
  66. /* For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL */
  67. #define CMN_TXPXCAL_START BIT(15)
  68. #define CMN_TXPXCAL_DONE BIT(14)
  69. #define CMN_TXPXCAL_NO_RESPONSE BIT(13)
  70. #define CMN_TXPXCAL_CURRENT_RESPONSE BIT(12)
  71. #define CMN_TXPU_ADJ_CTRL (0x108 << 2)
  72. #define CMN_TXPD_ADJ_CTRL (0x10c << 2)
  73. /*
  74. * For CMN_TXPUCAL_CTRL, CMN_TXPDCAL_CTRL,
  75. * CMN_TXPU_ADJ_CTRL, CMN_TXPDCAL_CTRL
  76. *
  77. * NOTE: some of these registers are documented to be 2's complement
  78. * signed numbers, but then documented to be always positive. Weird.
  79. * In such a case, using CMN_CALIB_CODE_POS() avoids the unnecessary
  80. * sign extension.
  81. */
  82. #define CMN_CALIB_CODE_WIDTH 7
  83. #define CMN_CALIB_CODE_OFFSET 0
  84. #define CMN_CALIB_CODE_MASK GENMASK(CMN_CALIB_CODE_WIDTH, 0)
  85. #define CMN_CALIB_CODE(x) \
  86. sign_extend32((x) >> CMN_CALIB_CODE_OFFSET, CMN_CALIB_CODE_WIDTH)
  87. #define CMN_CALIB_CODE_POS_MASK GENMASK(CMN_CALIB_CODE_WIDTH - 1, 0)
  88. #define CMN_CALIB_CODE_POS(x) \
  89. (((x) >> CMN_CALIB_CODE_OFFSET) & CMN_CALIB_CODE_POS_MASK)
  90. #define CMN_DIAG_PLL0_FBH_OVRD (0x1c0 << 2)
  91. #define CMN_DIAG_PLL0_FBL_OVRD (0x1c1 << 2)
  92. #define CMN_DIAG_PLL0_OVRD (0x1c2 << 2)
  93. #define CMN_DIAG_PLL0_V2I_TUNE (0x1c5 << 2)
  94. #define CMN_DIAG_PLL0_CP_TUNE (0x1c6 << 2)
  95. #define CMN_DIAG_PLL0_LF_PROG (0x1c7 << 2)
  96. #define CMN_DIAG_PLL1_FBH_OVRD (0x1d0 << 2)
  97. #define CMN_DIAG_PLL1_FBL_OVRD (0x1d1 << 2)
  98. #define CMN_DIAG_PLL1_OVRD (0x1d2 << 2)
  99. #define CMN_DIAG_PLL1_V2I_TUNE (0x1d5 << 2)
  100. #define CMN_DIAG_PLL1_CP_TUNE (0x1d6 << 2)
  101. #define CMN_DIAG_PLL1_LF_PROG (0x1d7 << 2)
  102. #define CMN_DIAG_PLL1_PTATIS_TUNE1 (0x1d8 << 2)
  103. #define CMN_DIAG_PLL1_PTATIS_TUNE2 (0x1d9 << 2)
  104. #define CMN_DIAG_PLL1_INCLK_CTRL (0x1da << 2)
  105. #define CMN_DIAG_HSCLK_SEL (0x1e0 << 2)
  106. #define XCVR_PSM_RCTRL(n) ((0x4001 | ((n) << 9)) << 2)
  107. #define XCVR_PSM_CAL_TMR(n) ((0x4002 | ((n) << 9)) << 2)
  108. #define XCVR_PSM_A0IN_TMR(n) ((0x4003 | ((n) << 9)) << 2)
  109. #define TX_TXCC_CAL_SCLR_MULT(n) ((0x4047 | ((n) << 9)) << 2)
  110. #define TX_TXCC_CPOST_MULT_00(n) ((0x404c | ((n) << 9)) << 2)
  111. #define TX_TXCC_CPOST_MULT_01(n) ((0x404d | ((n) << 9)) << 2)
  112. #define TX_TXCC_CPOST_MULT_10(n) ((0x404e | ((n) << 9)) << 2)
  113. #define TX_TXCC_CPOST_MULT_11(n) ((0x404f | ((n) << 9)) << 2)
  114. #define TX_TXCC_MGNFS_MULT_000(n) ((0x4050 | ((n) << 9)) << 2)
  115. #define TX_TXCC_MGNFS_MULT_001(n) ((0x4051 | ((n) << 9)) << 2)
  116. #define TX_TXCC_MGNFS_MULT_010(n) ((0x4052 | ((n) << 9)) << 2)
  117. #define TX_TXCC_MGNFS_MULT_011(n) ((0x4053 | ((n) << 9)) << 2)
  118. #define TX_TXCC_MGNFS_MULT_100(n) ((0x4054 | ((n) << 9)) << 2)
  119. #define TX_TXCC_MGNFS_MULT_101(n) ((0x4055 | ((n) << 9)) << 2)
  120. #define TX_TXCC_MGNFS_MULT_110(n) ((0x4056 | ((n) << 9)) << 2)
  121. #define TX_TXCC_MGNFS_MULT_111(n) ((0x4057 | ((n) << 9)) << 2)
  122. #define TX_TXCC_MGNLS_MULT_000(n) ((0x4058 | ((n) << 9)) << 2)
  123. #define TX_TXCC_MGNLS_MULT_001(n) ((0x4059 | ((n) << 9)) << 2)
  124. #define TX_TXCC_MGNLS_MULT_010(n) ((0x405a | ((n) << 9)) << 2)
  125. #define TX_TXCC_MGNLS_MULT_011(n) ((0x405b | ((n) << 9)) << 2)
  126. #define TX_TXCC_MGNLS_MULT_100(n) ((0x405c | ((n) << 9)) << 2)
  127. #define TX_TXCC_MGNLS_MULT_101(n) ((0x405d | ((n) << 9)) << 2)
  128. #define TX_TXCC_MGNLS_MULT_110(n) ((0x405e | ((n) << 9)) << 2)
  129. #define TX_TXCC_MGNLS_MULT_111(n) ((0x405f | ((n) << 9)) << 2)
  130. #define XCVR_DIAG_PLLDRC_CTRL(n) ((0x40e0 | ((n) << 9)) << 2)
  131. #define XCVR_DIAG_BIDI_CTRL(n) ((0x40e8 | ((n) << 9)) << 2)
  132. #define XCVR_DIAG_LANE_FCM_EN_MGN(n) ((0x40f2 | ((n) << 9)) << 2)
  133. #define TX_PSC_A0(n) ((0x4100 | ((n) << 9)) << 2)
  134. #define TX_PSC_A1(n) ((0x4101 | ((n) << 9)) << 2)
  135. #define TX_PSC_A2(n) ((0x4102 | ((n) << 9)) << 2)
  136. #define TX_PSC_A3(n) ((0x4103 | ((n) << 9)) << 2)
  137. #define TX_RCVDET_CTRL(n) ((0x4120 | ((n) << 9)) << 2)
  138. #define TX_RCVDET_EN_TMR(n) ((0x4122 | ((n) << 9)) << 2)
  139. #define TX_RCVDET_ST_TMR(n) ((0x4123 | ((n) << 9)) << 2)
  140. #define TX_DIAG_TX_DRV(n) ((0x41e1 | ((n) << 9)) << 2)
  141. #define TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 << 2)
  142. /* Use this for "n" in macros like "_MULT_XXX" to target the aux channel */
  143. #define AUX_CH_LANE 8
  144. #define TX_ANA_CTRL_REG_1 (0x5020 << 2)
  145. #define TXDA_DP_AUX_EN BIT(15)
  146. #define AUXDA_SE_EN BIT(14)
  147. #define TXDA_CAL_LATCH_EN BIT(13)
  148. #define AUXDA_POLARITY BIT(12)
  149. #define TXDA_DRV_POWER_ISOLATION_EN BIT(11)
  150. #define TXDA_DRV_POWER_EN_PH_2_N BIT(10)
  151. #define TXDA_DRV_POWER_EN_PH_1_N BIT(9)
  152. #define TXDA_BGREF_EN BIT(8)
  153. #define TXDA_DRV_LDO_EN BIT(7)
  154. #define TXDA_DECAP_EN_DEL BIT(6)
  155. #define TXDA_DECAP_EN BIT(5)
  156. #define TXDA_UPHY_SUPPLY_EN_DEL BIT(4)
  157. #define TXDA_UPHY_SUPPLY_EN BIT(3)
  158. #define TXDA_LOW_LEAKAGE_EN BIT(2)
  159. #define TXDA_DRV_IDLE_LOWI_EN BIT(1)
  160. #define TXDA_DRV_CMN_MODE_EN BIT(0)
  161. #define TX_ANA_CTRL_REG_2 (0x5021 << 2)
  162. #define AUXDA_DEBOUNCING_CLK BIT(15)
  163. #define TXDA_LPBK_RECOVERED_CLK_EN BIT(14)
  164. #define TXDA_LPBK_ISI_GEN_EN BIT(13)
  165. #define TXDA_LPBK_SERIAL_EN BIT(12)
  166. #define TXDA_LPBK_LINE_EN BIT(11)
  167. #define TXDA_DRV_LDO_REDC_SINKIQ BIT(10)
  168. #define XCVR_DECAP_EN_DEL BIT(9)
  169. #define XCVR_DECAP_EN BIT(8)
  170. #define TXDA_MPHY_ENABLE_HS_NT BIT(7)
  171. #define TXDA_MPHY_SA_MODE BIT(6)
  172. #define TXDA_DRV_LDO_RBYR_FB_EN BIT(5)
  173. #define TXDA_DRV_RST_PULL_DOWN BIT(4)
  174. #define TXDA_DRV_LDO_BG_FB_EN BIT(3)
  175. #define TXDA_DRV_LDO_BG_REF_EN BIT(2)
  176. #define TXDA_DRV_PREDRV_EN_DEL BIT(1)
  177. #define TXDA_DRV_PREDRV_EN BIT(0)
  178. #define TXDA_COEFF_CALC_CTRL (0x5022 << 2)
  179. #define TX_HIGH_Z BIT(6)
  180. #define TX_VMARGIN_OFFSET 3
  181. #define TX_VMARGIN_MASK 0x7
  182. #define LOW_POWER_SWING_EN BIT(2)
  183. #define TX_FCM_DRV_MAIN_EN BIT(1)
  184. #define TX_FCM_FULL_MARGIN BIT(0)
  185. #define TX_DIG_CTRL_REG_2 (0x5024 << 2)
  186. #define TX_HIGH_Z_TM_EN BIT(15)
  187. #define TX_RESCAL_CODE_OFFSET 0
  188. #define TX_RESCAL_CODE_MASK 0x3f
  189. #define TXDA_CYA_AUXDA_CYA (0x5025 << 2)
  190. #define TX_ANA_CTRL_REG_3 (0x5026 << 2)
  191. #define TX_ANA_CTRL_REG_4 (0x5027 << 2)
  192. #define TX_ANA_CTRL_REG_5 (0x5029 << 2)
  193. #define RX_PSC_A0(n) ((0x8000 | ((n) << 9)) << 2)
  194. #define RX_PSC_A1(n) ((0x8001 | ((n) << 9)) << 2)
  195. #define RX_PSC_A2(n) ((0x8002 | ((n) << 9)) << 2)
  196. #define RX_PSC_A3(n) ((0x8003 | ((n) << 9)) << 2)
  197. #define RX_PSC_CAL(n) ((0x8006 | ((n) << 9)) << 2)
  198. #define RX_PSC_RDY(n) ((0x8007 | ((n) << 9)) << 2)
  199. #define RX_IQPI_ILL_CAL_OVRD (0x8023 << 2)
  200. #define RX_EPI_ILL_CAL_OVRD (0x8033 << 2)
  201. #define RX_SDCAL0_OVRD (0x8041 << 2)
  202. #define RX_SDCAL1_OVRD (0x8049 << 2)
  203. #define RX_SLC_INIT (0x806d << 2)
  204. #define RX_SLC_RUN (0x806e << 2)
  205. #define RX_CDRLF_CNFG2 (0x8081 << 2)
  206. #define RX_SIGDET_HL_FILT_TMR(n) ((0x8090 | ((n) << 9)) << 2)
  207. #define RX_SLC_IOP0_OVRD (0x8101 << 2)
  208. #define RX_SLC_IOP1_OVRD (0x8105 << 2)
  209. #define RX_SLC_QOP0_OVRD (0x8109 << 2)
  210. #define RX_SLC_QOP1_OVRD (0x810d << 2)
  211. #define RX_SLC_EOP0_OVRD (0x8111 << 2)
  212. #define RX_SLC_EOP1_OVRD (0x8115 << 2)
  213. #define RX_SLC_ION0_OVRD (0x8119 << 2)
  214. #define RX_SLC_ION1_OVRD (0x811d << 2)
  215. #define RX_SLC_QON0_OVRD (0x8121 << 2)
  216. #define RX_SLC_QON1_OVRD (0x8125 << 2)
  217. #define RX_SLC_EON0_OVRD (0x8129 << 2)
  218. #define RX_SLC_EON1_OVRD (0x812d << 2)
  219. #define RX_SLC_IEP0_OVRD (0x8131 << 2)
  220. #define RX_SLC_IEP1_OVRD (0x8135 << 2)
  221. #define RX_SLC_QEP0_OVRD (0x8139 << 2)
  222. #define RX_SLC_QEP1_OVRD (0x813d << 2)
  223. #define RX_SLC_EEP0_OVRD (0x8141 << 2)
  224. #define RX_SLC_EEP1_OVRD (0x8145 << 2)
  225. #define RX_SLC_IEN0_OVRD (0x8149 << 2)
  226. #define RX_SLC_IEN1_OVRD (0x814d << 2)
  227. #define RX_SLC_QEN0_OVRD (0x8151 << 2)
  228. #define RX_SLC_QEN1_OVRD (0x8155 << 2)
  229. #define RX_SLC_EEN0_OVRD (0x8159 << 2)
  230. #define RX_SLC_EEN1_OVRD (0x815d << 2)
  231. #define RX_REE_CTRL_DATA_MASK(n) ((0x81bb | ((n) << 9)) << 2)
  232. #define RX_DIAG_SIGDET_TUNE(n) ((0x81dc | ((n) << 9)) << 2)
  233. #define RX_DIAG_SC2C_DELAY (0x81e1 << 2)
  234. #define PMA_LANE_CFG (0xc000 << 2)
  235. #define PIPE_CMN_CTRL1 (0xc001 << 2)
  236. #define PIPE_CMN_CTRL2 (0xc002 << 2)
  237. #define PIPE_COM_LOCK_CFG1 (0xc003 << 2)
  238. #define PIPE_COM_LOCK_CFG2 (0xc004 << 2)
  239. #define PIPE_RCV_DET_INH (0xc005 << 2)
  240. #define DP_MODE_CTL (0xc008 << 2)
  241. #define DP_CLK_CTL (0xc009 << 2)
  242. #define STS (0xc00F << 2)
  243. #define PHY_ISO_CMN_CTRL (0xc010 << 2)
  244. #define PHY_DP_TX_CTL (0xc408 << 2)
  245. #define PMA_CMN_CTRL1 (0xc800 << 2)
  246. #define PHY_PMA_ISO_CMN_CTRL (0xc810 << 2)
  247. #define PHY_ISOLATION_CTRL (0xc81f << 2)
  248. #define PHY_PMA_ISO_XCVR_CTRL(n) ((0xcc11 | ((n) << 6)) << 2)
  249. #define PHY_PMA_ISO_LINK_MODE(n) ((0xcc12 | ((n) << 6)) << 2)
  250. #define PHY_PMA_ISO_PWRST_CTRL(n) ((0xcc13 | ((n) << 6)) << 2)
  251. #define PHY_PMA_ISO_TX_DATA_LO(n) ((0xcc14 | ((n) << 6)) << 2)
  252. #define PHY_PMA_ISO_TX_DATA_HI(n) ((0xcc15 | ((n) << 6)) << 2)
  253. #define PHY_PMA_ISO_RX_DATA_LO(n) ((0xcc16 | ((n) << 6)) << 2)
  254. #define PHY_PMA_ISO_RX_DATA_HI(n) ((0xcc17 | ((n) << 6)) << 2)
  255. #define TX_BIST_CTRL(n) ((0x4140 | ((n) << 9)) << 2)
  256. #define TX_BIST_UDDWR(n) ((0x4141 | ((n) << 9)) << 2)
  257. /*
  258. * Selects which PLL clock will be driven on the analog high speed
  259. * clock 0: PLL 0 div 1
  260. * clock 1: PLL 1 div 2
  261. */
  262. #define CLK_PLL_CONFIG 0X30
  263. #define CLK_PLL_MASK 0x33
  264. #define CMN_READY BIT(0)
  265. #define DP_PLL_CLOCK_ENABLE BIT(2)
  266. #define DP_PLL_ENABLE BIT(0)
  267. #define DP_PLL_DATA_RATE_RBR ((2 << 12) | (4 << 8))
  268. #define DP_PLL_DATA_RATE_HBR ((2 << 12) | (4 << 8))
  269. #define DP_PLL_DATA_RATE_HBR2 ((1 << 12) | (2 << 8))
  270. #define DP_MODE_A0 BIT(4)
  271. #define DP_MODE_A2 BIT(6)
  272. #define DP_MODE_ENTER_A0 0xc101
  273. #define DP_MODE_ENTER_A2 0xc104
  274. #define PHY_MODE_SET_TIMEOUT 100000
  275. #define PIN_ASSIGN_C_E 0x51d9
  276. #define PIN_ASSIGN_D_F 0x5100
  277. #define MODE_DISCONNECT 0
  278. #define MODE_UFP_USB BIT(0)
  279. #define MODE_DFP_USB BIT(1)
  280. #define MODE_DFP_DP BIT(2)
  281. struct usb3phy_reg {
  282. u32 offset;
  283. u32 enable_bit;
  284. u32 write_enable;
  285. };
  286. /**
  287. * struct rockchip_usb3phy_port_cfg: usb3-phy port configuration.
  288. * @reg: the base address for usb3-phy config.
  289. * @typec_conn_dir: the register of type-c connector direction.
  290. * @usb3tousb2_en: the register of type-c force usb2 to usb2 enable.
  291. * @external_psm: the register of type-c phy external psm clock.
  292. * @pipe_status: the register of type-c phy pipe status.
  293. * @usb3_host_disable: the register of type-c usb3 host disable.
  294. * @usb3_host_port: the register of type-c usb3 host port.
  295. * @uphy_dp_sel: the register of type-c phy DP select control.
  296. */
  297. struct rockchip_usb3phy_port_cfg {
  298. unsigned int reg;
  299. struct usb3phy_reg typec_conn_dir;
  300. struct usb3phy_reg usb3tousb2_en;
  301. struct usb3phy_reg external_psm;
  302. struct usb3phy_reg pipe_status;
  303. struct usb3phy_reg usb3_host_disable;
  304. struct usb3phy_reg usb3_host_port;
  305. struct usb3phy_reg uphy_dp_sel;
  306. };
  307. struct rockchip_tcphy {
  308. void __iomem *reg_base;
  309. void __iomem *grf_base;
  310. struct clk clk_core;
  311. struct clk clk_ref;
  312. struct reset_ctl uphy_rst;
  313. struct reset_ctl pipe_rst;
  314. struct reset_ctl tcphy_rst;
  315. const struct rockchip_usb3phy_port_cfg *port_cfgs;
  316. u8 mode;
  317. };
  318. struct phy_reg {
  319. u16 value;
  320. u32 addr;
  321. };
  322. static struct phy_reg usb3_pll_cfg[] = {
  323. { 0xf0, CMN_PLL0_VCOCAL_INIT },
  324. { 0x18, CMN_PLL0_VCOCAL_ITER },
  325. { 0xd0, CMN_PLL0_INTDIV },
  326. { 0x4a4a, CMN_PLL0_FRACDIV },
  327. { 0x34, CMN_PLL0_HIGH_THR },
  328. { 0x1ee, CMN_PLL0_SS_CTRL1 },
  329. { 0x7f03, CMN_PLL0_SS_CTRL2 },
  330. { 0x20, CMN_PLL0_DSM_DIAG },
  331. { 0, CMN_DIAG_PLL0_OVRD },
  332. { 0, CMN_DIAG_PLL0_FBH_OVRD },
  333. { 0, CMN_DIAG_PLL0_FBL_OVRD },
  334. { 0x7, CMN_DIAG_PLL0_V2I_TUNE },
  335. { 0x45, CMN_DIAG_PLL0_CP_TUNE },
  336. { 0x8, CMN_DIAG_PLL0_LF_PROG },
  337. };
  338. static inline int property_enable(struct rockchip_tcphy *priv,
  339. const struct usb3phy_reg *reg, bool en)
  340. {
  341. u32 mask = 1 << reg->write_enable;
  342. u32 val = en << reg->enable_bit;
  343. return writel(val | mask, priv->grf_base + reg->offset);
  344. }
  345. static int rockchip_tcphy_get_mode(struct rockchip_tcphy *priv)
  346. {
  347. /* TODO: Add proper logic to find DP or USB3 mode */
  348. return MODE_DFP_USB | MODE_UFP_USB;
  349. }
  350. static void rockchip_tcphy_cfg_24m(struct rockchip_tcphy *priv)
  351. {
  352. u32 i, rdata;
  353. /*
  354. * cmn_ref_clk_sel = 3, select the 24Mhz for clk parent
  355. * cmn_psm_clk_dig_div = 2, set the clk division to 2
  356. */
  357. writel(0x830, priv->reg_base + PMA_CMN_CTRL1);
  358. for (i = 0; i < 4; i++) {
  359. /*
  360. * The following PHY configuration assumes a 24 MHz reference
  361. * clock.
  362. */
  363. writel(0x90, priv->reg_base + XCVR_DIAG_LANE_FCM_EN_MGN(i));
  364. writel(0x960, priv->reg_base + TX_RCVDET_EN_TMR(i));
  365. writel(0x30, priv->reg_base + TX_RCVDET_ST_TMR(i));
  366. }
  367. rdata = readl(priv->reg_base + CMN_DIAG_HSCLK_SEL);
  368. rdata &= ~CLK_PLL_MASK;
  369. rdata |= CLK_PLL_CONFIG;
  370. writel(rdata, priv->reg_base + CMN_DIAG_HSCLK_SEL);
  371. }
  372. static void rockchip_tcphy_cfg_usb3_pll(struct rockchip_tcphy *priv)
  373. {
  374. u32 i;
  375. /* load the configuration of PLL0 */
  376. for (i = 0; i < ARRAY_SIZE(usb3_pll_cfg); i++)
  377. writel(usb3_pll_cfg[i].value,
  378. priv->reg_base + usb3_pll_cfg[i].addr);
  379. }
  380. static void rockchip_tcphy_tx_usb3_cfg_lane(struct rockchip_tcphy *priv,
  381. u32 lane)
  382. {
  383. writel(0x7799, priv->reg_base + TX_PSC_A0(lane));
  384. writel(0x7798, priv->reg_base + TX_PSC_A1(lane));
  385. writel(0x5098, priv->reg_base + TX_PSC_A2(lane));
  386. writel(0x5098, priv->reg_base + TX_PSC_A3(lane));
  387. writel(0, priv->reg_base + TX_TXCC_MGNFS_MULT_000(lane));
  388. writel(0xbf, priv->reg_base + XCVR_DIAG_BIDI_CTRL(lane));
  389. }
  390. static void rockchip_tcphy_rx_usb3_cfg_lane(struct rockchip_tcphy *priv,
  391. u32 lane)
  392. {
  393. writel(0xa6fd, priv->reg_base + RX_PSC_A0(lane));
  394. writel(0xa6fd, priv->reg_base + RX_PSC_A1(lane));
  395. writel(0xa410, priv->reg_base + RX_PSC_A2(lane));
  396. writel(0x2410, priv->reg_base + RX_PSC_A3(lane));
  397. writel(0x23ff, priv->reg_base + RX_PSC_CAL(lane));
  398. writel(0x13, priv->reg_base + RX_SIGDET_HL_FILT_TMR(lane));
  399. writel(0x03e7, priv->reg_base + RX_REE_CTRL_DATA_MASK(lane));
  400. writel(0x1004, priv->reg_base + RX_DIAG_SIGDET_TUNE(lane));
  401. writel(0x2010, priv->reg_base + RX_PSC_RDY(lane));
  402. writel(0xfb, priv->reg_base + XCVR_DIAG_BIDI_CTRL(lane));
  403. }
  404. static int rockchip_tcphy_init(struct phy *phy, struct rockchip_tcphy *priv)
  405. {
  406. const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
  407. u32 val;
  408. int ret;
  409. ret = clk_enable(&priv->clk_core);
  410. if (ret) {
  411. dev_err(phy->dev, "failed to enable core clk (ret=%d)\n", ret);
  412. return ret;
  413. }
  414. ret = clk_enable(&priv->clk_ref);
  415. if (ret) {
  416. dev_err(phy->dev, "failed to enable ref clk (ret=%d)\n", ret);
  417. goto err_clk_core;
  418. }
  419. ret = reset_deassert(&priv->tcphy_rst);
  420. if (ret) {
  421. dev_err(phy->dev, "failed to deassert uphy-tcphy reset (ret=%d)\n",
  422. ret);
  423. goto err_clk_ref;
  424. }
  425. property_enable(priv, &cfg->typec_conn_dir, 0);
  426. rockchip_tcphy_cfg_24m(priv);
  427. rockchip_tcphy_cfg_usb3_pll(priv);
  428. rockchip_tcphy_tx_usb3_cfg_lane(priv, 0);
  429. rockchip_tcphy_rx_usb3_cfg_lane(priv, 1);
  430. ret = reset_deassert(&priv->uphy_rst);
  431. if (ret) {
  432. dev_err(phy->dev, "failed to deassert uphy rst (ret=%d)\n",
  433. ret);
  434. goto err_tcphy_rst;
  435. }
  436. ret = readl_poll_sleep_timeout(priv->reg_base + PMA_CMN_CTRL1,
  437. val, val & CMN_READY, 10,
  438. PHY_MODE_SET_TIMEOUT);
  439. if (ret < 0) {
  440. dev_err(phy->dev, "PMA Timeout!\n");
  441. ret = -ETIMEDOUT;
  442. goto err_uphy_rst;
  443. }
  444. ret = reset_deassert(&priv->pipe_rst);
  445. if (ret) {
  446. dev_err(phy->dev, "failed to deassert pipe rst (ret=%d)\n",
  447. ret);
  448. goto err_uphy_rst;
  449. }
  450. return 0;
  451. err_uphy_rst:
  452. reset_assert(&priv->uphy_rst);
  453. err_tcphy_rst:
  454. reset_assert(&priv->tcphy_rst);
  455. err_clk_ref:
  456. clk_disable(&priv->clk_ref);
  457. err_clk_core:
  458. clk_disable(&priv->clk_core);
  459. return ret;
  460. }
  461. static void rockchip_tcphy_exit(struct rockchip_tcphy *priv)
  462. {
  463. reset_assert(&priv->tcphy_rst);
  464. reset_assert(&priv->uphy_rst);
  465. reset_assert(&priv->pipe_rst);
  466. clk_disable(&priv->clk_core);
  467. clk_disable(&priv->clk_ref);
  468. }
  469. static int tcphy_cfg_usb3_to_usb2_only(struct rockchip_tcphy *priv,
  470. bool value)
  471. {
  472. const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
  473. property_enable(priv, &cfg->usb3tousb2_en, value);
  474. property_enable(priv, &cfg->usb3_host_disable, value);
  475. property_enable(priv, &cfg->usb3_host_port, !value);
  476. return 0;
  477. }
  478. static int rockchip_usb3_phy_power_on(struct phy *phy)
  479. {
  480. struct udevice *parent = dev_get_parent(phy->dev);
  481. struct rockchip_tcphy *priv = dev_get_priv(parent);
  482. const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
  483. const struct usb3phy_reg *reg = &cfg->pipe_status;
  484. int timeout, new_mode;
  485. u32 val;
  486. int ret;
  487. new_mode = rockchip_tcphy_get_mode(priv);
  488. if (new_mode < 0) {
  489. dev_err(phy->dev, "invalid mode %d\n", new_mode);
  490. return new_mode;
  491. }
  492. if (priv->mode == new_mode)
  493. return 0;
  494. if (priv->mode == MODE_DISCONNECT) {
  495. ret = rockchip_tcphy_init(phy, priv);
  496. if (ret) {
  497. dev_err(phy->dev, "failed to init tcphy (ret=%d)\n", ret);
  498. return ret;
  499. }
  500. }
  501. /* wait TCPHY for pipe ready */
  502. for (timeout = 0; timeout < 100; timeout++) {
  503. val = readl(priv->grf_base + reg->offset);
  504. if (!(val & BIT(reg->enable_bit))) {
  505. priv->mode |= new_mode & (MODE_DFP_USB | MODE_UFP_USB);
  506. /* enable usb3 host */
  507. tcphy_cfg_usb3_to_usb2_only(priv, false);
  508. return 0;
  509. }
  510. usleep_range(10, 20);
  511. }
  512. if (priv->mode == MODE_DISCONNECT)
  513. rockchip_tcphy_exit(priv);
  514. return -ETIMEDOUT;
  515. }
  516. static int rockchip_usb3_phy_power_off(struct phy *phy)
  517. {
  518. struct udevice *parent = dev_get_parent(phy->dev);
  519. struct rockchip_tcphy *priv = dev_get_priv(parent);
  520. tcphy_cfg_usb3_to_usb2_only(priv, false);
  521. if (priv->mode == MODE_DISCONNECT)
  522. goto exit;
  523. priv->mode &= ~(MODE_UFP_USB | MODE_DFP_USB);
  524. if (priv->mode == MODE_DISCONNECT)
  525. rockchip_tcphy_exit(priv);
  526. exit:
  527. return 0;
  528. }
  529. static struct phy_ops rockchip_tcphy_usb3_ops = {
  530. .power_on = rockchip_usb3_phy_power_on,
  531. .power_off = rockchip_usb3_phy_power_off,
  532. };
  533. static void rockchip_tcphy_pre_init(struct udevice *dev)
  534. {
  535. struct rockchip_tcphy *priv = dev_get_priv(dev);
  536. const struct rockchip_usb3phy_port_cfg *cfg = priv->port_cfgs;
  537. reset_assert(&priv->tcphy_rst);
  538. reset_assert(&priv->uphy_rst);
  539. reset_assert(&priv->pipe_rst);
  540. /* select external psm clock */
  541. property_enable(priv, &cfg->external_psm, 1);
  542. property_enable(priv, &cfg->usb3tousb2_en, 0);
  543. priv->mode = MODE_DISCONNECT;
  544. }
  545. static int rockchip_tcphy_parse_dt(struct udevice *dev)
  546. {
  547. struct rockchip_tcphy *priv = dev_get_priv(dev);
  548. int ret;
  549. priv->grf_base = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
  550. if (IS_ERR(priv->grf_base))
  551. return PTR_ERR(priv->grf_base);
  552. ret = clk_get_by_name(dev, "tcpdcore", &priv->clk_core);
  553. if (ret) {
  554. dev_err(dev, "failed to get tcpdcore clk (ret=%d)\n", ret);
  555. return ret;
  556. }
  557. ret = clk_get_by_name(dev, "tcpdphy-ref", &priv->clk_ref);
  558. if (ret) {
  559. dev_err(dev, "failed to get tcpdphy-ref clk (ret=%d)\n", ret);
  560. return ret;
  561. }
  562. ret = reset_get_by_name(dev, "uphy", &priv->uphy_rst);
  563. if (ret) {
  564. dev_err(dev, "failed to get uphy reset (ret=%d)\n", ret);
  565. return ret;
  566. }
  567. ret = reset_get_by_name(dev, "uphy-pipe", &priv->pipe_rst);
  568. if (ret) {
  569. dev_err(dev, "failed to get uphy-pipe reset (ret=%d)\n", ret);
  570. return ret;
  571. }
  572. ret = reset_get_by_name(dev, "uphy-tcphy", &priv->tcphy_rst);
  573. if (ret) {
  574. dev_err(dev, "failed to get uphy-tcphy reset (ret=%d)\n", ret);
  575. return ret;
  576. }
  577. return 0;
  578. }
  579. static int rockchip_tcphy_probe(struct udevice *dev)
  580. {
  581. struct rockchip_tcphy *priv = dev_get_priv(dev);
  582. const struct rockchip_usb3phy_port_cfg *phy_cfgs;
  583. unsigned int reg;
  584. int index, ret;
  585. priv->reg_base = (void __iomem *)dev_read_addr(dev);
  586. if (IS_ERR(priv->reg_base))
  587. return PTR_ERR(priv->reg_base);
  588. ret = dev_read_u32_index(dev, "reg", 1, &reg);
  589. if (ret) {
  590. dev_err(dev, "failed to read reg property (ret = %d)\n", ret);
  591. return ret;
  592. }
  593. phy_cfgs = (const struct rockchip_usb3phy_port_cfg *)
  594. dev_get_driver_data(dev);
  595. if (!phy_cfgs)
  596. return -EINVAL;
  597. /* find out a proper config which can be matched with dt. */
  598. index = 0;
  599. while (phy_cfgs[index].reg) {
  600. if (phy_cfgs[index].reg == reg) {
  601. priv->port_cfgs = &phy_cfgs[index];
  602. break;
  603. }
  604. ++index;
  605. }
  606. if (!priv->port_cfgs) {
  607. dev_err(dev, "failed find proper phy-cfg\n");
  608. return -EINVAL;
  609. }
  610. ret = rockchip_tcphy_parse_dt(dev);
  611. if (ret)
  612. return ret;
  613. rockchip_tcphy_pre_init(dev);
  614. return 0;
  615. }
  616. static int rockchip_tcphy_bind(struct udevice *dev)
  617. {
  618. struct udevice *tcphy_dev;
  619. ofnode node;
  620. const char *name;
  621. int ret = 0;
  622. dev_for_each_subnode(node, dev) {
  623. if (!ofnode_valid(node)) {
  624. dev_info(dev, "subnode %s not found\n", dev->name);
  625. return -ENXIO;
  626. }
  627. name = ofnode_get_name(node);
  628. dev_dbg(dev, "subnode %s\n", name);
  629. if (!strcasecmp(name, "dp-port")) {
  630. dev_dbg(dev, "Warning: dp-port not supported yet!\n");
  631. continue;
  632. } else if (!strcasecmp(name, "usb3-port")) {
  633. ret = device_bind_driver_to_node(dev,
  634. "rockchip_tcphy_usb3_port",
  635. name, node, &tcphy_dev);
  636. if (ret) {
  637. dev_err(dev,
  638. "'%s' cannot bind 'rockchip_tcphy_usb3_port'\n",
  639. name);
  640. return ret;
  641. }
  642. }
  643. }
  644. return ret;
  645. }
  646. static const struct rockchip_usb3phy_port_cfg rk3399_typec_phy_cfgs[] = {
  647. {
  648. .reg = 0xff7c0000,
  649. .typec_conn_dir = { 0xe580, 0, 16 },
  650. .usb3tousb2_en = { 0xe580, 3, 19 },
  651. .external_psm = { 0xe588, 14, 30 },
  652. .pipe_status = { 0xe5c0, 0, 0 },
  653. .usb3_host_disable = { 0x2434, 0, 16 },
  654. .usb3_host_port = { 0x2434, 12, 28 },
  655. .uphy_dp_sel = { 0x6268, 19, 19 },
  656. },
  657. {
  658. .reg = 0xff800000,
  659. .typec_conn_dir = { 0xe58c, 0, 16 },
  660. .usb3tousb2_en = { 0xe58c, 3, 19 },
  661. .external_psm = { 0xe594, 14, 30 },
  662. .pipe_status = { 0xe5c0, 16, 16 },
  663. .usb3_host_disable = { 0x2444, 0, 16 },
  664. .usb3_host_port = { 0x2444, 12, 28 },
  665. .uphy_dp_sel = { 0x6268, 3, 19 },
  666. },
  667. { /* sentinel */ }
  668. };
  669. static const struct udevice_id rockchip_typec_phy_ids[] = {
  670. {
  671. .compatible = "rockchip,rk3399-typec-phy",
  672. .data = (ulong)&rk3399_typec_phy_cfgs,
  673. },
  674. { /* sentinel */ }
  675. };
  676. U_BOOT_DRIVER(rockchip_tcphy_usb3_port) = {
  677. .name = "rockchip_tcphy_usb3_port",
  678. .id = UCLASS_PHY,
  679. .ops = &rockchip_tcphy_usb3_ops,
  680. };
  681. U_BOOT_DRIVER(rockchip_typec_phy) = {
  682. .name = "rockchip_typec_phy",
  683. .id = UCLASS_PHY,
  684. .of_match = rockchip_typec_phy_ids,
  685. .probe = rockchip_tcphy_probe,
  686. .bind = rockchip_tcphy_bind,
  687. .priv_auto_alloc_size = sizeof(struct rockchip_tcphy),
  688. };