phy-stm32-usbphyc.c 9.2 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410
  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
  4. */
  5. #include <common.h>
  6. #include <clk.h>
  7. #include <div64.h>
  8. #include <dm.h>
  9. #include <fdtdec.h>
  10. #include <generic-phy.h>
  11. #include <log.h>
  12. #include <reset.h>
  13. #include <syscon.h>
  14. #include <usb.h>
  15. #include <asm/io.h>
  16. #include <dm/device_compat.h>
  17. #include <linux/bitops.h>
  18. #include <linux/delay.h>
  19. #include <power/regulator.h>
  20. /* USBPHYC registers */
  21. #define STM32_USBPHYC_PLL 0x0
  22. #define STM32_USBPHYC_MISC 0x8
  23. /* STM32_USBPHYC_PLL bit fields */
  24. #define PLLNDIV GENMASK(6, 0)
  25. #define PLLNDIV_SHIFT 0
  26. #define PLLFRACIN GENMASK(25, 10)
  27. #define PLLFRACIN_SHIFT 10
  28. #define PLLEN BIT(26)
  29. #define PLLSTRB BIT(27)
  30. #define PLLSTRBYP BIT(28)
  31. #define PLLFRACCTL BIT(29)
  32. #define PLLDITHEN0 BIT(30)
  33. #define PLLDITHEN1 BIT(31)
  34. /* STM32_USBPHYC_MISC bit fields */
  35. #define SWITHOST BIT(0)
  36. #define MAX_PHYS 2
  37. /* max 100 us for PLL lock and 100 us for PHY init */
  38. #define PLL_INIT_TIME_US 200
  39. #define PLL_PWR_DOWN_TIME_US 5
  40. #define PLL_FVCO 2880 /* in MHz */
  41. #define PLL_INFF_MIN_RATE 19200000 /* in Hz */
  42. #define PLL_INFF_MAX_RATE 38400000 /* in Hz */
  43. struct pll_params {
  44. u8 ndiv;
  45. u16 frac;
  46. };
  47. struct stm32_usbphyc {
  48. fdt_addr_t base;
  49. struct clk clk;
  50. struct udevice *vdda1v1;
  51. struct udevice *vdda1v8;
  52. struct stm32_usbphyc_phy {
  53. struct udevice *vdd;
  54. bool init;
  55. bool powered;
  56. } phys[MAX_PHYS];
  57. };
  58. static void stm32_usbphyc_get_pll_params(u32 clk_rate,
  59. struct pll_params *pll_params)
  60. {
  61. unsigned long long fvco, ndiv, frac;
  62. /*
  63. * | FVCO = INFF*2*(NDIV + FRACT/2^16 ) when DITHER_DISABLE[1] = 1
  64. * | FVCO = 2880MHz
  65. * | NDIV = integer part of input bits to set the LDF
  66. * | FRACT = fractional part of input bits to set the LDF
  67. * => PLLNDIV = integer part of (FVCO / (INFF*2))
  68. * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
  69. * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
  70. */
  71. fvco = (unsigned long long)PLL_FVCO * 1000000; /* In Hz */
  72. ndiv = fvco;
  73. do_div(ndiv, (clk_rate * 2));
  74. pll_params->ndiv = (u8)ndiv;
  75. frac = fvco * (1 << 16);
  76. do_div(frac, (clk_rate * 2));
  77. frac = frac - (ndiv * (1 << 16));
  78. pll_params->frac = (u16)frac;
  79. }
  80. static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
  81. {
  82. struct pll_params pll_params;
  83. u32 clk_rate = clk_get_rate(&usbphyc->clk);
  84. u32 usbphyc_pll;
  85. if ((clk_rate < PLL_INFF_MIN_RATE) || (clk_rate > PLL_INFF_MAX_RATE)) {
  86. pr_debug("%s: input clk freq (%dHz) out of range\n",
  87. __func__, clk_rate);
  88. return -EINVAL;
  89. }
  90. stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
  91. usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP;
  92. usbphyc_pll |= ((pll_params.ndiv << PLLNDIV_SHIFT) & PLLNDIV);
  93. if (pll_params.frac) {
  94. usbphyc_pll |= PLLFRACCTL;
  95. usbphyc_pll |= ((pll_params.frac << PLLFRACIN_SHIFT)
  96. & PLLFRACIN);
  97. }
  98. writel(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
  99. pr_debug("%s: input clk freq=%dHz, ndiv=%d, frac=%d\n", __func__,
  100. clk_rate, pll_params.ndiv, pll_params.frac);
  101. return 0;
  102. }
  103. static bool stm32_usbphyc_is_init(struct stm32_usbphyc *usbphyc)
  104. {
  105. int i;
  106. for (i = 0; i < MAX_PHYS; i++) {
  107. if (usbphyc->phys[i].init)
  108. return true;
  109. }
  110. return false;
  111. }
  112. static bool stm32_usbphyc_is_powered(struct stm32_usbphyc *usbphyc)
  113. {
  114. int i;
  115. for (i = 0; i < MAX_PHYS; i++) {
  116. if (usbphyc->phys[i].powered)
  117. return true;
  118. }
  119. return false;
  120. }
  121. static int stm32_usbphyc_phy_init(struct phy *phy)
  122. {
  123. struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
  124. struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
  125. bool pllen = readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN ?
  126. true : false;
  127. int ret;
  128. pr_debug("%s phy ID = %lu\n", __func__, phy->id);
  129. /* Check if one phy port has already configured the pll */
  130. if (pllen && stm32_usbphyc_is_init(usbphyc))
  131. goto initialized;
  132. if (usbphyc->vdda1v1) {
  133. ret = regulator_set_enable(usbphyc->vdda1v1, true);
  134. if (ret)
  135. return ret;
  136. }
  137. if (usbphyc->vdda1v8) {
  138. ret = regulator_set_enable(usbphyc->vdda1v8, true);
  139. if (ret)
  140. return ret;
  141. }
  142. if (pllen) {
  143. clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
  144. udelay(PLL_PWR_DOWN_TIME_US);
  145. }
  146. ret = stm32_usbphyc_pll_init(usbphyc);
  147. if (ret)
  148. return ret;
  149. setbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
  150. /* We must wait PLL_INIT_TIME_US before using PHY */
  151. udelay(PLL_INIT_TIME_US);
  152. if (!(readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN))
  153. return -EIO;
  154. initialized:
  155. usbphyc_phy->init = true;
  156. return 0;
  157. }
  158. static int stm32_usbphyc_phy_exit(struct phy *phy)
  159. {
  160. struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
  161. struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
  162. int ret;
  163. pr_debug("%s phy ID = %lu\n", __func__, phy->id);
  164. usbphyc_phy->init = false;
  165. /* Check if other phy port requires pllen */
  166. if (stm32_usbphyc_is_init(usbphyc))
  167. return 0;
  168. clrbits_le32(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
  169. /*
  170. * We must wait PLL_PWR_DOWN_TIME_US before checking that PLLEN
  171. * bit is still clear
  172. */
  173. udelay(PLL_PWR_DOWN_TIME_US);
  174. if (readl(usbphyc->base + STM32_USBPHYC_PLL) & PLLEN)
  175. return -EIO;
  176. if (usbphyc->vdda1v1) {
  177. ret = regulator_set_enable(usbphyc->vdda1v1, false);
  178. if (ret)
  179. return ret;
  180. }
  181. if (usbphyc->vdda1v8) {
  182. ret = regulator_set_enable(usbphyc->vdda1v8, false);
  183. if (ret)
  184. return ret;
  185. }
  186. return 0;
  187. }
  188. static int stm32_usbphyc_phy_power_on(struct phy *phy)
  189. {
  190. struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
  191. struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
  192. int ret;
  193. pr_debug("%s phy ID = %lu\n", __func__, phy->id);
  194. if (usbphyc_phy->vdd) {
  195. ret = regulator_set_enable(usbphyc_phy->vdd, true);
  196. if (ret)
  197. return ret;
  198. }
  199. usbphyc_phy->powered = true;
  200. return 0;
  201. }
  202. static int stm32_usbphyc_phy_power_off(struct phy *phy)
  203. {
  204. struct stm32_usbphyc *usbphyc = dev_get_priv(phy->dev);
  205. struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + phy->id;
  206. int ret;
  207. pr_debug("%s phy ID = %lu\n", __func__, phy->id);
  208. usbphyc_phy->powered = false;
  209. if (stm32_usbphyc_is_powered(usbphyc))
  210. return 0;
  211. if (usbphyc_phy->vdd) {
  212. ret = regulator_set_enable_if_allowed(usbphyc_phy->vdd, false);
  213. if (ret)
  214. return ret;
  215. }
  216. return 0;
  217. }
  218. static int stm32_usbphyc_get_regulator(struct udevice *dev, ofnode node,
  219. char *supply_name,
  220. struct udevice **regulator)
  221. {
  222. struct ofnode_phandle_args regulator_phandle;
  223. int ret;
  224. ret = ofnode_parse_phandle_with_args(node, supply_name,
  225. NULL, 0, 0,
  226. &regulator_phandle);
  227. if (ret) {
  228. dev_err(dev, "Can't find %s property (%d)\n", supply_name, ret);
  229. return ret;
  230. }
  231. ret = uclass_get_device_by_ofnode(UCLASS_REGULATOR,
  232. regulator_phandle.node,
  233. regulator);
  234. if (ret) {
  235. dev_err(dev, "Can't get %s regulator (%d)\n", supply_name, ret);
  236. return ret;
  237. }
  238. return 0;
  239. }
  240. static int stm32_usbphyc_of_xlate(struct phy *phy,
  241. struct ofnode_phandle_args *args)
  242. {
  243. if (args->args_count < 1)
  244. return -ENODEV;
  245. if (args->args[0] >= MAX_PHYS)
  246. return -ENODEV;
  247. phy->id = args->args[0];
  248. if ((phy->id == 0 && args->args_count != 1) ||
  249. (phy->id == 1 && args->args_count != 2)) {
  250. dev_err(phy->dev, "invalid number of cells for phy port%ld\n",
  251. phy->id);
  252. return -EINVAL;
  253. }
  254. return 0;
  255. }
  256. static const struct phy_ops stm32_usbphyc_phy_ops = {
  257. .init = stm32_usbphyc_phy_init,
  258. .exit = stm32_usbphyc_phy_exit,
  259. .power_on = stm32_usbphyc_phy_power_on,
  260. .power_off = stm32_usbphyc_phy_power_off,
  261. .of_xlate = stm32_usbphyc_of_xlate,
  262. };
  263. static int stm32_usbphyc_probe(struct udevice *dev)
  264. {
  265. struct stm32_usbphyc *usbphyc = dev_get_priv(dev);
  266. struct reset_ctl reset;
  267. ofnode node;
  268. int i, ret;
  269. usbphyc->base = dev_read_addr(dev);
  270. if (usbphyc->base == FDT_ADDR_T_NONE)
  271. return -EINVAL;
  272. /* Enable clock */
  273. ret = clk_get_by_index(dev, 0, &usbphyc->clk);
  274. if (ret)
  275. return ret;
  276. ret = clk_enable(&usbphyc->clk);
  277. if (ret)
  278. return ret;
  279. /* Reset */
  280. ret = reset_get_by_index(dev, 0, &reset);
  281. if (!ret) {
  282. reset_assert(&reset);
  283. udelay(2);
  284. reset_deassert(&reset);
  285. }
  286. /* get usbphyc regulator */
  287. ret = device_get_supply_regulator(dev, "vdda1v1-supply",
  288. &usbphyc->vdda1v1);
  289. if (ret) {
  290. dev_err(dev, "Can't get vdda1v1-supply regulator\n");
  291. return ret;
  292. }
  293. ret = device_get_supply_regulator(dev, "vdda1v8-supply",
  294. &usbphyc->vdda1v8);
  295. if (ret) {
  296. dev_err(dev, "Can't get vdda1v8-supply regulator\n");
  297. return ret;
  298. }
  299. /*
  300. * parse all PHY subnodes in order to populate regulator associated
  301. * to each PHY port
  302. */
  303. node = dev_read_first_subnode(dev);
  304. for (i = 0; i < MAX_PHYS; i++) {
  305. struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys + i;
  306. usbphyc_phy->init = false;
  307. usbphyc_phy->powered = false;
  308. ret = stm32_usbphyc_get_regulator(dev, node, "phy-supply",
  309. &usbphyc_phy->vdd);
  310. if (ret)
  311. return ret;
  312. node = dev_read_next_subnode(node);
  313. }
  314. /* Check if second port has to be used for host controller */
  315. if (dev_read_bool(dev, "st,port2-switch-to-host"))
  316. setbits_le32(usbphyc->base + STM32_USBPHYC_MISC, SWITHOST);
  317. return 0;
  318. }
  319. static const struct udevice_id stm32_usbphyc_of_match[] = {
  320. { .compatible = "st,stm32mp1-usbphyc", },
  321. { },
  322. };
  323. U_BOOT_DRIVER(stm32_usb_phyc) = {
  324. .name = "stm32-usbphyc",
  325. .id = UCLASS_PHY,
  326. .of_match = stm32_usbphyc_of_match,
  327. .ops = &stm32_usbphyc_phy_ops,
  328. .probe = stm32_usbphyc_probe,
  329. .priv_auto_alloc_size = sizeof(struct stm32_usbphyc),
  330. };