meson-gxbb-usb2.c 6.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Meson8, Meson8b and GXBB USB2 PHY driver
  4. *
  5. * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  6. * Copyright (C) 2018 BayLibre, SAS
  7. *
  8. * Author: Beniamino Galvani <b.galvani@gmail.com>
  9. */
  10. #include <common.h>
  11. #include <clk.h>
  12. #include <dm.h>
  13. #include <generic-phy.h>
  14. #include <power/regulator.h>
  15. #include <regmap.h>
  16. #include <reset.h>
  17. #include <linux/bitops.h>
  18. #define REG_CONFIG 0x00
  19. #define REG_CONFIG_CLK_EN BIT(0)
  20. #define REG_CONFIG_CLK_SEL_MASK GENMASK(3, 1)
  21. #define REG_CONFIG_CLK_DIV_MASK GENMASK(10, 4)
  22. #define REG_CONFIG_CLK_32k_ALTSEL BIT(15)
  23. #define REG_CONFIG_TEST_TRIG BIT(31)
  24. #define REG_CTRL 0x04
  25. #define REG_CTRL_SOFT_PRST BIT(0)
  26. #define REG_CTRL_SOFT_HRESET BIT(1)
  27. #define REG_CTRL_SS_SCALEDOWN_MODE_MASK GENMASK(3, 2)
  28. #define REG_CTRL_CLK_DET_RST BIT(4)
  29. #define REG_CTRL_INTR_SEL BIT(5)
  30. #define REG_CTRL_CLK_DETECTED BIT(8)
  31. #define REG_CTRL_SOF_SENT_RCVD_TGL BIT(9)
  32. #define REG_CTRL_SOF_TOGGLE_OUT BIT(10)
  33. #define REG_CTRL_POWER_ON_RESET BIT(15)
  34. #define REG_CTRL_SLEEPM BIT(16)
  35. #define REG_CTRL_TX_BITSTUFF_ENN_H BIT(17)
  36. #define REG_CTRL_TX_BITSTUFF_ENN BIT(18)
  37. #define REG_CTRL_COMMON_ON BIT(19)
  38. #define REG_CTRL_REF_CLK_SEL_MASK GENMASK(21, 20)
  39. #define REG_CTRL_REF_CLK_SEL_SHIFT 20
  40. #define REG_CTRL_FSEL_MASK GENMASK(24, 22)
  41. #define REG_CTRL_FSEL_SHIFT 22
  42. #define REG_CTRL_PORT_RESET BIT(25)
  43. #define REG_CTRL_THREAD_ID_MASK GENMASK(31, 26)
  44. /* bits [31:26], [24:21] and [15:3] seem to be read-only */
  45. #define REG_ADP_BC 0x0c
  46. #define REG_ADP_BC_VBUS_VLD_EXT_SEL BIT(0)
  47. #define REG_ADP_BC_VBUS_VLD_EXT BIT(1)
  48. #define REG_ADP_BC_OTG_DISABLE BIT(2)
  49. #define REG_ADP_BC_ID_PULLUP BIT(3)
  50. #define REG_ADP_BC_DRV_VBUS BIT(4)
  51. #define REG_ADP_BC_ADP_PRB_EN BIT(5)
  52. #define REG_ADP_BC_ADP_DISCHARGE BIT(6)
  53. #define REG_ADP_BC_ADP_CHARGE BIT(7)
  54. #define REG_ADP_BC_SESS_END BIT(8)
  55. #define REG_ADP_BC_DEVICE_SESS_VLD BIT(9)
  56. #define REG_ADP_BC_B_VALID BIT(10)
  57. #define REG_ADP_BC_A_VALID BIT(11)
  58. #define REG_ADP_BC_ID_DIG BIT(12)
  59. #define REG_ADP_BC_VBUS_VALID BIT(13)
  60. #define REG_ADP_BC_ADP_PROBE BIT(14)
  61. #define REG_ADP_BC_ADP_SENSE BIT(15)
  62. #define REG_ADP_BC_ACA_ENABLE BIT(16)
  63. #define REG_ADP_BC_DCD_ENABLE BIT(17)
  64. #define REG_ADP_BC_VDAT_DET_EN_B BIT(18)
  65. #define REG_ADP_BC_VDAT_SRC_EN_B BIT(19)
  66. #define REG_ADP_BC_CHARGE_SEL BIT(20)
  67. #define REG_ADP_BC_CHARGE_DETECT BIT(21)
  68. #define REG_ADP_BC_ACA_PIN_RANGE_C BIT(22)
  69. #define REG_ADP_BC_ACA_PIN_RANGE_B BIT(23)
  70. #define REG_ADP_BC_ACA_PIN_RANGE_A BIT(24)
  71. #define REG_ADP_BC_ACA_PIN_GND BIT(25)
  72. #define REG_ADP_BC_ACA_PIN_FLOAT BIT(26)
  73. #define RESET_COMPLETE_TIME 500
  74. #define ACA_ENABLE_COMPLETE_TIME 50
  75. struct phy_meson_gxbb_usb2_priv {
  76. struct regmap *regmap;
  77. struct reset_ctl_bulk resets;
  78. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  79. struct udevice *phy_supply;
  80. #endif
  81. };
  82. static int phy_meson_gxbb_usb2_power_on(struct phy *phy)
  83. {
  84. struct udevice *dev = phy->dev;
  85. struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
  86. uint val;
  87. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  88. if (priv->phy_supply) {
  89. int ret = regulator_set_enable(priv->phy_supply, true);
  90. if (ret)
  91. return ret;
  92. }
  93. #endif
  94. regmap_update_bits(priv->regmap, REG_CONFIG,
  95. REG_CONFIG_CLK_32k_ALTSEL,
  96. REG_CONFIG_CLK_32k_ALTSEL);
  97. regmap_update_bits(priv->regmap, REG_CTRL,
  98. REG_CTRL_REF_CLK_SEL_MASK,
  99. 0x2 << REG_CTRL_REF_CLK_SEL_SHIFT);
  100. regmap_update_bits(priv->regmap, REG_CTRL,
  101. REG_CTRL_FSEL_MASK,
  102. 0x5 << REG_CTRL_FSEL_SHIFT);
  103. /* reset the PHY */
  104. regmap_update_bits(priv->regmap, REG_CTRL,
  105. REG_CTRL_POWER_ON_RESET,
  106. REG_CTRL_POWER_ON_RESET);
  107. udelay(RESET_COMPLETE_TIME);
  108. regmap_update_bits(priv->regmap, REG_CTRL,
  109. REG_CTRL_POWER_ON_RESET,
  110. 0);
  111. udelay(RESET_COMPLETE_TIME);
  112. regmap_update_bits(priv->regmap, REG_CTRL,
  113. REG_CTRL_SOF_TOGGLE_OUT,
  114. REG_CTRL_SOF_TOGGLE_OUT);
  115. /* Set host mode */
  116. regmap_update_bits(priv->regmap, REG_ADP_BC,
  117. REG_ADP_BC_ACA_ENABLE,
  118. REG_ADP_BC_ACA_ENABLE);
  119. udelay(ACA_ENABLE_COMPLETE_TIME);
  120. regmap_read(priv->regmap, REG_ADP_BC, &val);
  121. if (val & REG_ADP_BC_ACA_PIN_FLOAT) {
  122. pr_err("Error powering on GXBB USB PHY\n");
  123. return -EINVAL;
  124. }
  125. return 0;
  126. }
  127. static int phy_meson_gxbb_usb2_power_off(struct phy *phy)
  128. {
  129. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  130. struct udevice *dev = phy->dev;
  131. struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
  132. if (priv->phy_supply) {
  133. int ret = regulator_set_enable(priv->phy_supply, false);
  134. if (ret)
  135. return ret;
  136. }
  137. #endif
  138. return 0;
  139. }
  140. static struct phy_ops meson_gxbb_usb2_phy_ops = {
  141. .power_on = phy_meson_gxbb_usb2_power_on,
  142. .power_off = phy_meson_gxbb_usb2_power_off,
  143. };
  144. static int meson_gxbb_usb2_phy_probe(struct udevice *dev)
  145. {
  146. struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
  147. struct clk clk_usb_general, clk_usb;
  148. int ret;
  149. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  150. if (ret)
  151. return ret;
  152. ret = clk_get_by_name(dev, "usb_general", &clk_usb_general);
  153. if (ret)
  154. return ret;
  155. ret = clk_enable(&clk_usb_general);
  156. if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
  157. pr_err("Failed to enable PHY general clock\n");
  158. return ret;
  159. }
  160. ret = clk_get_by_name(dev, "usb", &clk_usb);
  161. if (ret)
  162. return ret;
  163. ret = clk_enable(&clk_usb);
  164. if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
  165. pr_err("Failed to enable PHY clock\n");
  166. return ret;
  167. }
  168. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  169. ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
  170. if (ret && ret != -ENOENT) {
  171. pr_err("Failed to get PHY regulator\n");
  172. return ret;
  173. }
  174. #endif
  175. ret = reset_get_bulk(dev, &priv->resets);
  176. if (!ret) {
  177. ret = reset_deassert_bulk(&priv->resets);
  178. if (ret) {
  179. pr_err("Failed to deassert reset\n");
  180. return ret;
  181. }
  182. }
  183. return 0;
  184. }
  185. static int meson_gxbb_usb2_phy_remove(struct udevice *dev)
  186. {
  187. struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev);
  188. return reset_release_bulk(&priv->resets);
  189. }
  190. static const struct udevice_id meson_gxbb_usb2_phy_ids[] = {
  191. { .compatible = "amlogic,meson8-usb2-phy" },
  192. { .compatible = "amlogic,meson8b-usb2-phy" },
  193. { .compatible = "amlogic,meson-gxbb-usb2-phy" },
  194. { }
  195. };
  196. U_BOOT_DRIVER(meson_gxbb_usb2_phy) = {
  197. .name = "meson_gxbb_usb2_phy",
  198. .id = UCLASS_PHY,
  199. .of_match = meson_gxbb_usb2_phy_ids,
  200. .probe = meson_gxbb_usb2_phy_probe,
  201. .remove = meson_gxbb_usb2_phy_remove,
  202. .ops = &meson_gxbb_usb2_phy_ops,
  203. .priv_auto_alloc_size = sizeof(struct phy_meson_gxbb_usb2_priv),
  204. };