meson-g12a-usb2.c 5.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Meson G12A USB2 PHY driver
  4. *
  5. * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  6. * Copyright (C) 2019 BayLibre, SAS
  7. * Author: Neil Armstrong <narmstron@baylibre.com>
  8. */
  9. #include <common.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <asm/io.h>
  13. #include <bitfield.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <generic-phy.h>
  17. #include <regmap.h>
  18. #include <linux/delay.h>
  19. #include <power/regulator.h>
  20. #include <reset.h>
  21. #include <clk.h>
  22. #include <linux/bitops.h>
  23. #include <linux/compat.h>
  24. #define PHY_CTRL_R0 0x0
  25. #define PHY_CTRL_R1 0x4
  26. #define PHY_CTRL_R2 0x8
  27. #define PHY_CTRL_R3 0xc
  28. #define PHY_CTRL_R4 0x10
  29. #define PHY_CTRL_R5 0x14
  30. #define PHY_CTRL_R6 0x18
  31. #define PHY_CTRL_R7 0x1c
  32. #define PHY_CTRL_R8 0x20
  33. #define PHY_CTRL_R9 0x24
  34. #define PHY_CTRL_R10 0x28
  35. #define PHY_CTRL_R11 0x2c
  36. #define PHY_CTRL_R12 0x30
  37. #define PHY_CTRL_R13 0x34
  38. #define PHY_CTRL_R14 0x38
  39. #define PHY_CTRL_R15 0x3c
  40. #define PHY_CTRL_R16 0x40
  41. #define PHY_CTRL_R17 0x44
  42. #define PHY_CTRL_R18 0x48
  43. #define PHY_CTRL_R19 0x4c
  44. #define PHY_CTRL_R20 0x50
  45. #define PHY_CTRL_R21 0x54
  46. #define PHY_CTRL_R22 0x58
  47. #define PHY_CTRL_R23 0x5c
  48. #define RESET_COMPLETE_TIME 1000
  49. #define PLL_RESET_COMPLETE_TIME 100
  50. struct phy_meson_g12a_usb2_priv {
  51. struct regmap *regmap;
  52. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  53. struct udevice *phy_supply;
  54. #endif
  55. #if CONFIG_IS_ENABLED(CLK)
  56. struct clk clk;
  57. #endif
  58. struct reset_ctl reset;
  59. };
  60. static int phy_meson_g12a_usb2_power_on(struct phy *phy)
  61. {
  62. struct udevice *dev = phy->dev;
  63. struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
  64. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  65. if (priv->phy_supply) {
  66. int ret = regulator_set_enable(priv->phy_supply, true);
  67. if (ret)
  68. return ret;
  69. }
  70. #endif
  71. return 0;
  72. }
  73. static int phy_meson_g12a_usb2_power_off(struct phy *phy)
  74. {
  75. struct udevice *dev = phy->dev;
  76. struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
  77. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  78. if (priv->phy_supply) {
  79. int ret = regulator_set_enable(priv->phy_supply, false);
  80. if (ret) {
  81. pr_err("Error disabling PHY supply\n");
  82. return ret;
  83. }
  84. }
  85. #endif
  86. return 0;
  87. }
  88. static int phy_meson_g12a_usb2_init(struct phy *phy)
  89. {
  90. struct udevice *dev = phy->dev;
  91. struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
  92. int ret;
  93. ret = reset_assert(&priv->reset);
  94. udelay(1);
  95. ret |= reset_deassert(&priv->reset);
  96. if (ret)
  97. return ret;
  98. udelay(RESET_COMPLETE_TIME);
  99. /* usb2_otg_aca_en == 0 */
  100. regmap_update_bits(priv->regmap, PHY_CTRL_R21, BIT(2), 0);
  101. /* PLL Setup : 24MHz * 20 / 1 = 480MHz */
  102. regmap_write(priv->regmap, PHY_CTRL_R16, 0x39400414);
  103. regmap_write(priv->regmap, PHY_CTRL_R17, 0x927e0000);
  104. regmap_write(priv->regmap, PHY_CTRL_R18, 0xac5f49e5);
  105. udelay(PLL_RESET_COMPLETE_TIME);
  106. /* UnReset PLL */
  107. regmap_write(priv->regmap, PHY_CTRL_R16, 0x19400414);
  108. /* PHY Tuning */
  109. regmap_write(priv->regmap, PHY_CTRL_R20, 0xfe18);
  110. regmap_write(priv->regmap, PHY_CTRL_R4, 0x8000fff);
  111. /* Tuning Disconnect Threshold */
  112. regmap_write(priv->regmap, PHY_CTRL_R3, 0x34);
  113. /* Analog Settings */
  114. regmap_write(priv->regmap, PHY_CTRL_R14, 0);
  115. regmap_write(priv->regmap, PHY_CTRL_R13, 0x78000);
  116. return 0;
  117. }
  118. static int phy_meson_g12a_usb2_exit(struct phy *phy)
  119. {
  120. struct udevice *dev = phy->dev;
  121. struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
  122. int ret;
  123. ret = reset_assert(&priv->reset);
  124. if (ret)
  125. return ret;
  126. return 0;
  127. }
  128. struct phy_ops meson_g12a_usb2_phy_ops = {
  129. .init = phy_meson_g12a_usb2_init,
  130. .exit = phy_meson_g12a_usb2_exit,
  131. .power_on = phy_meson_g12a_usb2_power_on,
  132. .power_off = phy_meson_g12a_usb2_power_off,
  133. };
  134. int meson_g12a_usb2_phy_probe(struct udevice *dev)
  135. {
  136. struct phy_meson_g12a_usb2_priv *priv = dev_get_priv(dev);
  137. int ret;
  138. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  139. if (ret)
  140. return ret;
  141. ret = reset_get_by_index(dev, 0, &priv->reset);
  142. if (ret == -ENOTSUPP)
  143. return 0;
  144. else if (ret)
  145. return ret;
  146. ret = reset_deassert(&priv->reset);
  147. if (ret) {
  148. reset_release_all(&priv->reset, 1);
  149. return ret;
  150. }
  151. #if CONFIG_IS_ENABLED(CLK)
  152. ret = clk_get_by_index(dev, 0, &priv->clk);
  153. if (ret < 0)
  154. return ret;
  155. ret = clk_enable(&priv->clk);
  156. if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
  157. pr_err("failed to enable PHY clock\n");
  158. clk_free(&priv->clk);
  159. return ret;
  160. }
  161. #endif
  162. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  163. ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
  164. if (ret && ret != -ENOENT) {
  165. pr_err("Failed to get PHY regulator\n");
  166. return ret;
  167. }
  168. #endif
  169. return 0;
  170. }
  171. static const struct udevice_id meson_g12a_usb2_phy_ids[] = {
  172. { .compatible = "amlogic,g12a-usb2-phy" },
  173. { }
  174. };
  175. U_BOOT_DRIVER(meson_g12a_usb2_phy) = {
  176. .name = "meson_g12a_usb2_phy",
  177. .id = UCLASS_PHY,
  178. .of_match = meson_g12a_usb2_phy_ids,
  179. .probe = meson_g12a_usb2_phy_probe,
  180. .ops = &meson_g12a_usb2_phy_ops,
  181. .priv_auto_alloc_size = sizeof(struct phy_meson_g12a_usb2_priv),
  182. };