pcie_layerscape_fixup.c 7.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2017-2020 NXP
  4. * Copyright 2014-2015 Freescale Semiconductor, Inc.
  5. * Layerscape PCIe driver
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <log.h>
  11. #include <pci.h>
  12. #include <asm/arch/fsl_serdes.h>
  13. #include <asm/io.h>
  14. #include <errno.h>
  15. #ifdef CONFIG_OF_BOARD_SETUP
  16. #include <linux/libfdt.h>
  17. #include <fdt_support.h>
  18. #ifdef CONFIG_ARM
  19. #include <asm/arch/clock.h>
  20. #endif
  21. #include "pcie_layerscape.h"
  22. #include "pcie_layerscape_fixup_common.h"
  23. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  24. /*
  25. * Return next available LUT index.
  26. */
  27. static int ls_pcie_next_lut_index(struct ls_pcie_rc *pcie_rc)
  28. {
  29. if (pcie_rc->next_lut_index < PCIE_LUT_ENTRY_COUNT)
  30. return pcie_rc->next_lut_index++;
  31. else
  32. return -ENOSPC; /* LUT is full */
  33. }
  34. static void lut_writel(struct ls_pcie_rc *pcie_rc, unsigned int value,
  35. unsigned int offset)
  36. {
  37. struct ls_pcie *pcie = pcie_rc->pcie;
  38. if (pcie->big_endian)
  39. out_be32(pcie->lut + offset, value);
  40. else
  41. out_le32(pcie->lut + offset, value);
  42. }
  43. /*
  44. * Program a single LUT entry
  45. */
  46. static void ls_pcie_lut_set_mapping(struct ls_pcie_rc *pcie_rc, int index,
  47. u32 devid, u32 streamid)
  48. {
  49. /* leave mask as all zeroes, want to match all bits */
  50. lut_writel(pcie_rc, devid << 16, PCIE_LUT_UDR(index));
  51. lut_writel(pcie_rc, streamid | PCIE_LUT_ENABLE, PCIE_LUT_LDR(index));
  52. }
  53. /*
  54. * An msi-map is a property to be added to the pci controller
  55. * node. It is a table, where each entry consists of 4 fields
  56. * e.g.:
  57. *
  58. * msi-map = <[devid] [phandle-to-msi-ctrl] [stream-id] [count]
  59. * [devid] [phandle-to-msi-ctrl] [stream-id] [count]>;
  60. */
  61. static void fdt_pcie_set_msi_map_entry_ls(void *blob,
  62. struct ls_pcie_rc *pcie_rc,
  63. u32 devid, u32 streamid)
  64. {
  65. u32 *prop;
  66. u32 phandle;
  67. int nodeoffset;
  68. uint svr;
  69. char *compat = NULL;
  70. struct ls_pcie *pcie = pcie_rc->pcie;
  71. /* find pci controller node */
  72. nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  73. pcie_rc->dbi_res.start);
  74. if (nodeoffset < 0) {
  75. #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  76. svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  77. if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  78. svr == SVR_LS2048A || svr == SVR_LS2044A ||
  79. svr == SVR_LS2081A || svr == SVR_LS2041A)
  80. compat = "fsl,ls2088a-pcie";
  81. else
  82. compat = CONFIG_FSL_PCIE_COMPAT;
  83. if (compat)
  84. nodeoffset = fdt_node_offset_by_compat_reg(blob,
  85. compat, pcie_rc->dbi_res.start);
  86. #endif
  87. if (nodeoffset < 0)
  88. return;
  89. }
  90. /* get phandle to MSI controller */
  91. prop = (u32 *)fdt_getprop(blob, nodeoffset, "msi-parent", 0);
  92. if (prop == NULL) {
  93. debug("\n%s: ERROR: missing msi-parent: PCIe%d\n",
  94. __func__, pcie->idx);
  95. return;
  96. }
  97. phandle = fdt32_to_cpu(*prop);
  98. /* set one msi-map row */
  99. fdt_appendprop_u32(blob, nodeoffset, "msi-map", devid);
  100. fdt_appendprop_u32(blob, nodeoffset, "msi-map", phandle);
  101. fdt_appendprop_u32(blob, nodeoffset, "msi-map", streamid);
  102. fdt_appendprop_u32(blob, nodeoffset, "msi-map", 1);
  103. }
  104. /*
  105. * An iommu-map is a property to be added to the pci controller
  106. * node. It is a table, where each entry consists of 4 fields
  107. * e.g.:
  108. *
  109. * iommu-map = <[devid] [phandle-to-iommu-ctrl] [stream-id] [count]
  110. * [devid] [phandle-to-iommu-ctrl] [stream-id] [count]>;
  111. */
  112. static void fdt_pcie_set_iommu_map_entry_ls(void *blob,
  113. struct ls_pcie_rc *pcie_rc,
  114. u32 devid, u32 streamid)
  115. {
  116. u32 *prop;
  117. u32 iommu_map[4];
  118. int nodeoffset;
  119. int lenp;
  120. uint svr;
  121. char *compat = NULL;
  122. struct ls_pcie *pcie = pcie_rc->pcie;
  123. /* find pci controller node */
  124. nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  125. pcie_rc->dbi_res.start);
  126. if (nodeoffset < 0) {
  127. #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  128. svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  129. if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  130. svr == SVR_LS2048A || svr == SVR_LS2044A ||
  131. svr == SVR_LS2081A || svr == SVR_LS2041A)
  132. compat = "fsl,ls2088a-pcie";
  133. else
  134. compat = CONFIG_FSL_PCIE_COMPAT;
  135. if (compat)
  136. nodeoffset = fdt_node_offset_by_compat_reg(blob,
  137. compat, pcie_rc->dbi_res.start);
  138. #endif
  139. if (nodeoffset < 0)
  140. return;
  141. }
  142. /* get phandle to iommu controller */
  143. prop = fdt_getprop_w(blob, nodeoffset, "iommu-map", &lenp);
  144. if (prop == NULL) {
  145. debug("\n%s: ERROR: missing iommu-map: PCIe%d\n",
  146. __func__, pcie->idx);
  147. return;
  148. }
  149. /* set iommu-map row */
  150. iommu_map[0] = cpu_to_fdt32(devid);
  151. iommu_map[1] = *++prop;
  152. iommu_map[2] = cpu_to_fdt32(streamid);
  153. iommu_map[3] = cpu_to_fdt32(1);
  154. if (devid == 0) {
  155. fdt_setprop_inplace(blob, nodeoffset, "iommu-map",
  156. iommu_map, 16);
  157. } else {
  158. fdt_appendprop(blob, nodeoffset, "iommu-map", iommu_map, 16);
  159. }
  160. }
  161. static void fdt_fixup_pcie_ls(void *blob)
  162. {
  163. struct udevice *dev, *bus;
  164. struct ls_pcie_rc *pcie_rc;
  165. int streamid;
  166. int index;
  167. pci_dev_t bdf;
  168. /* Scan all known buses */
  169. for (pci_find_first_device(&dev);
  170. dev;
  171. pci_find_next_device(&dev)) {
  172. for (bus = dev; device_is_on_pci_bus(bus);)
  173. bus = bus->parent;
  174. /* Only do the fixups for layerscape PCIe controllers */
  175. if (!device_is_compatible(bus, "fsl,ls-pcie") &&
  176. !device_is_compatible(bus, CONFIG_FSL_PCIE_COMPAT))
  177. continue;
  178. pcie_rc = dev_get_priv(bus);
  179. streamid = pcie_next_streamid(pcie_rc->stream_id_cur,
  180. pcie_rc->pcie->idx);
  181. if (streamid < 0) {
  182. debug("ERROR: no stream ids free\n");
  183. continue;
  184. } else {
  185. pcie_rc->stream_id_cur++;
  186. }
  187. index = ls_pcie_next_lut_index(pcie_rc);
  188. if (index < 0) {
  189. debug("ERROR: no LUT indexes free\n");
  190. continue;
  191. }
  192. /* the DT fixup must be relative to the hose first_busno */
  193. bdf = dm_pci_get_bdf(dev) - PCI_BDF(bus->seq, 0, 0);
  194. /* map PCI b.d.f to streamID in LUT */
  195. ls_pcie_lut_set_mapping(pcie_rc, index, bdf >> 8,
  196. streamid);
  197. /* update msi-map in device tree */
  198. fdt_pcie_set_msi_map_entry_ls(blob, pcie_rc, bdf >> 8,
  199. streamid);
  200. /* update iommu-map in device tree */
  201. fdt_pcie_set_iommu_map_entry_ls(blob, pcie_rc, bdf >> 8,
  202. streamid);
  203. }
  204. pcie_board_fix_fdt(blob);
  205. }
  206. #endif
  207. static void ft_pcie_rc_fix(void *blob, struct ls_pcie_rc *pcie_rc)
  208. {
  209. int off;
  210. uint svr;
  211. char *compat = NULL;
  212. struct ls_pcie *pcie = pcie_rc->pcie;
  213. off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
  214. pcie_rc->dbi_res.start);
  215. if (off < 0) {
  216. #ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
  217. svr = (get_svr() >> SVR_VAR_PER_SHIFT) & 0xFFFFFE;
  218. if (svr == SVR_LS2088A || svr == SVR_LS2084A ||
  219. svr == SVR_LS2048A || svr == SVR_LS2044A ||
  220. svr == SVR_LS2081A || svr == SVR_LS2041A)
  221. compat = "fsl,ls2088a-pcie";
  222. else
  223. compat = CONFIG_FSL_PCIE_COMPAT;
  224. if (compat)
  225. off = fdt_node_offset_by_compat_reg(blob,
  226. compat, pcie_rc->dbi_res.start);
  227. #endif
  228. if (off < 0)
  229. return;
  230. }
  231. if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_BRIDGE)
  232. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  233. else
  234. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  235. }
  236. static void ft_pcie_ep_fix(void *blob, struct ls_pcie_rc *pcie_rc)
  237. {
  238. int off;
  239. struct ls_pcie *pcie = pcie_rc->pcie;
  240. off = fdt_node_offset_by_compat_reg(blob, CONFIG_FSL_PCIE_EP_COMPAT,
  241. pcie_rc->dbi_res.start);
  242. if (off < 0)
  243. return;
  244. if (pcie_rc->enabled && pcie->mode == PCI_HEADER_TYPE_NORMAL)
  245. fdt_set_node_status(blob, off, FDT_STATUS_OKAY, 0);
  246. else
  247. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  248. }
  249. static void ft_pcie_ls_setup(void *blob, struct ls_pcie_rc *pcie_rc)
  250. {
  251. ft_pcie_ep_fix(blob, pcie_rc);
  252. ft_pcie_rc_fix(blob, pcie_rc);
  253. }
  254. /* Fixup Kernel DT for PCIe */
  255. void ft_pci_setup_ls(void *blob, struct bd_info *bd)
  256. {
  257. struct ls_pcie_rc *pcie_rc;
  258. list_for_each_entry(pcie_rc, &ls_pcie_list, list)
  259. ft_pcie_ls_setup(blob, pcie_rc);
  260. #if defined(CONFIG_FSL_LSCH3) || defined(CONFIG_FSL_LSCH2)
  261. fdt_fixup_pcie_ls(blob);
  262. #endif
  263. }
  264. #else /* !CONFIG_OF_BOARD_SETUP */
  265. void ft_pci_setup_ls(void *blob, struct bd_info *bd)
  266. {
  267. }
  268. #endif