pcie_fsl.c 15 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * Copyright 2019 NXP
  4. *
  5. * PCIe DM U-Boot driver for Freescale PowerPC SoCs
  6. * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
  7. */
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <malloc.h>
  11. #include <mapmem.h>
  12. #include <pci.h>
  13. #include <asm/fsl_pci.h>
  14. #include <asm/fsl_serdes.h>
  15. #include <asm/io.h>
  16. #include <linux/delay.h>
  17. #include "pcie_fsl.h"
  18. #include <dm/device_compat.h>
  19. LIST_HEAD(fsl_pcie_list);
  20. static int fsl_pcie_link_up(struct fsl_pcie *pcie);
  21. static int fsl_pcie_addr_valid(struct fsl_pcie *pcie, pci_dev_t bdf)
  22. {
  23. struct udevice *bus = pcie->bus;
  24. if (!pcie->enabled)
  25. return -ENXIO;
  26. if (PCI_BUS(bdf) < bus->seq)
  27. return -EINVAL;
  28. if (PCI_BUS(bdf) > bus->seq && (!fsl_pcie_link_up(pcie) || pcie->mode))
  29. return -EINVAL;
  30. if (PCI_BUS(bdf) == bus->seq && (PCI_DEV(bdf) > 0 || PCI_FUNC(bdf) > 0))
  31. return -EINVAL;
  32. if (PCI_BUS(bdf) == (bus->seq + 1) && (PCI_DEV(bdf) > 0))
  33. return -EINVAL;
  34. return 0;
  35. }
  36. static int fsl_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
  37. uint offset, ulong *valuep,
  38. enum pci_size_t size)
  39. {
  40. struct fsl_pcie *pcie = dev_get_priv(bus);
  41. ccsr_fsl_pci_t *regs = pcie->regs;
  42. u32 val;
  43. if (fsl_pcie_addr_valid(pcie, bdf)) {
  44. *valuep = pci_get_ff(size);
  45. return 0;
  46. }
  47. bdf = bdf - PCI_BDF(bus->seq, 0, 0);
  48. val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
  49. out_be32(&regs->cfg_addr, val);
  50. sync();
  51. switch (size) {
  52. case PCI_SIZE_8:
  53. *valuep = in_8((u8 *)&regs->cfg_data + (offset & 3));
  54. break;
  55. case PCI_SIZE_16:
  56. *valuep = in_le16((u16 *)((u8 *)&regs->cfg_data +
  57. (offset & 2)));
  58. break;
  59. case PCI_SIZE_32:
  60. *valuep = in_le32(&regs->cfg_data);
  61. break;
  62. }
  63. return 0;
  64. }
  65. static int fsl_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
  66. uint offset, ulong value,
  67. enum pci_size_t size)
  68. {
  69. struct fsl_pcie *pcie = dev_get_priv(bus);
  70. ccsr_fsl_pci_t *regs = pcie->regs;
  71. u32 val;
  72. u8 val_8;
  73. u16 val_16;
  74. u32 val_32;
  75. if (fsl_pcie_addr_valid(pcie, bdf))
  76. return 0;
  77. bdf = bdf - PCI_BDF(bus->seq, 0, 0);
  78. val = bdf | (offset & 0xfc) | ((offset & 0xf00) << 16) | 0x80000000;
  79. out_be32(&regs->cfg_addr, val);
  80. sync();
  81. switch (size) {
  82. case PCI_SIZE_8:
  83. val_8 = value;
  84. out_8((u8 *)&regs->cfg_data + (offset & 3), val_8);
  85. break;
  86. case PCI_SIZE_16:
  87. val_16 = value;
  88. out_le16((u16 *)((u8 *)&regs->cfg_data + (offset & 2)), val_16);
  89. break;
  90. case PCI_SIZE_32:
  91. val_32 = value;
  92. out_le32(&regs->cfg_data, val_32);
  93. break;
  94. }
  95. return 0;
  96. }
  97. static int fsl_pcie_hose_read_config(struct fsl_pcie *pcie, uint offset,
  98. ulong *valuep, enum pci_size_t size)
  99. {
  100. int ret;
  101. struct udevice *bus = pcie->bus;
  102. ret = fsl_pcie_read_config(bus, PCI_BDF(bus->seq, 0, 0),
  103. offset, valuep, size);
  104. return ret;
  105. }
  106. static int fsl_pcie_hose_write_config(struct fsl_pcie *pcie, uint offset,
  107. ulong value, enum pci_size_t size)
  108. {
  109. struct udevice *bus = pcie->bus;
  110. return fsl_pcie_write_config(bus, PCI_BDF(bus->seq, 0, 0),
  111. offset, value, size);
  112. }
  113. static int fsl_pcie_hose_read_config_byte(struct fsl_pcie *pcie, uint offset,
  114. u8 *valuep)
  115. {
  116. ulong val;
  117. int ret;
  118. ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_8);
  119. *valuep = val;
  120. return ret;
  121. }
  122. static int fsl_pcie_hose_read_config_word(struct fsl_pcie *pcie, uint offset,
  123. u16 *valuep)
  124. {
  125. ulong val;
  126. int ret;
  127. ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_16);
  128. *valuep = val;
  129. return ret;
  130. }
  131. static int fsl_pcie_hose_read_config_dword(struct fsl_pcie *pcie, uint offset,
  132. u32 *valuep)
  133. {
  134. ulong val;
  135. int ret;
  136. ret = fsl_pcie_hose_read_config(pcie, offset, &val, PCI_SIZE_32);
  137. *valuep = val;
  138. return ret;
  139. }
  140. static int fsl_pcie_hose_write_config_byte(struct fsl_pcie *pcie, uint offset,
  141. u8 value)
  142. {
  143. return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_8);
  144. }
  145. static int fsl_pcie_hose_write_config_word(struct fsl_pcie *pcie, uint offset,
  146. u16 value)
  147. {
  148. return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_16);
  149. }
  150. static int fsl_pcie_hose_write_config_dword(struct fsl_pcie *pcie, uint offset,
  151. u32 value)
  152. {
  153. return fsl_pcie_hose_write_config(pcie, offset, value, PCI_SIZE_32);
  154. }
  155. static int fsl_pcie_link_up(struct fsl_pcie *pcie)
  156. {
  157. ccsr_fsl_pci_t *regs = pcie->regs;
  158. u16 ltssm;
  159. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  160. ltssm = (in_be32(&regs->pex_csr0)
  161. & PEX_CSR0_LTSSM_MASK) >> PEX_CSR0_LTSSM_SHIFT;
  162. return ltssm == LTSSM_L0_REV3;
  163. }
  164. fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
  165. return ltssm == LTSSM_L0;
  166. }
  167. static bool fsl_pcie_is_agent(struct fsl_pcie *pcie)
  168. {
  169. u8 header_type;
  170. fsl_pcie_hose_read_config_byte(pcie, PCI_HEADER_TYPE, &header_type);
  171. return (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
  172. }
  173. static int fsl_pcie_setup_law(struct fsl_pcie *pcie)
  174. {
  175. struct pci_region *io, *mem, *pref;
  176. pci_get_regions(pcie->bus, &io, &mem, &pref);
  177. if (mem)
  178. set_next_law(mem->phys_start,
  179. law_size_bits(mem->size),
  180. pcie->law_trgt_if);
  181. if (io)
  182. set_next_law(io->phys_start,
  183. law_size_bits(io->size),
  184. pcie->law_trgt_if);
  185. return 0;
  186. }
  187. static void fsl_pcie_config_ready(struct fsl_pcie *pcie)
  188. {
  189. ccsr_fsl_pci_t *regs = pcie->regs;
  190. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  191. setbits_be32(&regs->config, FSL_PCIE_V3_CFG_RDY);
  192. return;
  193. }
  194. fsl_pcie_hose_write_config_byte(pcie, FSL_PCIE_CFG_RDY, 0x1);
  195. }
  196. static int fsl_pcie_setup_outbound_win(struct fsl_pcie *pcie, int idx,
  197. int type, u64 phys, u64 bus_addr,
  198. pci_size_t size)
  199. {
  200. ccsr_fsl_pci_t *regs = pcie->regs;
  201. pot_t *po = &regs->pot[idx];
  202. u32 war, sz;
  203. if (idx < 0)
  204. return -EINVAL;
  205. out_be32(&po->powbar, phys >> 12);
  206. out_be32(&po->potar, bus_addr >> 12);
  207. #ifdef CONFIG_SYS_PCI_64BIT
  208. out_be32(&po->potear, bus_addr >> 44);
  209. #else
  210. out_be32(&po->potear, 0);
  211. #endif
  212. sz = (__ilog2_u64((u64)size) - 1);
  213. war = POWAR_EN | sz;
  214. if (type == PCI_REGION_IO)
  215. war |= POWAR_IO_READ | POWAR_IO_WRITE;
  216. else
  217. war |= POWAR_MEM_READ | POWAR_MEM_WRITE;
  218. out_be32(&po->powar, war);
  219. return 0;
  220. }
  221. static int fsl_pcie_setup_inbound_win(struct fsl_pcie *pcie, int idx,
  222. bool pf, u64 phys, u64 bus_addr,
  223. pci_size_t size)
  224. {
  225. ccsr_fsl_pci_t *regs = pcie->regs;
  226. pit_t *pi = &regs->pit[idx];
  227. u32 sz = (__ilog2_u64(size) - 1);
  228. u32 flag = PIWAR_LOCAL;
  229. if (idx < 0)
  230. return -EINVAL;
  231. out_be32(&pi->pitar, phys >> 12);
  232. out_be32(&pi->piwbar, bus_addr >> 12);
  233. #ifdef CONFIG_SYS_PCI_64BIT
  234. out_be32(&pi->piwbear, bus_addr >> 44);
  235. #else
  236. out_be32(&pi->piwbear, 0);
  237. #endif
  238. #ifdef CONFIG_SYS_FSL_ERRATUM_A005434
  239. flag = 0;
  240. #endif
  241. flag |= PIWAR_EN | PIWAR_READ_SNOOP | PIWAR_WRITE_SNOOP;
  242. if (pf)
  243. flag |= PIWAR_PF;
  244. out_be32(&pi->piwar, flag | sz);
  245. return 0;
  246. }
  247. static int fsl_pcie_setup_outbound_wins(struct fsl_pcie *pcie)
  248. {
  249. struct pci_region *io, *mem, *pref;
  250. int idx = 1; /* skip 0 */
  251. pci_get_regions(pcie->bus, &io, &mem, &pref);
  252. if (io)
  253. /* ATU : OUTBOUND : IO */
  254. fsl_pcie_setup_outbound_win(pcie, idx++,
  255. PCI_REGION_IO,
  256. io->phys_start,
  257. io->bus_start,
  258. io->size);
  259. if (mem)
  260. /* ATU : OUTBOUND : MEM */
  261. fsl_pcie_setup_outbound_win(pcie, idx++,
  262. PCI_REGION_MEM,
  263. mem->phys_start,
  264. mem->bus_start,
  265. mem->size);
  266. return 0;
  267. }
  268. static int fsl_pcie_setup_inbound_wins(struct fsl_pcie *pcie)
  269. {
  270. phys_addr_t phys_start = CONFIG_SYS_PCI_MEMORY_PHYS;
  271. pci_addr_t bus_start = CONFIG_SYS_PCI_MEMORY_BUS;
  272. u64 sz = min((u64)gd->ram_size, (1ull << 32));
  273. pci_size_t pci_sz;
  274. int idx;
  275. if (pcie->block_rev >= PEX_IP_BLK_REV_2_2)
  276. idx = 2;
  277. else
  278. idx = 3;
  279. pci_sz = 1ull << __ilog2_u64(sz);
  280. dev_dbg(pcie->bus, "R0 bus_start: %llx phys_start: %llx size: %llx\n",
  281. (u64)bus_start, (u64)phys_start, (u64)sz);
  282. /* if we aren't an exact power of two match, pci_sz is smaller
  283. * round it up to the next power of two. We report the actual
  284. * size to pci region tracking.
  285. */
  286. if (pci_sz != sz)
  287. sz = 2ull << __ilog2_u64(sz);
  288. fsl_pcie_setup_inbound_win(pcie, idx--, true,
  289. CONFIG_SYS_PCI_MEMORY_PHYS,
  290. CONFIG_SYS_PCI_MEMORY_BUS, sz);
  291. #if defined(CONFIG_PHYS_64BIT) && defined(CONFIG_SYS_PCI_64BIT)
  292. /*
  293. * On 64-bit capable systems, set up a mapping for all of DRAM
  294. * in high pci address space.
  295. */
  296. pci_sz = 1ull << __ilog2_u64(gd->ram_size);
  297. /* round up to the next largest power of two */
  298. if (gd->ram_size > pci_sz)
  299. pci_sz = 1ull << (__ilog2_u64(gd->ram_size) + 1);
  300. dev_dbg(pcie->bus, "R64 bus_start: %llx phys_start: %llx size: %llx\n",
  301. (u64)CONFIG_SYS_PCI64_MEMORY_BUS,
  302. (u64)CONFIG_SYS_PCI_MEMORY_PHYS, (u64)pci_sz);
  303. fsl_pcie_setup_inbound_win(pcie, idx--, true,
  304. CONFIG_SYS_PCI_MEMORY_PHYS,
  305. CONFIG_SYS_PCI64_MEMORY_BUS, pci_sz);
  306. #endif
  307. return 0;
  308. }
  309. static int fsl_pcie_init_atmu(struct fsl_pcie *pcie)
  310. {
  311. fsl_pcie_setup_outbound_wins(pcie);
  312. fsl_pcie_setup_inbound_wins(pcie);
  313. return 0;
  314. }
  315. static int fsl_pcie_init_port(struct fsl_pcie *pcie)
  316. {
  317. ccsr_fsl_pci_t *regs = pcie->regs;
  318. u32 val_32;
  319. u16 val_16;
  320. fsl_pcie_init_atmu(pcie);
  321. #ifdef CONFIG_FSL_PCIE_DISABLE_ASPM
  322. val_32 = 0;
  323. fsl_pcie_hose_read_config_dword(pcie, PCI_LCR, &val_32);
  324. val_32 &= ~0x03;
  325. fsl_pcie_hose_write_config_dword(pcie, PCI_LCR, val_32);
  326. udelay(1);
  327. #endif
  328. #ifdef CONFIG_FSL_PCIE_RESET
  329. u16 ltssm;
  330. int i;
  331. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  332. /* assert PCIe reset */
  333. setbits_be32(&regs->pdb_stat, 0x08000000);
  334. (void)in_be32(&regs->pdb_stat);
  335. udelay(1000);
  336. /* clear PCIe reset */
  337. clrbits_be32(&regs->pdb_stat, 0x08000000);
  338. asm("sync;isync");
  339. for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
  340. udelay(1000);
  341. } else {
  342. fsl_pcie_hose_read_config_word(pcie, PCI_LTSSM, &ltssm);
  343. if (ltssm == 1) {
  344. /* assert PCIe reset */
  345. setbits_be32(&regs->pdb_stat, 0x08000000);
  346. (void)in_be32(&regs->pdb_stat);
  347. udelay(100);
  348. /* clear PCIe reset */
  349. clrbits_be32(&regs->pdb_stat, 0x08000000);
  350. asm("sync;isync");
  351. for (i = 0; i < 100 &&
  352. !fsl_pcie_link_up(pcie); i++)
  353. udelay(1000);
  354. }
  355. }
  356. #endif
  357. #ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
  358. if (!fsl_pcie_link_up(pcie)) {
  359. serdes_corenet_t *srds_regs;
  360. srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  361. val_32 = in_be32(&srds_regs->srdspccr0);
  362. if ((val_32 >> 28) == 3) {
  363. int i;
  364. out_be32(&srds_regs->srdspccr0, 2 << 28);
  365. setbits_be32(&regs->pdb_stat, 0x08000000);
  366. in_be32(&regs->pdb_stat);
  367. udelay(100);
  368. clrbits_be32(&regs->pdb_stat, 0x08000000);
  369. asm("sync;isync");
  370. for (i = 0; i < 100 && !fsl_pcie_link_up(pcie); i++)
  371. udelay(1000);
  372. }
  373. }
  374. #endif
  375. /*
  376. * The Read-Only Write Enable bit defaults to 1 instead of 0.
  377. * Set to 0 to protect the read-only registers.
  378. */
  379. #ifdef CONFIG_SYS_FSL_ERRATUM_A007815
  380. clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
  381. #endif
  382. /*
  383. * Enable All Error Interrupts except
  384. * - Master abort (pci)
  385. * - Master PERR (pci)
  386. * - ICCA (PCIe)
  387. */
  388. out_be32(&regs->peer, ~0x20140);
  389. /* set URR, FER, NFER (but not CER) */
  390. fsl_pcie_hose_read_config_dword(pcie, PCI_DCR, &val_32);
  391. val_32 |= 0xf000e;
  392. fsl_pcie_hose_write_config_dword(pcie, PCI_DCR, val_32);
  393. /* Clear all error indications */
  394. out_be32(&regs->pme_msg_det, 0xffffffff);
  395. out_be32(&regs->pme_msg_int_en, 0xffffffff);
  396. out_be32(&regs->pedr, 0xffffffff);
  397. fsl_pcie_hose_read_config_word(pcie, PCI_DSR, &val_16);
  398. if (val_16)
  399. fsl_pcie_hose_write_config_word(pcie, PCI_DSR, 0xffff);
  400. fsl_pcie_hose_read_config_word(pcie, PCI_SEC_STATUS, &val_16);
  401. if (val_16)
  402. fsl_pcie_hose_write_config_word(pcie, PCI_SEC_STATUS, 0xffff);
  403. return 0;
  404. }
  405. static int fsl_pcie_fixup_classcode(struct fsl_pcie *pcie)
  406. {
  407. ccsr_fsl_pci_t *regs = pcie->regs;
  408. u32 classcode_reg;
  409. u32 val;
  410. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0) {
  411. classcode_reg = PCI_CLASS_REVISION;
  412. setbits_be32(&regs->dbi_ro_wr_en, 0x01);
  413. } else {
  414. classcode_reg = CSR_CLASSCODE;
  415. }
  416. fsl_pcie_hose_read_config_dword(pcie, classcode_reg, &val);
  417. val &= 0xff;
  418. val |= PCI_CLASS_BRIDGE_PCI << 16;
  419. fsl_pcie_hose_write_config_dword(pcie, classcode_reg, val);
  420. if (pcie->block_rev >= PEX_IP_BLK_REV_3_0)
  421. clrbits_be32(&regs->dbi_ro_wr_en, 0x01);
  422. return 0;
  423. }
  424. static int fsl_pcie_init_rc(struct fsl_pcie *pcie)
  425. {
  426. return fsl_pcie_fixup_classcode(pcie);
  427. }
  428. static int fsl_pcie_init_ep(struct fsl_pcie *pcie)
  429. {
  430. fsl_pcie_config_ready(pcie);
  431. return 0;
  432. }
  433. static int fsl_pcie_probe(struct udevice *dev)
  434. {
  435. struct fsl_pcie *pcie = dev_get_priv(dev);
  436. ccsr_fsl_pci_t *regs = pcie->regs;
  437. u16 val_16;
  438. pcie->bus = dev;
  439. pcie->block_rev = in_be32(&regs->block_rev1);
  440. list_add(&pcie->list, &fsl_pcie_list);
  441. pcie->enabled = is_serdes_configured(PCIE1 + pcie->idx);
  442. if (!pcie->enabled) {
  443. printf("PCIe%d: %s disabled\n", pcie->idx, dev->name);
  444. return 0;
  445. }
  446. fsl_pcie_setup_law(pcie);
  447. pcie->mode = fsl_pcie_is_agent(pcie);
  448. fsl_pcie_init_port(pcie);
  449. printf("PCIe%d: %s ", pcie->idx, dev->name);
  450. if (pcie->mode) {
  451. printf("Endpoint");
  452. fsl_pcie_init_ep(pcie);
  453. } else {
  454. printf("Root Complex");
  455. fsl_pcie_init_rc(pcie);
  456. }
  457. if (!fsl_pcie_link_up(pcie)) {
  458. printf(": %s\n", pcie->mode ? "undetermined link" : "no link");
  459. return 0;
  460. }
  461. fsl_pcie_hose_read_config_word(pcie, PCI_LSR, &val_16);
  462. printf(": x%d gen%d\n", (val_16 & 0x3f0) >> 4, (val_16 & 0xf));
  463. return 0;
  464. }
  465. static int fsl_pcie_ofdata_to_platdata(struct udevice *dev)
  466. {
  467. struct fsl_pcie *pcie = dev_get_priv(dev);
  468. struct fsl_pcie_data *info;
  469. int ret;
  470. pcie->regs = dev_remap_addr(dev);
  471. if (!pcie->regs) {
  472. pr_err("\"reg\" resource not found\n");
  473. return -EINVAL;
  474. }
  475. ret = dev_read_u32(dev, "law_trgt_if", &pcie->law_trgt_if);
  476. if (ret < 0) {
  477. pr_err("\"law_trgt_if\" not found\n");
  478. return ret;
  479. }
  480. info = (struct fsl_pcie_data *)dev_get_driver_data(dev);
  481. pcie->info = info;
  482. pcie->idx = abs((u32)(dev_read_addr(dev) & info->block_offset_mask) -
  483. info->block_offset) / info->stride;
  484. return 0;
  485. }
  486. static const struct dm_pci_ops fsl_pcie_ops = {
  487. .read_config = fsl_pcie_read_config,
  488. .write_config = fsl_pcie_write_config,
  489. };
  490. static struct fsl_pcie_data p1_p2_data = {
  491. .block_offset = 0xa000,
  492. .block_offset_mask = 0xffff,
  493. .stride = 0x1000,
  494. };
  495. static struct fsl_pcie_data p2041_data = {
  496. .block_offset = 0x200000,
  497. .block_offset_mask = 0x3fffff,
  498. .stride = 0x1000,
  499. };
  500. static struct fsl_pcie_data t2080_data = {
  501. .block_offset = 0x240000,
  502. .block_offset_mask = 0x3fffff,
  503. .stride = 0x10000,
  504. };
  505. static const struct udevice_id fsl_pcie_ids[] = {
  506. { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data },
  507. { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data },
  508. { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data },
  509. { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
  510. { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data },
  511. { .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data },
  512. { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data },
  513. { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data },
  514. { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
  515. { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data },
  516. { }
  517. };
  518. U_BOOT_DRIVER(fsl_pcie) = {
  519. .name = "fsl_pcie",
  520. .id = UCLASS_PCI,
  521. .of_match = fsl_pcie_ids,
  522. .ops = &fsl_pcie_ops,
  523. .ofdata_to_platdata = fsl_pcie_ofdata_to_platdata,
  524. .probe = fsl_pcie_probe,
  525. .priv_auto_alloc_size = sizeof(struct fsl_pcie),
  526. };