pci_sh7751.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * SH7751 PCI Controller (PCIC) for U-Boot.
  4. * (C) Dustin McIntire (dustin@sensoria.com)
  5. * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
  6. */
  7. #include <common.h>
  8. #include <dm.h>
  9. #include <pci.h>
  10. #include <asm/processor.h>
  11. #include <asm/io.h>
  12. #include <asm/pci.h>
  13. #include <linux/bitops.h>
  14. #include <linux/delay.h>
  15. /* Register addresses and such */
  16. #define SH7751_BCR1 (vu_long *)0xFF800000
  17. #define SH7751_BCR2 (vu_short *)0xFF800004
  18. #define SH7751_WCR1 (vu_long *)0xFF800008
  19. #define SH7751_WCR2 (vu_long *)0xFF80000C
  20. #define SH7751_WCR3 (vu_long *)0xFF800010
  21. #define SH7751_MCR (vu_long *)0xFF800014
  22. #define SH7751_BCR3 (vu_short *)0xFF800050
  23. #define SH7751_PCICONF0 (vu_long *)0xFE200000
  24. #define SH7751_PCICONF1 (vu_long *)0xFE200004
  25. #define SH7751_PCICONF2 (vu_long *)0xFE200008
  26. #define SH7751_PCICONF3 (vu_long *)0xFE20000C
  27. #define SH7751_PCICONF4 (vu_long *)0xFE200010
  28. #define SH7751_PCICONF5 (vu_long *)0xFE200014
  29. #define SH7751_PCICONF6 (vu_long *)0xFE200018
  30. #define SH7751_PCICR (vu_long *)0xFE200100
  31. #define SH7751_PCILSR0 (vu_long *)0xFE200104
  32. #define SH7751_PCILSR1 (vu_long *)0xFE200108
  33. #define SH7751_PCILAR0 (vu_long *)0xFE20010C
  34. #define SH7751_PCILAR1 (vu_long *)0xFE200110
  35. #define SH7751_PCIMBR (vu_long *)0xFE2001C4
  36. #define SH7751_PCIIOBR (vu_long *)0xFE2001C8
  37. #define SH7751_PCIPINT (vu_long *)0xFE2001CC
  38. #define SH7751_PCIPINTM (vu_long *)0xFE2001D0
  39. #define SH7751_PCICLKR (vu_long *)0xFE2001D4
  40. #define SH7751_PCIBCR1 (vu_long *)0xFE2001E0
  41. #define SH7751_PCIBCR2 (vu_long *)0xFE2001E4
  42. #define SH7751_PCIWCR1 (vu_long *)0xFE2001E8
  43. #define SH7751_PCIWCR2 (vu_long *)0xFE2001EC
  44. #define SH7751_PCIWCR3 (vu_long *)0xFE2001F0
  45. #define SH7751_PCIMCR (vu_long *)0xFE2001F4
  46. #define SH7751_PCIBCR3 (vu_long *)0xFE2001F8
  47. #define BCR1_BREQEN 0x00080000
  48. #define PCI_SH7751_ID 0x35051054
  49. #define PCI_SH7751R_ID 0x350E1054
  50. #define SH7751_PCICONF1_WCC 0x00000080
  51. #define SH7751_PCICONF1_PER 0x00000040
  52. #define SH7751_PCICONF1_BUM 0x00000004
  53. #define SH7751_PCICONF1_MES 0x00000002
  54. #define SH7751_PCICONF1_CMDS 0x000000C6
  55. #define SH7751_PCI_HOST_BRIDGE 0x6
  56. #define SH7751_PCICR_PREFIX 0xa5000000
  57. #define SH7751_PCICR_PRST 0x00000002
  58. #define SH7751_PCICR_CFIN 0x00000001
  59. #define SH7751_PCIPINT_D3 0x00000002
  60. #define SH7751_PCIPINT_D0 0x00000001
  61. #define SH7751_PCICLKR_PREFIX 0xa5000000
  62. #define SH7751_PCI_MEM_BASE 0xFD000000
  63. #define SH7751_PCI_MEM_SIZE 0x01000000
  64. #define SH7751_PCI_IO_BASE 0xFE240000
  65. #define SH7751_PCI_IO_SIZE 0x00040000
  66. #define SH7751_PCIPAR (vu_long *)0xFE2001C0
  67. #define SH7751_PCIPDR (vu_long *)0xFE200220
  68. #define p4_in(addr) (*addr)
  69. #define p4_out(data, addr) (*addr) = (data)
  70. static int sh7751_pci_addr_valid(pci_dev_t d, uint offset)
  71. {
  72. if (PCI_FUNC(d))
  73. return -EINVAL;
  74. return 0;
  75. }
  76. static u32 get_bus_address(const struct udevice *dev, pci_dev_t bdf, u32 offset)
  77. {
  78. return BIT(31) | (PCI_DEV(bdf) << 8) | (offset & ~3);
  79. }
  80. static int sh7751_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
  81. uint offset, ulong *value,
  82. enum pci_size_t size)
  83. {
  84. u32 addr, reg;
  85. int ret;
  86. ret = sh7751_pci_addr_valid(bdf, offset);
  87. if (ret) {
  88. *value = pci_get_ff(size);
  89. return 0;
  90. }
  91. addr = get_bus_address(dev, bdf, offset);
  92. p4_out(addr, SH7751_PCIPAR);
  93. reg = p4_in(SH7751_PCIPDR);
  94. *value = pci_conv_32_to_size(reg, offset, size);
  95. return 0;
  96. }
  97. static int sh7751_pci_write_config(struct udevice *dev, pci_dev_t bdf,
  98. uint offset, ulong value,
  99. enum pci_size_t size)
  100. {
  101. u32 addr, reg, old;
  102. int ret;
  103. ret = sh7751_pci_addr_valid(bdf, offset);
  104. if (ret)
  105. return ret;
  106. addr = get_bus_address(dev, bdf, offset);
  107. p4_out(addr, SH7751_PCIPAR);
  108. old = p4_in(SH7751_PCIPDR);
  109. reg = pci_conv_size_to_32(old, value, offset, size);
  110. p4_out(reg, SH7751_PCIPDR);
  111. return 0;
  112. }
  113. static int sh7751_pci_probe(struct udevice *dev)
  114. {
  115. /* Double-check that we're a 7751 or 7751R chip */
  116. if (p4_in(SH7751_PCICONF0) != PCI_SH7751_ID
  117. && p4_in(SH7751_PCICONF0) != PCI_SH7751R_ID) {
  118. printf("PCI: Unknown PCI host bridge.\n");
  119. return 1;
  120. }
  121. printf("PCI: SH7751 PCI host bridge found.\n");
  122. /* Double-check some BSC config settings */
  123. /* (Area 3 non-MPX 32-bit, PCI bus pins) */
  124. if ((p4_in(SH7751_BCR1) & 0x20008) == 0x20000) {
  125. printf("SH7751_BCR1 value is wrong(0x%08X)\n",
  126. (unsigned int)p4_in(SH7751_BCR1));
  127. return 2;
  128. }
  129. if ((p4_in(SH7751_BCR2) & 0xC0) != 0xC0) {
  130. printf("SH7751_BCR2 value is wrong(0x%08X)\n",
  131. (unsigned int)p4_in(SH7751_BCR2));
  132. return 3;
  133. }
  134. if (p4_in(SH7751_BCR2) & 0x01) {
  135. printf("SH7751_BCR2 value is wrong(0x%08X)\n",
  136. (unsigned int)p4_in(SH7751_BCR2));
  137. return 4;
  138. }
  139. /* Force BREQEN in BCR1 to allow PCIC access */
  140. p4_out((p4_in(SH7751_BCR1) | BCR1_BREQEN), SH7751_BCR1);
  141. /* Toggle PCI reset pin */
  142. p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_PRST), SH7751_PCICR);
  143. udelay(32);
  144. p4_out(SH7751_PCICR_PREFIX, SH7751_PCICR);
  145. /* Set cmd bits: WCC, PER, BUM, MES */
  146. /* (Addr/Data stepping, Parity enabled, Bus Master, Memory enabled) */
  147. p4_out(0xfb900047, SH7751_PCICONF1); /* K.Kino */
  148. /* Define this host as the host bridge */
  149. p4_out((SH7751_PCI_HOST_BRIDGE << 24), SH7751_PCICONF2);
  150. /* Force PCI clock(s) on */
  151. p4_out(0, SH7751_PCICLKR);
  152. p4_out(0x03, SH7751_PCICLKR);
  153. /* Clear powerdown IRQs, also mask them (unused) */
  154. p4_out((SH7751_PCIPINT_D0 | SH7751_PCIPINT_D3), SH7751_PCIPINT);
  155. p4_out(0, SH7751_PCIPINTM);
  156. p4_out(0xab000001, SH7751_PCICONF4);
  157. /* Set up target memory mappings (for external DMA access) */
  158. /* Map both P0 and P2 range to Area 3 RAM for ease of use */
  159. p4_out(CONFIG_SYS_SDRAM_SIZE - 0x100000, SH7751_PCILSR0);
  160. p4_out(CONFIG_SYS_SDRAM_BASE & 0x1FF00000, SH7751_PCILAR0);
  161. p4_out(CONFIG_SYS_SDRAM_BASE & 0xFFF00000, SH7751_PCICONF5);
  162. p4_out(0, SH7751_PCILSR1);
  163. p4_out(0, SH7751_PCILAR1);
  164. p4_out(0xd0000000, SH7751_PCICONF6);
  165. /* Map memory window to same address on PCI bus */
  166. p4_out(SH7751_PCI_MEM_BASE, SH7751_PCIMBR);
  167. /* Map IO window to same address on PCI bus */
  168. p4_out(SH7751_PCI_IO_BASE, SH7751_PCIIOBR);
  169. /* set BREQEN */
  170. p4_out(inl(SH7751_BCR1) | 0x00080000, SH7751_BCR1);
  171. /* Copy BSC registers into PCI BSC */
  172. p4_out(inl(SH7751_BCR1), SH7751_PCIBCR1);
  173. p4_out(inw(SH7751_BCR2), SH7751_PCIBCR2);
  174. p4_out(inw(SH7751_BCR3), SH7751_PCIBCR3);
  175. p4_out(inl(SH7751_WCR1), SH7751_PCIWCR1);
  176. p4_out(inl(SH7751_WCR2), SH7751_PCIWCR2);
  177. p4_out(inl(SH7751_WCR3), SH7751_PCIWCR3);
  178. p4_out(inl(SH7751_MCR), SH7751_PCIMCR);
  179. /* Finally, set central function init complete */
  180. p4_out((SH7751_PCICR_PREFIX | SH7751_PCICR_CFIN), SH7751_PCICR);
  181. return 0;
  182. }
  183. static const struct dm_pci_ops sh7751_pci_ops = {
  184. .read_config = sh7751_pci_read_config,
  185. .write_config = sh7751_pci_write_config,
  186. };
  187. static const struct udevice_id sh7751_pci_ids[] = {
  188. { .compatible = "renesas,pci-sh7751" },
  189. { }
  190. };
  191. U_BOOT_DRIVER(sh7751_pci) = {
  192. .name = "sh7751_pci",
  193. .id = UCLASS_PCI,
  194. .of_match = sh7751_pci_ids,
  195. .ops = &sh7751_pci_ops,
  196. .probe = sh7751_pci_probe,
  197. };