pci_mvebu.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCIe driver for Marvell MVEBU SoCs
  4. *
  5. * Based on Barebox drivers/pci/pci-mvebu.c
  6. *
  7. * Ported to U-Boot by:
  8. * Anton Schubert <anton.schubert@gmx.de>
  9. * Stefan Roese <sr@denx.de>
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <dm/device-internal.h>
  16. #include <dm/lists.h>
  17. #include <dm/of_access.h>
  18. #include <pci.h>
  19. #include <asm/io.h>
  20. #include <asm/arch/cpu.h>
  21. #include <asm/arch/soc.h>
  22. #include <linux/bitops.h>
  23. #include <linux/errno.h>
  24. #include <linux/ioport.h>
  25. #include <linux/mbus.h>
  26. DECLARE_GLOBAL_DATA_PTR;
  27. /* PCIe unit register offsets */
  28. #define SELECT(x, n) ((x >> n) & 1UL)
  29. #define PCIE_DEV_ID_OFF 0x0000
  30. #define PCIE_CMD_OFF 0x0004
  31. #define PCIE_DEV_REV_OFF 0x0008
  32. #define PCIE_BAR_LO_OFF(n) (0x0010 + ((n) << 3))
  33. #define PCIE_BAR_HI_OFF(n) (0x0014 + ((n) << 3))
  34. #define PCIE_CAPAB_OFF 0x0060
  35. #define PCIE_CTRL_STAT_OFF 0x0068
  36. #define PCIE_HEADER_LOG_4_OFF 0x0128
  37. #define PCIE_BAR_CTRL_OFF(n) (0x1804 + (((n) - 1) * 4))
  38. #define PCIE_WIN04_CTRL_OFF(n) (0x1820 + ((n) << 4))
  39. #define PCIE_WIN04_BASE_OFF(n) (0x1824 + ((n) << 4))
  40. #define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
  41. #define PCIE_WIN5_CTRL_OFF 0x1880
  42. #define PCIE_WIN5_BASE_OFF 0x1884
  43. #define PCIE_WIN5_REMAP_OFF 0x188c
  44. #define PCIE_CONF_ADDR_OFF 0x18f8
  45. #define PCIE_CONF_ADDR_EN BIT(31)
  46. #define PCIE_CONF_REG(r) ((((r) & 0xf00) << 16) | ((r) & 0xfc))
  47. #define PCIE_CONF_BUS(b) (((b) & 0xff) << 16)
  48. #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 11)
  49. #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 8)
  50. #define PCIE_CONF_ADDR(dev, reg) \
  51. (PCIE_CONF_BUS(PCI_BUS(dev)) | PCIE_CONF_DEV(PCI_DEV(dev)) | \
  52. PCIE_CONF_FUNC(PCI_FUNC(dev)) | PCIE_CONF_REG(reg) | \
  53. PCIE_CONF_ADDR_EN)
  54. #define PCIE_CONF_DATA_OFF 0x18fc
  55. #define PCIE_MASK_OFF 0x1910
  56. #define PCIE_MASK_ENABLE_INTS (0xf << 24)
  57. #define PCIE_CTRL_OFF 0x1a00
  58. #define PCIE_CTRL_X1_MODE BIT(0)
  59. #define PCIE_STAT_OFF 0x1a04
  60. #define PCIE_STAT_BUS (0xff << 8)
  61. #define PCIE_STAT_DEV (0x1f << 16)
  62. #define PCIE_STAT_LINK_DOWN BIT(0)
  63. #define PCIE_DEBUG_CTRL 0x1a60
  64. #define PCIE_DEBUG_SOFT_RESET BIT(20)
  65. struct mvebu_pcie {
  66. struct pci_controller hose;
  67. void __iomem *base;
  68. void __iomem *membase;
  69. struct resource mem;
  70. void __iomem *iobase;
  71. u32 port;
  72. u32 lane;
  73. int devfn;
  74. u32 lane_mask;
  75. pci_dev_t dev;
  76. char name[16];
  77. unsigned int mem_target;
  78. unsigned int mem_attr;
  79. };
  80. /*
  81. * MVEBU PCIe controller needs MEMORY and I/O BARs to be mapped
  82. * into SoCs address space. Each controller will map 128M of MEM
  83. * and 64K of I/O space when registered.
  84. */
  85. static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
  86. #define PCIE_MEM_SIZE (128 << 20)
  87. static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
  88. {
  89. u32 val;
  90. val = readl(pcie->base + PCIE_STAT_OFF);
  91. return !(val & PCIE_STAT_LINK_DOWN);
  92. }
  93. static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie *pcie, int busno)
  94. {
  95. u32 stat;
  96. stat = readl(pcie->base + PCIE_STAT_OFF);
  97. stat &= ~PCIE_STAT_BUS;
  98. stat |= busno << 8;
  99. writel(stat, pcie->base + PCIE_STAT_OFF);
  100. }
  101. static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie *pcie, int devno)
  102. {
  103. u32 stat;
  104. stat = readl(pcie->base + PCIE_STAT_OFF);
  105. stat &= ~PCIE_STAT_DEV;
  106. stat |= devno << 16;
  107. writel(stat, pcie->base + PCIE_STAT_OFF);
  108. }
  109. static int mvebu_pcie_get_local_bus_nr(struct mvebu_pcie *pcie)
  110. {
  111. u32 stat;
  112. stat = readl(pcie->base + PCIE_STAT_OFF);
  113. return (stat & PCIE_STAT_BUS) >> 8;
  114. }
  115. static int mvebu_pcie_get_local_dev_nr(struct mvebu_pcie *pcie)
  116. {
  117. u32 stat;
  118. stat = readl(pcie->base + PCIE_STAT_OFF);
  119. return (stat & PCIE_STAT_DEV) >> 16;
  120. }
  121. static inline struct mvebu_pcie *hose_to_pcie(struct pci_controller *hose)
  122. {
  123. return container_of(hose, struct mvebu_pcie, hose);
  124. }
  125. static int mvebu_pcie_read_config(const struct udevice *bus, pci_dev_t bdf,
  126. uint offset, ulong *valuep,
  127. enum pci_size_t size)
  128. {
  129. struct mvebu_pcie *pcie = dev_get_platdata(bus);
  130. int local_bus = PCI_BUS(pcie->dev);
  131. int local_dev = PCI_DEV(pcie->dev);
  132. u32 reg;
  133. u32 data;
  134. debug("PCIE CFG read: (b,d,f)=(%2d,%2d,%2d) ",
  135. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  136. /* Only allow one other device besides the local one on the local bus */
  137. if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
  138. if (local_dev == 0 && PCI_DEV(bdf) != 1) {
  139. debug("- out of range\n");
  140. /*
  141. * If local dev is 0, the first other dev can
  142. * only be 1
  143. */
  144. *valuep = pci_get_ff(size);
  145. return 0;
  146. } else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
  147. debug("- out of range\n");
  148. /*
  149. * If local dev is not 0, the first other dev can
  150. * only be 0
  151. */
  152. *valuep = pci_get_ff(size);
  153. return 0;
  154. }
  155. }
  156. /* write address */
  157. reg = PCIE_CONF_ADDR(bdf, offset);
  158. writel(reg, pcie->base + PCIE_CONF_ADDR_OFF);
  159. data = readl(pcie->base + PCIE_CONF_DATA_OFF);
  160. debug("(addr,val)=(0x%04x, 0x%08x)\n", offset, data);
  161. *valuep = pci_conv_32_to_size(data, offset, size);
  162. return 0;
  163. }
  164. static int mvebu_pcie_write_config(struct udevice *bus, pci_dev_t bdf,
  165. uint offset, ulong value,
  166. enum pci_size_t size)
  167. {
  168. struct mvebu_pcie *pcie = dev_get_platdata(bus);
  169. int local_bus = PCI_BUS(pcie->dev);
  170. int local_dev = PCI_DEV(pcie->dev);
  171. u32 data;
  172. debug("PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
  173. PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
  174. debug("(addr,val)=(0x%04x, 0x%08lx)\n", offset, value);
  175. /* Only allow one other device besides the local one on the local bus */
  176. if (PCI_BUS(bdf) == local_bus && PCI_DEV(bdf) != local_dev) {
  177. if (local_dev == 0 && PCI_DEV(bdf) != 1) {
  178. /*
  179. * If local dev is 0, the first other dev can
  180. * only be 1
  181. */
  182. return 0;
  183. } else if (local_dev != 0 && PCI_DEV(bdf) != 0) {
  184. /*
  185. * If local dev is not 0, the first other dev can
  186. * only be 0
  187. */
  188. return 0;
  189. }
  190. }
  191. writel(PCIE_CONF_ADDR(bdf, offset), pcie->base + PCIE_CONF_ADDR_OFF);
  192. data = pci_conv_size_to_32(0, value, offset, size);
  193. writel(data, pcie->base + PCIE_CONF_DATA_OFF);
  194. return 0;
  195. }
  196. /*
  197. * Setup PCIE BARs and Address Decode Wins:
  198. * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
  199. * WIN[0-3] -> DRAM bank[0-3]
  200. */
  201. static void mvebu_pcie_setup_wins(struct mvebu_pcie *pcie)
  202. {
  203. const struct mbus_dram_target_info *dram = mvebu_mbus_dram_info();
  204. u32 size;
  205. int i;
  206. /* First, disable and clear BARs and windows. */
  207. for (i = 1; i < 3; i++) {
  208. writel(0, pcie->base + PCIE_BAR_CTRL_OFF(i));
  209. writel(0, pcie->base + PCIE_BAR_LO_OFF(i));
  210. writel(0, pcie->base + PCIE_BAR_HI_OFF(i));
  211. }
  212. for (i = 0; i < 5; i++) {
  213. writel(0, pcie->base + PCIE_WIN04_CTRL_OFF(i));
  214. writel(0, pcie->base + PCIE_WIN04_BASE_OFF(i));
  215. writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
  216. }
  217. writel(0, pcie->base + PCIE_WIN5_CTRL_OFF);
  218. writel(0, pcie->base + PCIE_WIN5_BASE_OFF);
  219. writel(0, pcie->base + PCIE_WIN5_REMAP_OFF);
  220. /* Setup windows for DDR banks. Count total DDR size on the fly. */
  221. size = 0;
  222. for (i = 0; i < dram->num_cs; i++) {
  223. const struct mbus_dram_window *cs = dram->cs + i;
  224. writel(cs->base & 0xffff0000,
  225. pcie->base + PCIE_WIN04_BASE_OFF(i));
  226. writel(0, pcie->base + PCIE_WIN04_REMAP_OFF(i));
  227. writel(((cs->size - 1) & 0xffff0000) |
  228. (cs->mbus_attr << 8) |
  229. (dram->mbus_dram_target_id << 4) | 1,
  230. pcie->base + PCIE_WIN04_CTRL_OFF(i));
  231. size += cs->size;
  232. }
  233. /* Round up 'size' to the nearest power of two. */
  234. if ((size & (size - 1)) != 0)
  235. size = 1 << fls(size);
  236. /* Setup BAR[1] to all DRAM banks. */
  237. writel(dram->cs[0].base | 0xc, pcie->base + PCIE_BAR_LO_OFF(1));
  238. writel(0, pcie->base + PCIE_BAR_HI_OFF(1));
  239. writel(((size - 1) & 0xffff0000) | 0x1,
  240. pcie->base + PCIE_BAR_CTRL_OFF(1));
  241. }
  242. static int mvebu_pcie_probe(struct udevice *dev)
  243. {
  244. struct mvebu_pcie *pcie = dev_get_platdata(dev);
  245. struct udevice *ctlr = pci_get_controller(dev);
  246. struct pci_controller *hose = dev_get_uclass_priv(ctlr);
  247. static int bus;
  248. u32 reg;
  249. debug("%s: PCIe %d.%d - up, base %08x\n", __func__,
  250. pcie->port, pcie->lane, (u32)pcie->base);
  251. /* Read Id info and local bus/dev */
  252. debug("direct conf read %08x, local bus %d, local dev %d\n",
  253. readl(pcie->base), mvebu_pcie_get_local_bus_nr(pcie),
  254. mvebu_pcie_get_local_dev_nr(pcie));
  255. mvebu_pcie_set_local_bus_nr(pcie, bus);
  256. mvebu_pcie_set_local_dev_nr(pcie, 0);
  257. pcie->dev = PCI_BDF(bus, 0, 0);
  258. pcie->mem.start = (u32)mvebu_pcie_membase;
  259. pcie->mem.end = pcie->mem.start + PCIE_MEM_SIZE - 1;
  260. mvebu_pcie_membase += PCIE_MEM_SIZE;
  261. if (mvebu_mbus_add_window_by_id(pcie->mem_target, pcie->mem_attr,
  262. (phys_addr_t)pcie->mem.start,
  263. PCIE_MEM_SIZE)) {
  264. printf("PCIe unable to add mbus window for mem at %08x+%08x\n",
  265. (u32)pcie->mem.start, PCIE_MEM_SIZE);
  266. }
  267. /* Setup windows and configure host bridge */
  268. mvebu_pcie_setup_wins(pcie);
  269. /* Master + slave enable. */
  270. reg = readl(pcie->base + PCIE_CMD_OFF);
  271. reg |= PCI_COMMAND_MEMORY;
  272. reg |= PCI_COMMAND_MASTER;
  273. reg |= BIT(10); /* disable interrupts */
  274. writel(reg, pcie->base + PCIE_CMD_OFF);
  275. /* PCI memory space */
  276. pci_set_region(hose->regions + 0, pcie->mem.start,
  277. pcie->mem.start, PCIE_MEM_SIZE, PCI_REGION_MEM);
  278. pci_set_region(hose->regions + 1,
  279. 0, 0,
  280. gd->ram_size,
  281. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  282. hose->region_count = 2;
  283. /* Set BAR0 to internal registers */
  284. writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
  285. writel(0, pcie->base + PCIE_BAR_HI_OFF(0));
  286. bus++;
  287. return 0;
  288. }
  289. static int mvebu_pcie_port_parse_dt(ofnode node, struct mvebu_pcie *pcie)
  290. {
  291. const u32 *addr;
  292. int len;
  293. addr = ofnode_get_property(node, "assigned-addresses", &len);
  294. if (!addr) {
  295. pr_err("property \"assigned-addresses\" not found");
  296. return -FDT_ERR_NOTFOUND;
  297. }
  298. pcie->base = (void *)(fdt32_to_cpu(addr[2]) + SOC_REGS_PHY_BASE);
  299. return 0;
  300. }
  301. #define DT_FLAGS_TO_TYPE(flags) (((flags) >> 24) & 0x03)
  302. #define DT_TYPE_IO 0x1
  303. #define DT_TYPE_MEM32 0x2
  304. #define DT_CPUADDR_TO_TARGET(cpuaddr) (((cpuaddr) >> 56) & 0xFF)
  305. #define DT_CPUADDR_TO_ATTR(cpuaddr) (((cpuaddr) >> 48) & 0xFF)
  306. static int mvebu_get_tgt_attr(ofnode node, int devfn,
  307. unsigned long type,
  308. unsigned int *tgt,
  309. unsigned int *attr)
  310. {
  311. const int na = 3, ns = 2;
  312. const __be32 *range;
  313. int rlen, nranges, rangesz, pna, i;
  314. *tgt = -1;
  315. *attr = -1;
  316. range = ofnode_get_property(node, "ranges", &rlen);
  317. if (!range)
  318. return -EINVAL;
  319. /*
  320. * Linux uses of_n_addr_cells() to get the number of address cells
  321. * here. Currently this function is only available in U-Boot when
  322. * CONFIG_OF_LIVE is enabled. Until this is enabled for MVEBU in
  323. * general, lets't hardcode the "pna" value in the U-Boot code.
  324. */
  325. pna = 2; /* hardcoded for now because of lack of of_n_addr_cells() */
  326. rangesz = pna + na + ns;
  327. nranges = rlen / sizeof(__be32) / rangesz;
  328. for (i = 0; i < nranges; i++, range += rangesz) {
  329. u32 flags = of_read_number(range, 1);
  330. u32 slot = of_read_number(range + 1, 1);
  331. u64 cpuaddr = of_read_number(range + na, pna);
  332. unsigned long rtype;
  333. if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_IO)
  334. rtype = IORESOURCE_IO;
  335. else if (DT_FLAGS_TO_TYPE(flags) == DT_TYPE_MEM32)
  336. rtype = IORESOURCE_MEM;
  337. else
  338. continue;
  339. /*
  340. * The Linux code used PCI_SLOT() here, which expects devfn
  341. * in bits 7..0. PCI_DEV() in U-Boot is similar to PCI_SLOT(),
  342. * only expects devfn in 15..8, where its saved in this driver.
  343. */
  344. if (slot == PCI_DEV(devfn) && type == rtype) {
  345. *tgt = DT_CPUADDR_TO_TARGET(cpuaddr);
  346. *attr = DT_CPUADDR_TO_ATTR(cpuaddr);
  347. return 0;
  348. }
  349. }
  350. return -ENOENT;
  351. }
  352. static int mvebu_pcie_ofdata_to_platdata(struct udevice *dev)
  353. {
  354. struct mvebu_pcie *pcie = dev_get_platdata(dev);
  355. int ret = 0;
  356. /* Get port number, lane number and memory target / attr */
  357. if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-port",
  358. &pcie->port)) {
  359. ret = -ENODEV;
  360. goto err;
  361. }
  362. if (ofnode_read_u32(dev_ofnode(dev), "marvell,pcie-lane", &pcie->lane))
  363. pcie->lane = 0;
  364. sprintf(pcie->name, "pcie%d.%d", pcie->port, pcie->lane);
  365. /* pci_get_devfn() returns devfn in bits 15..8, see PCI_DEV usage */
  366. pcie->devfn = pci_get_devfn(dev);
  367. if (pcie->devfn < 0) {
  368. ret = -ENODEV;
  369. goto err;
  370. }
  371. ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
  372. IORESOURCE_MEM,
  373. &pcie->mem_target, &pcie->mem_attr);
  374. if (ret < 0) {
  375. printf("%s: cannot get tgt/attr for mem window\n", pcie->name);
  376. goto err;
  377. }
  378. /* Parse PCIe controller register base from DT */
  379. ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie);
  380. if (ret < 0)
  381. goto err;
  382. /* Check link and skip ports that have no link */
  383. if (!mvebu_pcie_link_up(pcie)) {
  384. debug("%s: %s - down\n", __func__, pcie->name);
  385. ret = -ENODEV;
  386. goto err;
  387. }
  388. return 0;
  389. err:
  390. return ret;
  391. }
  392. static const struct dm_pci_ops mvebu_pcie_ops = {
  393. .read_config = mvebu_pcie_read_config,
  394. .write_config = mvebu_pcie_write_config,
  395. };
  396. static struct driver pcie_mvebu_drv = {
  397. .name = "pcie_mvebu",
  398. .id = UCLASS_PCI,
  399. .ops = &mvebu_pcie_ops,
  400. .probe = mvebu_pcie_probe,
  401. .ofdata_to_platdata = mvebu_pcie_ofdata_to_platdata,
  402. .platdata_auto_alloc_size = sizeof(struct mvebu_pcie),
  403. };
  404. /*
  405. * Use a MISC device to bind the n instances (child nodes) of the
  406. * PCIe base controller in UCLASS_PCI.
  407. */
  408. static int mvebu_pcie_bind(struct udevice *parent)
  409. {
  410. struct mvebu_pcie *pcie;
  411. struct uclass_driver *drv;
  412. struct udevice *dev;
  413. ofnode subnode;
  414. /* Lookup eth driver */
  415. drv = lists_uclass_lookup(UCLASS_PCI);
  416. if (!drv) {
  417. puts("Cannot find PCI driver\n");
  418. return -ENOENT;
  419. }
  420. ofnode_for_each_subnode(subnode, dev_ofnode(parent)) {
  421. if (!ofnode_is_available(subnode))
  422. continue;
  423. pcie = calloc(1, sizeof(*pcie));
  424. if (!pcie)
  425. return -ENOMEM;
  426. /* Create child device UCLASS_PCI and bind it */
  427. device_bind_ofnode(parent, &pcie_mvebu_drv, pcie->name, pcie,
  428. subnode, &dev);
  429. }
  430. return 0;
  431. }
  432. static const struct udevice_id mvebu_pcie_ids[] = {
  433. { .compatible = "marvell,armada-xp-pcie" },
  434. { .compatible = "marvell,armada-370-pcie" },
  435. { }
  436. };
  437. U_BOOT_DRIVER(pcie_mvebu_base) = {
  438. .name = "pcie_mvebu_base",
  439. .id = UCLASS_MISC,
  440. .of_match = mvebu_pcie_ids,
  441. .bind = mvebu_pcie_bind,
  442. };