pci_ftpci100.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Faraday FTPCI100 PCI Bridge Controller Device Driver Implementation
  4. *
  5. * Copyright (C) 2011 Andes Technology Corporation
  6. * Gavin Guo, Andes Technology Corporation <gavinguo@andestech.com>
  7. * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
  8. */
  9. #include <common.h>
  10. #include <init.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <pci.h>
  14. #include <faraday/ftpci100.h>
  15. #include <asm/io.h>
  16. #include <asm/types.h> /* u32, u16.... used by pci.h */
  17. struct ftpci100_data {
  18. unsigned int reg_base;
  19. unsigned int io_base;
  20. unsigned int mem_base;
  21. unsigned int mmio_base;
  22. unsigned int ndevs;
  23. };
  24. static struct pci_config devs[FTPCI100_MAX_FUNCTIONS];
  25. static struct pci_controller local_hose;
  26. static void setup_pci_bar(unsigned int bus, unsigned int dev, unsigned func,
  27. unsigned char header, struct ftpci100_data *priv)
  28. {
  29. struct pci_controller *hose = (struct pci_controller *)&local_hose;
  30. unsigned int i, tmp32, bar_no, iovsmem = 1;
  31. pci_dev_t dev_nu;
  32. /* A device is present, add an entry to the array */
  33. devs[priv->ndevs].bus = bus;
  34. devs[priv->ndevs].dev = dev;
  35. devs[priv->ndevs].func = func;
  36. dev_nu = PCI_BDF(bus, dev, func);
  37. if ((header & 0x7f) == 0x01)
  38. /* PCI-PCI Bridge */
  39. bar_no = 2;
  40. else
  41. bar_no = 6;
  42. /* Allocate address spaces by configuring BARs */
  43. for (i = 0; i < bar_no; i++) {
  44. pci_hose_write_config_dword(hose, dev_nu,
  45. PCI_BASE_ADDRESS_0 + i * 4, 0xffffffff);
  46. pci_hose_read_config_dword(hose, dev_nu,
  47. PCI_BASE_ADDRESS_0 + i * 4, &tmp32);
  48. if (tmp32 == 0x0)
  49. continue;
  50. /* IO space */
  51. if (tmp32 & 0x1) {
  52. iovsmem = 0;
  53. unsigned int size_mask = ~(tmp32 & 0xfffffffc);
  54. if (priv->io_base & size_mask)
  55. priv->io_base = (priv->io_base & ~size_mask) + \
  56. size_mask + 1;
  57. devs[priv->ndevs].bar[i].addr = priv->io_base;
  58. devs[priv->ndevs].bar[i].size = size_mask + 1;
  59. pci_hose_write_config_dword(hose, dev_nu,
  60. PCI_BASE_ADDRESS_0 + i * 4,
  61. priv->io_base);
  62. debug("Allocated IO address 0x%X-" \
  63. "0x%X for Bus %d, Device %d, Function %d\n",
  64. priv->io_base,
  65. priv->io_base + size_mask, bus, dev, func);
  66. priv->io_base += size_mask + 1;
  67. } else {
  68. /* Memory space */
  69. unsigned int is_64bit = ((tmp32 & 0x6) == 0x4);
  70. unsigned int is_pref = tmp32 & 0x8;
  71. unsigned int size_mask = ~(tmp32 & 0xfffffff0);
  72. unsigned int alloc_base;
  73. unsigned int *addr_mem_base;
  74. if (is_pref)
  75. addr_mem_base = &priv->mem_base;
  76. else
  77. addr_mem_base = &priv->mmio_base;
  78. alloc_base = *addr_mem_base;
  79. if (alloc_base & size_mask)
  80. alloc_base = (alloc_base & ~size_mask) \
  81. + size_mask + 1;
  82. pci_hose_write_config_dword(hose, dev_nu,
  83. PCI_BASE_ADDRESS_0 + i * 4, alloc_base);
  84. debug("Allocated %s address 0x%X-" \
  85. "0x%X for Bus %d, Device %d, Function %d\n",
  86. is_pref ? "MEM" : "MMIO", alloc_base,
  87. alloc_base + size_mask, bus, dev, func);
  88. devs[priv->ndevs].bar[i].addr = alloc_base;
  89. devs[priv->ndevs].bar[i].size = size_mask + 1;
  90. debug("BAR address BAR size\n");
  91. debug("%010x %08d\n",
  92. devs[priv->ndevs].bar[0].addr,
  93. devs[priv->ndevs].bar[0].size);
  94. alloc_base += size_mask + 1;
  95. *addr_mem_base = alloc_base;
  96. if (is_64bit) {
  97. i++;
  98. pci_hose_write_config_dword(hose, dev_nu,
  99. PCI_BASE_ADDRESS_0 + i * 4, 0x0);
  100. }
  101. }
  102. }
  103. /* Enable Bus Master, Memory Space, and IO Space */
  104. pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
  105. pci_hose_write_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, 0x08);
  106. pci_hose_read_config_dword(hose, dev_nu, PCI_CACHE_LINE_SIZE, &tmp32);
  107. pci_hose_read_config_dword(hose, dev_nu, PCI_COMMAND, &tmp32);
  108. tmp32 &= 0xffff;
  109. if (iovsmem == 0)
  110. tmp32 |= 0x5;
  111. else
  112. tmp32 |= 0x6;
  113. pci_hose_write_config_dword(hose, dev_nu, PCI_COMMAND, tmp32);
  114. }
  115. static void pci_bus_scan(struct ftpci100_data *priv)
  116. {
  117. struct pci_controller *hose = (struct pci_controller *)&local_hose;
  118. unsigned int bus, dev, func;
  119. pci_dev_t dev_nu;
  120. unsigned int data32;
  121. unsigned int tmp;
  122. unsigned char header;
  123. unsigned char int_pin;
  124. unsigned int niobars;
  125. unsigned int nmbars;
  126. priv->ndevs = 1;
  127. nmbars = 0;
  128. niobars = 0;
  129. for (bus = 0; bus < MAX_BUS_NUM; bus++)
  130. for (dev = 0; dev < MAX_DEV_NUM; dev++)
  131. for (func = 0; func < MAX_FUN_NUM; func++) {
  132. dev_nu = PCI_BDF(bus, dev, func);
  133. pci_hose_read_config_dword(hose, dev_nu,
  134. PCI_VENDOR_ID, &data32);
  135. /*
  136. * some broken boards return 0 or ~0,
  137. * if a slot is empty.
  138. */
  139. if (data32 == 0xffffffff ||
  140. data32 == 0x00000000 ||
  141. data32 == 0x0000ffff ||
  142. data32 == 0xffff0000)
  143. continue;
  144. pci_hose_read_config_dword(hose, dev_nu,
  145. PCI_HEADER_TYPE, &tmp);
  146. header = (unsigned char)tmp;
  147. setup_pci_bar(bus, dev, func, header, priv);
  148. devs[priv->ndevs].v_id = (u16)(data32 & \
  149. 0x0000ffff);
  150. devs[priv->ndevs].d_id = (u16)((data32 & \
  151. 0xffff0000) >> 16);
  152. /* Figure out what INTX# line the card uses */
  153. pci_hose_read_config_byte(hose, dev_nu,
  154. PCI_INTERRUPT_PIN, &int_pin);
  155. /* assign the appropriate irq line */
  156. if (int_pin > PCI_IRQ_LINES) {
  157. printf("more irq lines than expect\n");
  158. } else if (int_pin != 0) {
  159. /* This device uses an interrupt line */
  160. devs[priv->ndevs].pin = int_pin;
  161. }
  162. pci_hose_read_config_dword(hose, dev_nu,
  163. PCI_CLASS_DEVICE, &data32);
  164. debug("%06d %03d %03d " \
  165. "%04d %08x %08x " \
  166. "%03d %08x %06d %08x\n",
  167. priv->ndevs, devs[priv->ndevs].bus,
  168. devs[priv->ndevs].dev,
  169. devs[priv->ndevs].func,
  170. devs[priv->ndevs].d_id,
  171. devs[priv->ndevs].v_id,
  172. devs[priv->ndevs].pin,
  173. devs[priv->ndevs].bar[0].addr,
  174. devs[priv->ndevs].bar[0].size,
  175. data32 >> 8);
  176. priv->ndevs++;
  177. }
  178. }
  179. static void ftpci_preinit(struct ftpci100_data *priv)
  180. {
  181. struct ftpci100_ahbc *ftpci100;
  182. struct pci_controller *hose = (struct pci_controller *)&local_hose;
  183. u32 pci_config_addr;
  184. u32 pci_config_data;
  185. priv->reg_base = CONFIG_FTPCI100_BASE;
  186. priv->io_base = CONFIG_FTPCI100_BASE + CONFIG_FTPCI100_IO_SIZE;
  187. priv->mmio_base = CONFIG_FTPCI100_MEM_BASE;
  188. priv->mem_base = CONFIG_FTPCI100_MEM_BASE + CONFIG_FTPCI100_MEM_SIZE;
  189. ftpci100 = (struct ftpci100_ahbc *)priv->reg_base;
  190. pci_config_addr = (u32) &ftpci100->conf;
  191. pci_config_data = (u32) &ftpci100->data;
  192. /* print device name */
  193. printf("FTPCI100\n");
  194. /* dump basic configuration */
  195. debug("%s: Config addr is %08X, data port is %08X\n",
  196. __func__, pci_config_addr, pci_config_data);
  197. /* PCI memory space */
  198. pci_set_region(hose->regions + 0,
  199. CONFIG_PCI_MEM_BUS,
  200. CONFIG_PCI_MEM_PHYS,
  201. CONFIG_PCI_MEM_SIZE,
  202. PCI_REGION_MEM);
  203. hose->region_count++;
  204. /* PCI IO space */
  205. pci_set_region(hose->regions + 1,
  206. CONFIG_PCI_IO_BUS,
  207. CONFIG_PCI_IO_PHYS,
  208. CONFIG_PCI_IO_SIZE,
  209. PCI_REGION_IO);
  210. hose->region_count++;
  211. #if defined(CONFIG_PCI_SYS_BUS)
  212. /* PCI System Memory space */
  213. pci_set_region(hose->regions + 2,
  214. CONFIG_PCI_SYS_BUS,
  215. CONFIG_PCI_SYS_PHYS,
  216. CONFIG_PCI_SYS_SIZE,
  217. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  218. hose->region_count++;
  219. #endif
  220. /* setup indirect read/write function */
  221. pci_setup_indirect(hose, pci_config_addr, pci_config_data);
  222. /* register hose */
  223. pci_register_hose(hose);
  224. }
  225. void pci_ftpci_init(void)
  226. {
  227. struct ftpci100_data *priv = NULL;
  228. struct pci_controller *hose = (struct pci_controller *)&local_hose;
  229. pci_dev_t bridge_num;
  230. struct pci_device_id bridge_ids[] = {
  231. {FTPCI100_BRIDGE_VENDORID, FTPCI100_BRIDGE_DEVICEID},
  232. {0, 0}
  233. };
  234. priv = malloc(sizeof(struct ftpci100_data));
  235. if (!priv) {
  236. printf("%s(): failed to malloc priv\n", __func__);
  237. return;
  238. }
  239. memset(priv, 0, sizeof(struct ftpci100_data));
  240. ftpci_preinit(priv);
  241. debug("Device bus dev func deviceID vendorID pin address" \
  242. " size class\n");
  243. pci_bus_scan(priv);
  244. /*
  245. * Setup the PCI Bridge Window to 1GB,
  246. * it will cause USB OHCI Host controller Unrecoverable Error
  247. * if it is not set.
  248. */
  249. bridge_num = pci_find_devices(bridge_ids, 0);
  250. if (bridge_num == -1) {
  251. printf("PCI Bridge not found\n");
  252. return;
  253. }
  254. pci_hose_write_config_dword(hose, bridge_num, PCI_MEM_BASE_SIZE1,
  255. FTPCI100_BASE_ADR_SIZE(1024));
  256. }