pci-rcar-gen3.c 10 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Renesas RCar Gen3 PCIEC driver
  4. *
  5. * Copyright (C) 2018-2019 Marek Vasut <marek.vasut@gmail.com>
  6. *
  7. * Based on Linux PCIe driver for Renesas R-Car SoCs
  8. * Copyright (C) 2014 Renesas Electronics Europe Ltd
  9. *
  10. * Based on:
  11. * arch/sh/drivers/pci/pcie-sh7786.c
  12. * arch/sh/drivers/pci/ops-sh7786.c
  13. * Copyright (C) 2009 - 2011 Paul Mundt
  14. *
  15. * Author: Phil Edworthy <phil.edworthy@renesas.com>
  16. */
  17. #include <common.h>
  18. #include <asm/io.h>
  19. #include <clk.h>
  20. #include <dm.h>
  21. #include <errno.h>
  22. #include <pci.h>
  23. #include <wait_bit.h>
  24. #include <linux/bitops.h>
  25. #define PCIECAR 0x000010
  26. #define PCIECCTLR 0x000018
  27. #define CONFIG_SEND_ENABLE BIT(31)
  28. #define TYPE0 (0 << 8)
  29. #define TYPE1 BIT(8)
  30. #define PCIECDR 0x000020
  31. #define PCIEMSR 0x000028
  32. #define PCIEINTXR 0x000400
  33. #define PCIEPHYSR 0x0007f0
  34. #define PHYRDY BIT(0)
  35. #define PCIEMSITXR 0x000840
  36. /* Transfer control */
  37. #define PCIETCTLR 0x02000
  38. #define CFINIT 1
  39. #define PCIETSTR 0x02004
  40. #define DATA_LINK_ACTIVE 1
  41. #define PCIEERRFR 0x02020
  42. #define UNSUPPORTED_REQUEST BIT(4)
  43. #define PCIEMSIFR 0x02044
  44. #define PCIEMSIALR 0x02048
  45. #define MSIFE 1
  46. #define PCIEMSIAUR 0x0204c
  47. #define PCIEMSIIER 0x02050
  48. /* root port address */
  49. #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
  50. /* local address reg & mask */
  51. #define PCIELAR(x) (0x02200 + ((x) * 0x20))
  52. #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
  53. #define LAM_PREFETCH BIT(3)
  54. #define LAM_64BIT BIT(2)
  55. #define LAR_ENABLE BIT(1)
  56. /* PCIe address reg & mask */
  57. #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
  58. #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
  59. #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
  60. #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
  61. #define PAR_ENABLE BIT(31)
  62. #define IO_SPACE BIT(8)
  63. /* Configuration */
  64. #define PCICONF(x) (0x010000 + ((x) * 0x4))
  65. #define PMCAP(x) (0x010040 + ((x) * 0x4))
  66. #define EXPCAP(x) (0x010070 + ((x) * 0x4))
  67. #define VCCAP(x) (0x010100 + ((x) * 0x4))
  68. /* link layer */
  69. #define IDSETR1 0x011004
  70. #define TLCTLR 0x011048
  71. #define MACSR 0x011054
  72. #define SPCHGFIN BIT(4)
  73. #define SPCHGFAIL BIT(6)
  74. #define SPCHGSUC BIT(7)
  75. #define LINK_SPEED (0xf << 16)
  76. #define LINK_SPEED_2_5GTS (1 << 16)
  77. #define LINK_SPEED_5_0GTS (2 << 16)
  78. #define MACCTLR 0x011058
  79. #define SPEED_CHANGE BIT(24)
  80. #define SCRAMBLE_DISABLE BIT(27)
  81. #define MACS2R 0x011078
  82. #define MACCGSPSETR 0x011084
  83. #define SPCNGRSN BIT(31)
  84. /* R-Car H1 PHY */
  85. #define H1_PCIEPHYADRR 0x04000c
  86. #define WRITE_CMD BIT(16)
  87. #define PHY_ACK BIT(24)
  88. #define RATE_POS 12
  89. #define LANE_POS 8
  90. #define ADR_POS 0
  91. #define H1_PCIEPHYDOUTR 0x040014
  92. /* R-Car Gen2 PHY */
  93. #define GEN2_PCIEPHYADDR 0x780
  94. #define GEN2_PCIEPHYDATA 0x784
  95. #define GEN2_PCIEPHYCTRL 0x78c
  96. #define INT_PCI_MSI_NR 32
  97. #define RCONF(x) (PCICONF(0) + (x))
  98. #define RPMCAP(x) (PMCAP(0) + (x))
  99. #define REXPCAP(x) (EXPCAP(0) + (x))
  100. #define RVCCAP(x) (VCCAP(0) + (x))
  101. #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
  102. #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
  103. #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
  104. #define RCAR_PCI_MAX_RESOURCES 4
  105. #define MAX_NR_INBOUND_MAPS 6
  106. enum {
  107. RCAR_PCI_ACCESS_READ,
  108. RCAR_PCI_ACCESS_WRITE,
  109. };
  110. struct rcar_gen3_pcie_priv {
  111. fdt_addr_t regs;
  112. };
  113. static void rcar_rmw32(struct udevice *dev, int where, u32 mask, u32 data)
  114. {
  115. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  116. int shift = 8 * (where & 3);
  117. clrsetbits_le32(priv->regs + (where & ~3),
  118. mask << shift, data << shift);
  119. }
  120. static u32 rcar_read_conf(const struct udevice *dev, int where)
  121. {
  122. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  123. int shift = 8 * (where & 3);
  124. return readl(priv->regs + (where & ~3)) >> shift;
  125. }
  126. static int rcar_pcie_config_access(const struct udevice *udev,
  127. unsigned char access_type,
  128. pci_dev_t bdf, int where, ulong *data)
  129. {
  130. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(udev);
  131. u32 reg = where & ~3;
  132. /* Clear errors */
  133. clrbits_le32(priv->regs + PCIEERRFR, 0);
  134. /* Set the PIO address */
  135. writel((bdf << 8) | reg, priv->regs + PCIECAR);
  136. /* Enable the configuration access */
  137. if (!PCI_BUS(bdf))
  138. writel(CONFIG_SEND_ENABLE | TYPE0, priv->regs + PCIECCTLR);
  139. else
  140. writel(CONFIG_SEND_ENABLE | TYPE1, priv->regs + PCIECCTLR);
  141. /* Check for errors */
  142. if (readl(priv->regs + PCIEERRFR) & UNSUPPORTED_REQUEST)
  143. return -ENODEV;
  144. /* Check for master and target aborts */
  145. if (rcar_read_conf(udev, RCONF(PCI_STATUS)) &
  146. (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
  147. return -ENODEV;
  148. if (access_type == RCAR_PCI_ACCESS_READ)
  149. *data = readl(priv->regs + PCIECDR);
  150. else
  151. writel(*data, priv->regs + PCIECDR);
  152. /* Disable the configuration access */
  153. writel(0, priv->regs + PCIECCTLR);
  154. return 0;
  155. }
  156. static int rcar_gen3_pcie_addr_valid(pci_dev_t d, uint where)
  157. {
  158. u32 slot;
  159. if (PCI_FUNC(d))
  160. return -EINVAL;
  161. slot = PCI_DEV(d);
  162. if (slot != 1)
  163. return -EINVAL;
  164. return 0;
  165. }
  166. static int rcar_gen3_pcie_read_config(const struct udevice *dev, pci_dev_t bdf,
  167. uint where, ulong *val,
  168. enum pci_size_t size)
  169. {
  170. ulong reg;
  171. int ret;
  172. ret = rcar_gen3_pcie_addr_valid(bdf, where);
  173. if (ret) {
  174. *val = pci_get_ff(size);
  175. return 0;
  176. }
  177. ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_READ,
  178. bdf, where, &reg);
  179. if (ret != 0)
  180. reg = 0xffffffffUL;
  181. *val = pci_conv_32_to_size(reg, where, size);
  182. return ret;
  183. }
  184. static int rcar_gen3_pcie_write_config(struct udevice *dev, pci_dev_t bdf,
  185. uint where, ulong val,
  186. enum pci_size_t size)
  187. {
  188. ulong data;
  189. int ret;
  190. ret = rcar_gen3_pcie_addr_valid(bdf, where);
  191. if (ret)
  192. return ret;
  193. data = pci_conv_32_to_size(val, where, size);
  194. ret = rcar_pcie_config_access(dev, RCAR_PCI_ACCESS_WRITE,
  195. bdf, where, &data);
  196. return ret;
  197. }
  198. static int rcar_gen3_pcie_wait_for_phyrdy(struct udevice *dev)
  199. {
  200. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  201. return wait_for_bit_le32((void *)priv->regs + PCIEPHYSR, PHYRDY,
  202. true, 50, false);
  203. }
  204. static int rcar_gen3_pcie_wait_for_dl(struct udevice *dev)
  205. {
  206. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  207. return wait_for_bit_le32((void *)priv->regs + PCIETSTR,
  208. DATA_LINK_ACTIVE, true, 50, false);
  209. }
  210. static int rcar_gen3_pcie_hw_init(struct udevice *dev)
  211. {
  212. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  213. int ret;
  214. /* Begin initialization */
  215. writel(0, priv->regs + PCIETCTLR);
  216. /* Set mode */
  217. writel(1, priv->regs + PCIEMSR);
  218. ret = rcar_gen3_pcie_wait_for_phyrdy(dev);
  219. if (ret)
  220. return ret;
  221. /*
  222. * Initial header for port config space is type 1, set the device
  223. * class to match. Hardware takes care of propagating the IDSETR
  224. * settings, so there is no need to bother with a quirk.
  225. */
  226. writel(PCI_CLASS_BRIDGE_PCI << 16, priv->regs + IDSETR1);
  227. /*
  228. * Setup Secondary Bus Number & Subordinate Bus Number, even though
  229. * they aren't used, to avoid bridge being detected as broken.
  230. */
  231. rcar_rmw32(dev, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
  232. rcar_rmw32(dev, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
  233. /* Initialize default capabilities. */
  234. rcar_rmw32(dev, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
  235. rcar_rmw32(dev, REXPCAP(PCI_EXP_FLAGS),
  236. PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
  237. rcar_rmw32(dev, RCONF(PCI_HEADER_TYPE), 0x7f,
  238. PCI_HEADER_TYPE_BRIDGE);
  239. /* Enable data link layer active state reporting */
  240. rcar_rmw32(dev, REXPCAP(PCI_EXP_LNKCAP),
  241. PCI_EXP_LNKCAP_DLLLARC, PCI_EXP_LNKCAP_DLLLARC);
  242. /* Write out the physical slot number = 0 */
  243. rcar_rmw32(dev, REXPCAP(PCI_EXP_SLTCAP),
  244. PCI_EXP_SLTCAP_PSN, 0);
  245. /* Set the completion timer timeout to the maximum 50ms. */
  246. rcar_rmw32(dev, TLCTLR + 1, 0x3f, 50);
  247. /* Terminate list of capabilities (Next Capability Offset=0) */
  248. rcar_rmw32(dev, RVCCAP(0), 0xfff00000, 0);
  249. /* Finish initialization - establish a PCI Express link */
  250. writel(CFINIT, priv->regs + PCIETCTLR);
  251. return rcar_gen3_pcie_wait_for_dl(dev);
  252. }
  253. static int rcar_gen3_pcie_probe(struct udevice *dev)
  254. {
  255. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  256. struct pci_controller *hose = dev_get_uclass_priv(dev);
  257. struct clk pci_clk;
  258. u32 mask;
  259. int i, cnt, ret;
  260. ret = clk_get_by_index(dev, 0, &pci_clk);
  261. if (ret)
  262. return ret;
  263. ret = clk_enable(&pci_clk);
  264. if (ret)
  265. return ret;
  266. for (i = 0; i < hose->region_count; i++) {
  267. if (hose->regions[i].flags != PCI_REGION_SYS_MEMORY)
  268. continue;
  269. if (hose->regions[i].phys_start == 0)
  270. continue;
  271. mask = (hose->regions[i].size - 1) & ~0xf;
  272. mask |= LAR_ENABLE;
  273. writel(hose->regions[i].phys_start, priv->regs + PCIEPRAR(0));
  274. writel(hose->regions[i].phys_start, priv->regs + PCIELAR(0));
  275. writel(mask, priv->regs + PCIELAMR(0));
  276. break;
  277. }
  278. writel(0, priv->regs + PCIEPRAR(4));
  279. writel(0, priv->regs + PCIELAR(4));
  280. writel(0, priv->regs + PCIELAMR(4));
  281. ret = rcar_gen3_pcie_hw_init(dev);
  282. if (ret)
  283. return ret;
  284. for (i = 0, cnt = 0; i < hose->region_count; i++) {
  285. if (hose->regions[i].flags == PCI_REGION_SYS_MEMORY)
  286. continue;
  287. writel(0, priv->regs + PCIEPTCTLR(cnt));
  288. writel((hose->regions[i].size - 1) & ~0x7f,
  289. priv->regs + PCIEPAMR(cnt));
  290. writel(upper_32_bits(hose->regions[i].phys_start),
  291. priv->regs + PCIEPAUR(cnt));
  292. writel(lower_32_bits(hose->regions[i].phys_start),
  293. priv->regs + PCIEPALR(cnt));
  294. mask = PAR_ENABLE;
  295. if (hose->regions[i].flags == PCI_REGION_IO)
  296. mask |= IO_SPACE;
  297. writel(mask, priv->regs + PCIEPTCTLR(cnt));
  298. cnt++;
  299. }
  300. return 0;
  301. }
  302. static int rcar_gen3_pcie_ofdata_to_platdata(struct udevice *dev)
  303. {
  304. struct rcar_gen3_pcie_priv *priv = dev_get_platdata(dev);
  305. priv->regs = devfdt_get_addr_index(dev, 0);
  306. if (!priv->regs)
  307. return -EINVAL;
  308. return 0;
  309. }
  310. static const struct dm_pci_ops rcar_gen3_pcie_ops = {
  311. .read_config = rcar_gen3_pcie_read_config,
  312. .write_config = rcar_gen3_pcie_write_config,
  313. };
  314. static const struct udevice_id rcar_gen3_pcie_ids[] = {
  315. { .compatible = "renesas,pcie-rcar-gen3" },
  316. { }
  317. };
  318. U_BOOT_DRIVER(rcar_gen3_pcie) = {
  319. .name = "rcar_gen3_pcie",
  320. .id = UCLASS_PCI,
  321. .of_match = rcar_gen3_pcie_ids,
  322. .ops = &rcar_gen3_pcie_ops,
  323. .probe = rcar_gen3_pcie_probe,
  324. .ofdata_to_platdata = rcar_gen3_pcie_ofdata_to_platdata,
  325. .platdata_auto_alloc_size = sizeof(struct rcar_gen3_pcie_priv),
  326. };