ravb.c 17 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * drivers/net/ravb.c
  4. * This file is driver for Renesas Ethernet AVB.
  5. *
  6. * Copyright (C) 2015-2017 Renesas Electronics Corporation
  7. *
  8. * Based on the SuperH Ethernet driver.
  9. */
  10. #include <common.h>
  11. #include <clk.h>
  12. #include <cpu_func.h>
  13. #include <dm.h>
  14. #include <errno.h>
  15. #include <log.h>
  16. #include <miiphy.h>
  17. #include <malloc.h>
  18. #include <asm/cache.h>
  19. #include <linux/bitops.h>
  20. #include <linux/delay.h>
  21. #include <linux/mii.h>
  22. #include <wait_bit.h>
  23. #include <asm/io.h>
  24. #include <asm/gpio.h>
  25. /* Registers */
  26. #define RAVB_REG_CCC 0x000
  27. #define RAVB_REG_DBAT 0x004
  28. #define RAVB_REG_CSR 0x00C
  29. #define RAVB_REG_APSR 0x08C
  30. #define RAVB_REG_RCR 0x090
  31. #define RAVB_REG_TGC 0x300
  32. #define RAVB_REG_TCCR 0x304
  33. #define RAVB_REG_RIC0 0x360
  34. #define RAVB_REG_RIC1 0x368
  35. #define RAVB_REG_RIC2 0x370
  36. #define RAVB_REG_TIC 0x378
  37. #define RAVB_REG_ECMR 0x500
  38. #define RAVB_REG_RFLR 0x508
  39. #define RAVB_REG_ECSIPR 0x518
  40. #define RAVB_REG_PIR 0x520
  41. #define RAVB_REG_GECMR 0x5b0
  42. #define RAVB_REG_MAHR 0x5c0
  43. #define RAVB_REG_MALR 0x5c8
  44. #define CCC_OPC_CONFIG BIT(0)
  45. #define CCC_OPC_OPERATION BIT(1)
  46. #define CCC_BOC BIT(20)
  47. #define CSR_OPS 0x0000000F
  48. #define CSR_OPS_CONFIG BIT(1)
  49. #define APSR_TDM BIT(14)
  50. #define TCCR_TSRQ0 BIT(0)
  51. #define RFLR_RFL_MIN 0x05EE
  52. #define PIR_MDI BIT(3)
  53. #define PIR_MDO BIT(2)
  54. #define PIR_MMD BIT(1)
  55. #define PIR_MDC BIT(0)
  56. #define ECMR_TRCCM BIT(26)
  57. #define ECMR_RZPF BIT(20)
  58. #define ECMR_PFR BIT(18)
  59. #define ECMR_RXF BIT(17)
  60. #define ECMR_RE BIT(6)
  61. #define ECMR_TE BIT(5)
  62. #define ECMR_DM BIT(1)
  63. #define ECMR_CHG_DM (ECMR_TRCCM | ECMR_RZPF | ECMR_PFR | ECMR_RXF)
  64. /* DMA Descriptors */
  65. #define RAVB_NUM_BASE_DESC 16
  66. #define RAVB_NUM_TX_DESC 8
  67. #define RAVB_NUM_RX_DESC 8
  68. #define RAVB_TX_QUEUE_OFFSET 0
  69. #define RAVB_RX_QUEUE_OFFSET 4
  70. #define RAVB_DESC_DT(n) ((n) << 28)
  71. #define RAVB_DESC_DT_FSINGLE RAVB_DESC_DT(0x7)
  72. #define RAVB_DESC_DT_LINKFIX RAVB_DESC_DT(0x9)
  73. #define RAVB_DESC_DT_EOS RAVB_DESC_DT(0xa)
  74. #define RAVB_DESC_DT_FEMPTY RAVB_DESC_DT(0xc)
  75. #define RAVB_DESC_DT_EEMPTY RAVB_DESC_DT(0x3)
  76. #define RAVB_DESC_DT_MASK RAVB_DESC_DT(0xf)
  77. #define RAVB_DESC_DS(n) (((n) & 0xfff) << 0)
  78. #define RAVB_DESC_DS_MASK 0xfff
  79. #define RAVB_RX_DESC_MSC_MC BIT(23)
  80. #define RAVB_RX_DESC_MSC_CEEF BIT(22)
  81. #define RAVB_RX_DESC_MSC_CRL BIT(21)
  82. #define RAVB_RX_DESC_MSC_FRE BIT(20)
  83. #define RAVB_RX_DESC_MSC_RTLF BIT(19)
  84. #define RAVB_RX_DESC_MSC_RTSF BIT(18)
  85. #define RAVB_RX_DESC_MSC_RFE BIT(17)
  86. #define RAVB_RX_DESC_MSC_CRC BIT(16)
  87. #define RAVB_RX_DESC_MSC_MASK (0xff << 16)
  88. #define RAVB_RX_DESC_MSC_RX_ERR_MASK \
  89. (RAVB_RX_DESC_MSC_CRC | RAVB_RX_DESC_MSC_RFE | RAVB_RX_DESC_MSC_RTLF | \
  90. RAVB_RX_DESC_MSC_RTSF | RAVB_RX_DESC_MSC_CEEF)
  91. #define RAVB_TX_TIMEOUT_MS 1000
  92. struct ravb_desc {
  93. u32 ctrl;
  94. u32 dptr;
  95. };
  96. struct ravb_rxdesc {
  97. struct ravb_desc data;
  98. struct ravb_desc link;
  99. u8 __pad[48];
  100. u8 packet[PKTSIZE_ALIGN];
  101. };
  102. struct ravb_priv {
  103. struct ravb_desc base_desc[RAVB_NUM_BASE_DESC];
  104. struct ravb_desc tx_desc[RAVB_NUM_TX_DESC];
  105. struct ravb_rxdesc rx_desc[RAVB_NUM_RX_DESC];
  106. u32 rx_desc_idx;
  107. u32 tx_desc_idx;
  108. struct phy_device *phydev;
  109. struct mii_dev *bus;
  110. void __iomem *iobase;
  111. struct clk clk;
  112. struct gpio_desc reset_gpio;
  113. };
  114. static inline void ravb_flush_dcache(u32 addr, u32 len)
  115. {
  116. flush_dcache_range(addr, addr + len);
  117. }
  118. static inline void ravb_invalidate_dcache(u32 addr, u32 len)
  119. {
  120. u32 start = addr & ~((uintptr_t)ARCH_DMA_MINALIGN - 1);
  121. u32 end = roundup(addr + len, ARCH_DMA_MINALIGN);
  122. invalidate_dcache_range(start, end);
  123. }
  124. static int ravb_send(struct udevice *dev, void *packet, int len)
  125. {
  126. struct ravb_priv *eth = dev_get_priv(dev);
  127. struct ravb_desc *desc = &eth->tx_desc[eth->tx_desc_idx];
  128. unsigned int start;
  129. /* Update TX descriptor */
  130. ravb_flush_dcache((uintptr_t)packet, len);
  131. memset(desc, 0x0, sizeof(*desc));
  132. desc->ctrl = RAVB_DESC_DT_FSINGLE | RAVB_DESC_DS(len);
  133. desc->dptr = (uintptr_t)packet;
  134. ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
  135. /* Restart the transmitter if disabled */
  136. if (!(readl(eth->iobase + RAVB_REG_TCCR) & TCCR_TSRQ0))
  137. setbits_le32(eth->iobase + RAVB_REG_TCCR, TCCR_TSRQ0);
  138. /* Wait until packet is transmitted */
  139. start = get_timer(0);
  140. while (get_timer(start) < RAVB_TX_TIMEOUT_MS) {
  141. ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
  142. if ((desc->ctrl & RAVB_DESC_DT_MASK) != RAVB_DESC_DT_FSINGLE)
  143. break;
  144. udelay(10);
  145. };
  146. if (get_timer(start) >= RAVB_TX_TIMEOUT_MS)
  147. return -ETIMEDOUT;
  148. eth->tx_desc_idx = (eth->tx_desc_idx + 1) % (RAVB_NUM_TX_DESC - 1);
  149. return 0;
  150. }
  151. static int ravb_recv(struct udevice *dev, int flags, uchar **packetp)
  152. {
  153. struct ravb_priv *eth = dev_get_priv(dev);
  154. struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
  155. int len;
  156. u8 *packet;
  157. /* Check if the rx descriptor is ready */
  158. ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
  159. if ((desc->data.ctrl & RAVB_DESC_DT_MASK) == RAVB_DESC_DT_FEMPTY)
  160. return -EAGAIN;
  161. /* Check for errors */
  162. if (desc->data.ctrl & RAVB_RX_DESC_MSC_RX_ERR_MASK) {
  163. desc->data.ctrl &= ~RAVB_RX_DESC_MSC_MASK;
  164. return -EAGAIN;
  165. }
  166. len = desc->data.ctrl & RAVB_DESC_DS_MASK;
  167. packet = (u8 *)(uintptr_t)desc->data.dptr;
  168. ravb_invalidate_dcache((uintptr_t)packet, len);
  169. *packetp = packet;
  170. return len;
  171. }
  172. static int ravb_free_pkt(struct udevice *dev, uchar *packet, int length)
  173. {
  174. struct ravb_priv *eth = dev_get_priv(dev);
  175. struct ravb_rxdesc *desc = &eth->rx_desc[eth->rx_desc_idx];
  176. /* Make current descriptor available again */
  177. desc->data.ctrl = RAVB_DESC_DT_FEMPTY | RAVB_DESC_DS(PKTSIZE_ALIGN);
  178. ravb_flush_dcache((uintptr_t)desc, sizeof(*desc));
  179. /* Point to the next descriptor */
  180. eth->rx_desc_idx = (eth->rx_desc_idx + 1) % RAVB_NUM_RX_DESC;
  181. desc = &eth->rx_desc[eth->rx_desc_idx];
  182. ravb_invalidate_dcache((uintptr_t)desc, sizeof(*desc));
  183. return 0;
  184. }
  185. static int ravb_reset(struct udevice *dev)
  186. {
  187. struct ravb_priv *eth = dev_get_priv(dev);
  188. /* Set config mode */
  189. writel(CCC_OPC_CONFIG, eth->iobase + RAVB_REG_CCC);
  190. /* Check the operating mode is changed to the config mode. */
  191. return wait_for_bit_le32(eth->iobase + RAVB_REG_CSR,
  192. CSR_OPS_CONFIG, true, 100, true);
  193. }
  194. static void ravb_base_desc_init(struct ravb_priv *eth)
  195. {
  196. const u32 desc_size = RAVB_NUM_BASE_DESC * sizeof(struct ravb_desc);
  197. int i;
  198. /* Initialize all descriptors */
  199. memset(eth->base_desc, 0x0, desc_size);
  200. for (i = 0; i < RAVB_NUM_BASE_DESC; i++)
  201. eth->base_desc[i].ctrl = RAVB_DESC_DT_EOS;
  202. ravb_flush_dcache((uintptr_t)eth->base_desc, desc_size);
  203. /* Register the descriptor base address table */
  204. writel((uintptr_t)eth->base_desc, eth->iobase + RAVB_REG_DBAT);
  205. }
  206. static void ravb_tx_desc_init(struct ravb_priv *eth)
  207. {
  208. const u32 desc_size = RAVB_NUM_TX_DESC * sizeof(struct ravb_desc);
  209. int i;
  210. /* Initialize all descriptors */
  211. memset(eth->tx_desc, 0x0, desc_size);
  212. eth->tx_desc_idx = 0;
  213. for (i = 0; i < RAVB_NUM_TX_DESC; i++)
  214. eth->tx_desc[i].ctrl = RAVB_DESC_DT_EEMPTY;
  215. /* Mark the end of the descriptors */
  216. eth->tx_desc[RAVB_NUM_TX_DESC - 1].ctrl = RAVB_DESC_DT_LINKFIX;
  217. eth->tx_desc[RAVB_NUM_TX_DESC - 1].dptr = (uintptr_t)eth->tx_desc;
  218. ravb_flush_dcache((uintptr_t)eth->tx_desc, desc_size);
  219. /* Point the controller to the TX descriptor list. */
  220. eth->base_desc[RAVB_TX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
  221. eth->base_desc[RAVB_TX_QUEUE_OFFSET].dptr = (uintptr_t)eth->tx_desc;
  222. ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_TX_QUEUE_OFFSET],
  223. sizeof(struct ravb_desc));
  224. }
  225. static void ravb_rx_desc_init(struct ravb_priv *eth)
  226. {
  227. const u32 desc_size = RAVB_NUM_RX_DESC * sizeof(struct ravb_rxdesc);
  228. int i;
  229. /* Initialize all descriptors */
  230. memset(eth->rx_desc, 0x0, desc_size);
  231. eth->rx_desc_idx = 0;
  232. for (i = 0; i < RAVB_NUM_RX_DESC; i++) {
  233. eth->rx_desc[i].data.ctrl = RAVB_DESC_DT_EEMPTY |
  234. RAVB_DESC_DS(PKTSIZE_ALIGN);
  235. eth->rx_desc[i].data.dptr = (uintptr_t)eth->rx_desc[i].packet;
  236. eth->rx_desc[i].link.ctrl = RAVB_DESC_DT_LINKFIX;
  237. eth->rx_desc[i].link.dptr = (uintptr_t)&eth->rx_desc[i + 1];
  238. }
  239. /* Mark the end of the descriptors */
  240. eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.ctrl = RAVB_DESC_DT_LINKFIX;
  241. eth->rx_desc[RAVB_NUM_RX_DESC - 1].link.dptr = (uintptr_t)eth->rx_desc;
  242. ravb_flush_dcache((uintptr_t)eth->rx_desc, desc_size);
  243. /* Point the controller to the rx descriptor list */
  244. eth->base_desc[RAVB_RX_QUEUE_OFFSET].ctrl = RAVB_DESC_DT_LINKFIX;
  245. eth->base_desc[RAVB_RX_QUEUE_OFFSET].dptr = (uintptr_t)eth->rx_desc;
  246. ravb_flush_dcache((uintptr_t)&eth->base_desc[RAVB_RX_QUEUE_OFFSET],
  247. sizeof(struct ravb_desc));
  248. }
  249. static int ravb_phy_config(struct udevice *dev)
  250. {
  251. struct ravb_priv *eth = dev_get_priv(dev);
  252. struct eth_pdata *pdata = dev_get_platdata(dev);
  253. struct phy_device *phydev;
  254. int mask = 0xffffffff, reg;
  255. if (dm_gpio_is_valid(&eth->reset_gpio)) {
  256. dm_gpio_set_value(&eth->reset_gpio, 1);
  257. mdelay(20);
  258. dm_gpio_set_value(&eth->reset_gpio, 0);
  259. mdelay(1);
  260. }
  261. phydev = phy_find_by_mask(eth->bus, mask, pdata->phy_interface);
  262. if (!phydev)
  263. return -ENODEV;
  264. phy_connect_dev(phydev, dev);
  265. eth->phydev = phydev;
  266. phydev->supported &= SUPPORTED_100baseT_Full |
  267. SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
  268. SUPPORTED_TP | SUPPORTED_MII | SUPPORTED_Pause |
  269. SUPPORTED_Asym_Pause;
  270. if (pdata->max_speed != 1000) {
  271. phydev->supported &= ~SUPPORTED_1000baseT_Full;
  272. reg = phy_read(phydev, -1, MII_CTRL1000);
  273. reg &= ~(BIT(9) | BIT(8));
  274. phy_write(phydev, -1, MII_CTRL1000, reg);
  275. }
  276. phy_config(phydev);
  277. return 0;
  278. }
  279. /* Set Mac address */
  280. static int ravb_write_hwaddr(struct udevice *dev)
  281. {
  282. struct ravb_priv *eth = dev_get_priv(dev);
  283. struct eth_pdata *pdata = dev_get_platdata(dev);
  284. unsigned char *mac = pdata->enetaddr;
  285. writel((mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3],
  286. eth->iobase + RAVB_REG_MAHR);
  287. writel((mac[4] << 8) | mac[5], eth->iobase + RAVB_REG_MALR);
  288. return 0;
  289. }
  290. /* E-MAC init function */
  291. static int ravb_mac_init(struct ravb_priv *eth)
  292. {
  293. /* Disable MAC Interrupt */
  294. writel(0, eth->iobase + RAVB_REG_ECSIPR);
  295. /* Recv frame limit set register */
  296. writel(RFLR_RFL_MIN, eth->iobase + RAVB_REG_RFLR);
  297. return 0;
  298. }
  299. /* AVB-DMAC init function */
  300. static int ravb_dmac_init(struct udevice *dev)
  301. {
  302. struct ravb_priv *eth = dev_get_priv(dev);
  303. struct eth_pdata *pdata = dev_get_platdata(dev);
  304. int ret = 0;
  305. /* Set CONFIG mode */
  306. ret = ravb_reset(dev);
  307. if (ret)
  308. return ret;
  309. /* Disable all interrupts */
  310. writel(0, eth->iobase + RAVB_REG_RIC0);
  311. writel(0, eth->iobase + RAVB_REG_RIC1);
  312. writel(0, eth->iobase + RAVB_REG_RIC2);
  313. writel(0, eth->iobase + RAVB_REG_TIC);
  314. /* Set little endian */
  315. clrbits_le32(eth->iobase + RAVB_REG_CCC, CCC_BOC);
  316. /* AVB rx set */
  317. writel(0x18000001, eth->iobase + RAVB_REG_RCR);
  318. /* FIFO size set */
  319. writel(0x00222210, eth->iobase + RAVB_REG_TGC);
  320. /* Delay CLK: 2ns (not applicable on R-Car E3/D3) */
  321. if ((rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77990) ||
  322. (rmobile_get_cpu_type() == RMOBILE_CPU_TYPE_R8A77995))
  323. return 0;
  324. if ((pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_ID) ||
  325. (pdata->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID))
  326. writel(APSR_TDM, eth->iobase + RAVB_REG_APSR);
  327. return 0;
  328. }
  329. static int ravb_config(struct udevice *dev)
  330. {
  331. struct ravb_priv *eth = dev_get_priv(dev);
  332. struct phy_device *phy = eth->phydev;
  333. u32 mask = ECMR_CHG_DM | ECMR_RE | ECMR_TE;
  334. int ret;
  335. /* Configure AVB-DMAC register */
  336. ravb_dmac_init(dev);
  337. /* Configure E-MAC registers */
  338. ravb_mac_init(eth);
  339. ravb_write_hwaddr(dev);
  340. ret = phy_startup(phy);
  341. if (ret)
  342. return ret;
  343. /* Set the transfer speed */
  344. if (phy->speed == 100)
  345. writel(0, eth->iobase + RAVB_REG_GECMR);
  346. else if (phy->speed == 1000)
  347. writel(1, eth->iobase + RAVB_REG_GECMR);
  348. /* Check if full duplex mode is supported by the phy */
  349. if (phy->duplex)
  350. mask |= ECMR_DM;
  351. writel(mask, eth->iobase + RAVB_REG_ECMR);
  352. return 0;
  353. }
  354. static int ravb_start(struct udevice *dev)
  355. {
  356. struct ravb_priv *eth = dev_get_priv(dev);
  357. int ret;
  358. ret = ravb_reset(dev);
  359. if (ret)
  360. return ret;
  361. ravb_base_desc_init(eth);
  362. ravb_tx_desc_init(eth);
  363. ravb_rx_desc_init(eth);
  364. ret = ravb_config(dev);
  365. if (ret)
  366. return ret;
  367. /* Setting the control will start the AVB-DMAC process. */
  368. writel(CCC_OPC_OPERATION, eth->iobase + RAVB_REG_CCC);
  369. return 0;
  370. }
  371. static void ravb_stop(struct udevice *dev)
  372. {
  373. struct ravb_priv *eth = dev_get_priv(dev);
  374. phy_shutdown(eth->phydev);
  375. ravb_reset(dev);
  376. }
  377. static int ravb_probe(struct udevice *dev)
  378. {
  379. struct eth_pdata *pdata = dev_get_platdata(dev);
  380. struct ravb_priv *eth = dev_get_priv(dev);
  381. struct ofnode_phandle_args phandle_args;
  382. struct mii_dev *mdiodev;
  383. void __iomem *iobase;
  384. int ret;
  385. iobase = map_physmem(pdata->iobase, 0x1000, MAP_NOCACHE);
  386. eth->iobase = iobase;
  387. ret = clk_get_by_index(dev, 0, &eth->clk);
  388. if (ret < 0)
  389. goto err_mdio_alloc;
  390. ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0, &phandle_args);
  391. if (!ret) {
  392. gpio_request_by_name_nodev(phandle_args.node, "reset-gpios", 0,
  393. &eth->reset_gpio, GPIOD_IS_OUT);
  394. }
  395. if (!dm_gpio_is_valid(&eth->reset_gpio)) {
  396. gpio_request_by_name(dev, "reset-gpios", 0, &eth->reset_gpio,
  397. GPIOD_IS_OUT);
  398. }
  399. mdiodev = mdio_alloc();
  400. if (!mdiodev) {
  401. ret = -ENOMEM;
  402. goto err_mdio_alloc;
  403. }
  404. mdiodev->read = bb_miiphy_read;
  405. mdiodev->write = bb_miiphy_write;
  406. bb_miiphy_buses[0].priv = eth;
  407. snprintf(mdiodev->name, sizeof(mdiodev->name), dev->name);
  408. ret = mdio_register(mdiodev);
  409. if (ret < 0)
  410. goto err_mdio_register;
  411. eth->bus = miiphy_get_dev_by_name(dev->name);
  412. /* Bring up PHY */
  413. ret = clk_enable(&eth->clk);
  414. if (ret)
  415. goto err_mdio_register;
  416. ret = ravb_reset(dev);
  417. if (ret)
  418. goto err_mdio_reset;
  419. ret = ravb_phy_config(dev);
  420. if (ret)
  421. goto err_mdio_reset;
  422. return 0;
  423. err_mdio_reset:
  424. clk_disable(&eth->clk);
  425. err_mdio_register:
  426. mdio_free(mdiodev);
  427. err_mdio_alloc:
  428. unmap_physmem(eth->iobase, MAP_NOCACHE);
  429. return ret;
  430. }
  431. static int ravb_remove(struct udevice *dev)
  432. {
  433. struct ravb_priv *eth = dev_get_priv(dev);
  434. clk_disable(&eth->clk);
  435. free(eth->phydev);
  436. mdio_unregister(eth->bus);
  437. mdio_free(eth->bus);
  438. if (dm_gpio_is_valid(&eth->reset_gpio))
  439. dm_gpio_free(dev, &eth->reset_gpio);
  440. unmap_physmem(eth->iobase, MAP_NOCACHE);
  441. return 0;
  442. }
  443. int ravb_bb_init(struct bb_miiphy_bus *bus)
  444. {
  445. return 0;
  446. }
  447. int ravb_bb_mdio_active(struct bb_miiphy_bus *bus)
  448. {
  449. struct ravb_priv *eth = bus->priv;
  450. setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
  451. return 0;
  452. }
  453. int ravb_bb_mdio_tristate(struct bb_miiphy_bus *bus)
  454. {
  455. struct ravb_priv *eth = bus->priv;
  456. clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MMD);
  457. return 0;
  458. }
  459. int ravb_bb_set_mdio(struct bb_miiphy_bus *bus, int v)
  460. {
  461. struct ravb_priv *eth = bus->priv;
  462. if (v)
  463. setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
  464. else
  465. clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDO);
  466. return 0;
  467. }
  468. int ravb_bb_get_mdio(struct bb_miiphy_bus *bus, int *v)
  469. {
  470. struct ravb_priv *eth = bus->priv;
  471. *v = (readl(eth->iobase + RAVB_REG_PIR) & PIR_MDI) >> 3;
  472. return 0;
  473. }
  474. int ravb_bb_set_mdc(struct bb_miiphy_bus *bus, int v)
  475. {
  476. struct ravb_priv *eth = bus->priv;
  477. if (v)
  478. setbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
  479. else
  480. clrbits_le32(eth->iobase + RAVB_REG_PIR, PIR_MDC);
  481. return 0;
  482. }
  483. int ravb_bb_delay(struct bb_miiphy_bus *bus)
  484. {
  485. udelay(10);
  486. return 0;
  487. }
  488. struct bb_miiphy_bus bb_miiphy_buses[] = {
  489. {
  490. .name = "ravb",
  491. .init = ravb_bb_init,
  492. .mdio_active = ravb_bb_mdio_active,
  493. .mdio_tristate = ravb_bb_mdio_tristate,
  494. .set_mdio = ravb_bb_set_mdio,
  495. .get_mdio = ravb_bb_get_mdio,
  496. .set_mdc = ravb_bb_set_mdc,
  497. .delay = ravb_bb_delay,
  498. },
  499. };
  500. int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses);
  501. static const struct eth_ops ravb_ops = {
  502. .start = ravb_start,
  503. .send = ravb_send,
  504. .recv = ravb_recv,
  505. .free_pkt = ravb_free_pkt,
  506. .stop = ravb_stop,
  507. .write_hwaddr = ravb_write_hwaddr,
  508. };
  509. int ravb_ofdata_to_platdata(struct udevice *dev)
  510. {
  511. struct eth_pdata *pdata = dev_get_platdata(dev);
  512. const char *phy_mode;
  513. const fdt32_t *cell;
  514. int ret = 0;
  515. pdata->iobase = dev_read_addr(dev);
  516. pdata->phy_interface = -1;
  517. phy_mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy-mode",
  518. NULL);
  519. if (phy_mode)
  520. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  521. if (pdata->phy_interface == -1) {
  522. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  523. return -EINVAL;
  524. }
  525. pdata->max_speed = 1000;
  526. cell = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "max-speed", NULL);
  527. if (cell)
  528. pdata->max_speed = fdt32_to_cpu(*cell);
  529. sprintf(bb_miiphy_buses[0].name, dev->name);
  530. return ret;
  531. }
  532. static const struct udevice_id ravb_ids[] = {
  533. { .compatible = "renesas,etheravb-r8a7795" },
  534. { .compatible = "renesas,etheravb-r8a7796" },
  535. { .compatible = "renesas,etheravb-r8a77965" },
  536. { .compatible = "renesas,etheravb-r8a77970" },
  537. { .compatible = "renesas,etheravb-r8a77990" },
  538. { .compatible = "renesas,etheravb-r8a77995" },
  539. { .compatible = "renesas,etheravb-rcar-gen3" },
  540. { }
  541. };
  542. U_BOOT_DRIVER(eth_ravb) = {
  543. .name = "ravb",
  544. .id = UCLASS_ETH,
  545. .of_match = ravb_ids,
  546. .ofdata_to_platdata = ravb_ofdata_to_platdata,
  547. .probe = ravb_probe,
  548. .remove = ravb_remove,
  549. .ops = &ravb_ops,
  550. .priv_auto_alloc_size = sizeof(struct ravb_priv),
  551. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  552. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  553. };