pch_gbe.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
  4. *
  5. * Intel Platform Controller Hub EG20T (codename Topcliff) GMAC Driver
  6. */
  7. #include <common.h>
  8. #include <cpu_func.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <log.h>
  12. #include <malloc.h>
  13. #include <asm/io.h>
  14. #include <pci.h>
  15. #include <miiphy.h>
  16. #include <linux/delay.h>
  17. #include "pch_gbe.h"
  18. #if !defined(CONFIG_PHYLIB)
  19. # error "PCH Gigabit Ethernet driver requires PHYLIB - missing CONFIG_PHYLIB"
  20. #endif
  21. static struct pci_device_id supported[] = {
  22. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TCF_GBE) },
  23. { }
  24. };
  25. static void pch_gbe_mac_read(struct pch_gbe_regs *mac_regs, u8 *addr)
  26. {
  27. u32 macid_hi, macid_lo;
  28. macid_hi = readl(&mac_regs->mac_adr[0].high);
  29. macid_lo = readl(&mac_regs->mac_adr[0].low) & 0xffff;
  30. debug("pch_gbe: macid_hi %#x macid_lo %#x\n", macid_hi, macid_lo);
  31. addr[0] = (u8)(macid_hi & 0xff);
  32. addr[1] = (u8)((macid_hi >> 8) & 0xff);
  33. addr[2] = (u8)((macid_hi >> 16) & 0xff);
  34. addr[3] = (u8)((macid_hi >> 24) & 0xff);
  35. addr[4] = (u8)(macid_lo & 0xff);
  36. addr[5] = (u8)((macid_lo >> 8) & 0xff);
  37. }
  38. static int pch_gbe_mac_write(struct pch_gbe_regs *mac_regs, u8 *addr)
  39. {
  40. u32 macid_hi, macid_lo;
  41. ulong start;
  42. macid_hi = addr[0] + (addr[1] << 8) + (addr[2] << 16) + (addr[3] << 24);
  43. macid_lo = addr[4] + (addr[5] << 8);
  44. writel(macid_hi, &mac_regs->mac_adr[0].high);
  45. writel(macid_lo, &mac_regs->mac_adr[0].low);
  46. writel(0xfffe, &mac_regs->addr_mask);
  47. start = get_timer(0);
  48. while (get_timer(start) < PCH_GBE_TIMEOUT) {
  49. if (!(readl(&mac_regs->addr_mask) & PCH_GBE_BUSY))
  50. return 0;
  51. udelay(10);
  52. }
  53. return -ETIME;
  54. }
  55. static int pch_gbe_reset(struct udevice *dev)
  56. {
  57. struct pch_gbe_priv *priv = dev_get_priv(dev);
  58. struct eth_pdata *plat = dev_get_platdata(dev);
  59. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  60. ulong start;
  61. priv->rx_idx = 0;
  62. priv->tx_idx = 0;
  63. writel(PCH_GBE_ALL_RST, &mac_regs->reset);
  64. /*
  65. * Configure the MAC to RGMII mode after reset
  66. *
  67. * For some unknown reason, we must do the configuration here right
  68. * after resetting the whole MAC, otherwise the reset bit in the RESET
  69. * register will never be cleared by the hardware. And there is another
  70. * way of having the same magic, that is to configure the MODE register
  71. * to have the MAC work in MII/GMII mode, which is how current Linux
  72. * pch_gbe driver does. Since anyway we need program the MAC to RGMII
  73. * mode in the driver, we just do it here.
  74. *
  75. * Note: this behavior is not documented in the hardware manual.
  76. */
  77. writel(PCH_GBE_RGMII_MODE_RGMII | PCH_GBE_CHIP_TYPE_INTERNAL,
  78. &mac_regs->rgmii_ctrl);
  79. start = get_timer(0);
  80. while (get_timer(start) < PCH_GBE_TIMEOUT) {
  81. if (!(readl(&mac_regs->reset) & PCH_GBE_ALL_RST)) {
  82. /*
  83. * Soft reset clears hardware MAC address registers,
  84. * so we have to reload MAC address here in order to
  85. * make linux pch_gbe driver happy.
  86. */
  87. return pch_gbe_mac_write(mac_regs, plat->enetaddr);
  88. }
  89. udelay(10);
  90. }
  91. debug("pch_gbe: reset timeout\n");
  92. return -ETIME;
  93. }
  94. static void pch_gbe_rx_descs_init(struct udevice *dev)
  95. {
  96. struct pch_gbe_priv *priv = dev_get_priv(dev);
  97. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  98. struct pch_gbe_rx_desc *rx_desc = &priv->rx_desc[0];
  99. int i;
  100. memset(rx_desc, 0, sizeof(struct pch_gbe_rx_desc) * PCH_GBE_DESC_NUM);
  101. for (i = 0; i < PCH_GBE_DESC_NUM; i++)
  102. rx_desc[i].buffer_addr = dm_pci_virt_to_mem(priv->dev,
  103. priv->rx_buff[i]);
  104. flush_dcache_range((ulong)rx_desc, (ulong)&rx_desc[PCH_GBE_DESC_NUM]);
  105. writel(dm_pci_virt_to_mem(priv->dev, rx_desc),
  106. &mac_regs->rx_dsc_base);
  107. writel(sizeof(struct pch_gbe_rx_desc) * (PCH_GBE_DESC_NUM - 1),
  108. &mac_regs->rx_dsc_size);
  109. writel(dm_pci_virt_to_mem(priv->dev, rx_desc + 1),
  110. &mac_regs->rx_dsc_sw_p);
  111. }
  112. static void pch_gbe_tx_descs_init(struct udevice *dev)
  113. {
  114. struct pch_gbe_priv *priv = dev_get_priv(dev);
  115. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  116. struct pch_gbe_tx_desc *tx_desc = &priv->tx_desc[0];
  117. memset(tx_desc, 0, sizeof(struct pch_gbe_tx_desc) * PCH_GBE_DESC_NUM);
  118. flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[PCH_GBE_DESC_NUM]);
  119. writel(dm_pci_virt_to_mem(priv->dev, tx_desc),
  120. &mac_regs->tx_dsc_base);
  121. writel(sizeof(struct pch_gbe_tx_desc) * (PCH_GBE_DESC_NUM - 1),
  122. &mac_regs->tx_dsc_size);
  123. writel(dm_pci_virt_to_mem(priv->dev, tx_desc + 1),
  124. &mac_regs->tx_dsc_sw_p);
  125. }
  126. static void pch_gbe_adjust_link(struct pch_gbe_regs *mac_regs,
  127. struct phy_device *phydev)
  128. {
  129. if (!phydev->link) {
  130. printf("%s: No link.\n", phydev->dev->name);
  131. return;
  132. }
  133. clrbits_le32(&mac_regs->rgmii_ctrl,
  134. PCH_GBE_RGMII_RATE_2_5M | PCH_GBE_CRS_SEL);
  135. clrbits_le32(&mac_regs->mode,
  136. PCH_GBE_MODE_GMII_ETHER | PCH_GBE_MODE_FULL_DUPLEX);
  137. switch (phydev->speed) {
  138. case 1000:
  139. setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_125M);
  140. setbits_le32(&mac_regs->mode, PCH_GBE_MODE_GMII_ETHER);
  141. break;
  142. case 100:
  143. setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_25M);
  144. setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
  145. break;
  146. case 10:
  147. setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_RGMII_RATE_2_5M);
  148. setbits_le32(&mac_regs->mode, PCH_GBE_MODE_MII_ETHER);
  149. break;
  150. }
  151. if (phydev->duplex) {
  152. setbits_le32(&mac_regs->rgmii_ctrl, PCH_GBE_CRS_SEL);
  153. setbits_le32(&mac_regs->mode, PCH_GBE_MODE_FULL_DUPLEX);
  154. }
  155. printf("Speed: %d, %s duplex\n", phydev->speed,
  156. (phydev->duplex) ? "full" : "half");
  157. return;
  158. }
  159. static int pch_gbe_start(struct udevice *dev)
  160. {
  161. struct pch_gbe_priv *priv = dev_get_priv(dev);
  162. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  163. if (pch_gbe_reset(dev))
  164. return -1;
  165. pch_gbe_rx_descs_init(dev);
  166. pch_gbe_tx_descs_init(dev);
  167. /* Enable frame bursting */
  168. writel(PCH_GBE_MODE_FR_BST, &mac_regs->mode);
  169. /* Disable TCP/IP accelerator */
  170. writel(PCH_GBE_RX_TCPIPACC_OFF, &mac_regs->tcpip_acc);
  171. /* Disable RX flow control */
  172. writel(0, &mac_regs->rx_fctrl);
  173. /* Configure RX/TX mode */
  174. writel(PCH_GBE_RH_ALM_EMP_16 | PCH_GBE_RH_ALM_FULL_16 |
  175. PCH_GBE_RH_RD_TRG_32, &mac_regs->rx_mode);
  176. writel(PCH_GBE_TM_TH_TX_STRT_32 | PCH_GBE_TM_TH_ALM_EMP_16 |
  177. PCH_GBE_TM_TH_ALM_FULL_32 | PCH_GBE_TM_ST_AND_FD |
  178. PCH_GBE_TM_SHORT_PKT, &mac_regs->tx_mode);
  179. /* Start up the PHY */
  180. if (phy_startup(priv->phydev)) {
  181. printf("Could not initialize PHY %s\n",
  182. priv->phydev->dev->name);
  183. return -1;
  184. }
  185. pch_gbe_adjust_link(mac_regs, priv->phydev);
  186. if (!priv->phydev->link)
  187. return -1;
  188. /* Enable TX & RX */
  189. writel(PCH_GBE_RX_DMA_EN | PCH_GBE_TX_DMA_EN, &mac_regs->dma_ctrl);
  190. writel(PCH_GBE_MRE_MAC_RX_EN, &mac_regs->mac_rx_en);
  191. return 0;
  192. }
  193. static void pch_gbe_stop(struct udevice *dev)
  194. {
  195. struct pch_gbe_priv *priv = dev_get_priv(dev);
  196. pch_gbe_reset(dev);
  197. phy_shutdown(priv->phydev);
  198. }
  199. static int pch_gbe_send(struct udevice *dev, void *packet, int length)
  200. {
  201. struct pch_gbe_priv *priv = dev_get_priv(dev);
  202. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  203. struct pch_gbe_tx_desc *tx_head, *tx_desc;
  204. u16 frame_ctrl = 0;
  205. u32 int_st;
  206. ulong start;
  207. flush_dcache_range((ulong)packet, (ulong)packet + length);
  208. tx_head = &priv->tx_desc[0];
  209. tx_desc = &priv->tx_desc[priv->tx_idx];
  210. if (length < 64)
  211. frame_ctrl |= PCH_GBE_TXD_CTRL_APAD;
  212. tx_desc->buffer_addr = dm_pci_virt_to_mem(priv->dev, packet);
  213. tx_desc->length = length;
  214. tx_desc->tx_words_eob = length + 3;
  215. tx_desc->tx_frame_ctrl = frame_ctrl;
  216. tx_desc->dma_status = 0;
  217. tx_desc->gbec_status = 0;
  218. flush_dcache_range((ulong)tx_desc, (ulong)&tx_desc[1]);
  219. /* Test the wrap-around condition */
  220. if (++priv->tx_idx >= PCH_GBE_DESC_NUM)
  221. priv->tx_idx = 0;
  222. writel(dm_pci_virt_to_mem(priv->dev, tx_head + priv->tx_idx),
  223. &mac_regs->tx_dsc_sw_p);
  224. start = get_timer(0);
  225. while (get_timer(start) < PCH_GBE_TIMEOUT) {
  226. int_st = readl(&mac_regs->int_st);
  227. if (int_st & PCH_GBE_INT_TX_CMPLT)
  228. return 0;
  229. udelay(10);
  230. }
  231. debug("pch_gbe: sent failed\n");
  232. return -ETIME;
  233. }
  234. static int pch_gbe_recv(struct udevice *dev, int flags, uchar **packetp)
  235. {
  236. struct pch_gbe_priv *priv = dev_get_priv(dev);
  237. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  238. struct pch_gbe_rx_desc *rx_desc;
  239. ulong hw_desc, length;
  240. void *buffer;
  241. rx_desc = &priv->rx_desc[priv->rx_idx];
  242. readl(&mac_regs->int_st);
  243. hw_desc = readl(&mac_regs->rx_dsc_hw_p_hld);
  244. /* Just return if not receiving any packet */
  245. if (virt_to_phys(rx_desc) == hw_desc)
  246. return -EAGAIN;
  247. /* Invalidate the descriptor */
  248. invalidate_dcache_range((ulong)rx_desc, (ulong)&rx_desc[1]);
  249. length = rx_desc->rx_words_eob - 3 - ETH_FCS_LEN;
  250. buffer = dm_pci_mem_to_virt(priv->dev, rx_desc->buffer_addr, length, 0);
  251. invalidate_dcache_range((ulong)buffer, (ulong)buffer + length);
  252. *packetp = (uchar *)buffer;
  253. return length;
  254. }
  255. static int pch_gbe_free_pkt(struct udevice *dev, uchar *packet, int length)
  256. {
  257. struct pch_gbe_priv *priv = dev_get_priv(dev);
  258. struct pch_gbe_regs *mac_regs = priv->mac_regs;
  259. struct pch_gbe_rx_desc *rx_head = &priv->rx_desc[0];
  260. int rx_swp;
  261. /* Test the wrap-around condition */
  262. if (++priv->rx_idx >= PCH_GBE_DESC_NUM)
  263. priv->rx_idx = 0;
  264. rx_swp = priv->rx_idx;
  265. if (++rx_swp >= PCH_GBE_DESC_NUM)
  266. rx_swp = 0;
  267. writel(dm_pci_virt_to_mem(priv->dev, rx_head + rx_swp),
  268. &mac_regs->rx_dsc_sw_p);
  269. return 0;
  270. }
  271. static int pch_gbe_mdio_ready(struct pch_gbe_regs *mac_regs)
  272. {
  273. ulong start = get_timer(0);
  274. while (get_timer(start) < PCH_GBE_TIMEOUT) {
  275. if (readl(&mac_regs->miim) & PCH_GBE_MIIM_OPER_READY)
  276. return 0;
  277. udelay(10);
  278. }
  279. return -ETIME;
  280. }
  281. static int pch_gbe_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  282. {
  283. struct pch_gbe_regs *mac_regs = bus->priv;
  284. u32 miim;
  285. if (pch_gbe_mdio_ready(mac_regs))
  286. return -ETIME;
  287. miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
  288. (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
  289. PCH_GBE_MIIM_OPER_READ;
  290. writel(miim, &mac_regs->miim);
  291. if (pch_gbe_mdio_ready(mac_regs))
  292. return -ETIME;
  293. return readl(&mac_regs->miim) & 0xffff;
  294. }
  295. static int pch_gbe_mdio_write(struct mii_dev *bus, int addr, int devad,
  296. int reg, u16 val)
  297. {
  298. struct pch_gbe_regs *mac_regs = bus->priv;
  299. u32 miim;
  300. if (pch_gbe_mdio_ready(mac_regs))
  301. return -ETIME;
  302. miim = (addr << PCH_GBE_MIIM_PHY_ADDR_SHIFT) |
  303. (reg << PCH_GBE_MIIM_REG_ADDR_SHIFT) |
  304. PCH_GBE_MIIM_OPER_WRITE | val;
  305. writel(miim, &mac_regs->miim);
  306. if (pch_gbe_mdio_ready(mac_regs))
  307. return -ETIME;
  308. else
  309. return 0;
  310. }
  311. static int pch_gbe_mdio_init(const char *name, struct pch_gbe_regs *mac_regs)
  312. {
  313. struct mii_dev *bus;
  314. bus = mdio_alloc();
  315. if (!bus) {
  316. debug("pch_gbe: failed to allocate MDIO bus\n");
  317. return -ENOMEM;
  318. }
  319. bus->read = pch_gbe_mdio_read;
  320. bus->write = pch_gbe_mdio_write;
  321. strcpy(bus->name, name);
  322. bus->priv = (void *)mac_regs;
  323. return mdio_register(bus);
  324. }
  325. static int pch_gbe_phy_init(struct udevice *dev)
  326. {
  327. struct pch_gbe_priv *priv = dev_get_priv(dev);
  328. struct eth_pdata *plat = dev_get_platdata(dev);
  329. struct phy_device *phydev;
  330. int mask = 0xffffffff;
  331. phydev = phy_find_by_mask(priv->bus, mask, plat->phy_interface);
  332. if (!phydev) {
  333. printf("pch_gbe: cannot find the phy\n");
  334. return -1;
  335. }
  336. phy_connect_dev(phydev, dev);
  337. phydev->supported &= PHY_GBIT_FEATURES;
  338. phydev->advertising = phydev->supported;
  339. priv->phydev = phydev;
  340. phy_config(phydev);
  341. return 0;
  342. }
  343. static int pch_gbe_probe(struct udevice *dev)
  344. {
  345. struct pch_gbe_priv *priv;
  346. struct eth_pdata *plat = dev_get_platdata(dev);
  347. void *iobase;
  348. int err;
  349. /*
  350. * The priv structure contains the descriptors and frame buffers which
  351. * need a strict buswidth alignment (64 bytes). This is guaranteed by
  352. * DM_FLAG_ALLOC_PRIV_DMA flag in the U_BOOT_DRIVER.
  353. */
  354. priv = dev_get_priv(dev);
  355. priv->dev = dev;
  356. iobase = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_1, PCI_REGION_MEM);
  357. plat->iobase = (ulong)iobase;
  358. priv->mac_regs = (struct pch_gbe_regs *)iobase;
  359. /* Read MAC address from SROM and initialize dev->enetaddr with it */
  360. pch_gbe_mac_read(priv->mac_regs, plat->enetaddr);
  361. plat->phy_interface = PHY_INTERFACE_MODE_RGMII;
  362. pch_gbe_mdio_init(dev->name, priv->mac_regs);
  363. priv->bus = miiphy_get_dev_by_name(dev->name);
  364. err = pch_gbe_reset(dev);
  365. if (err)
  366. return err;
  367. return pch_gbe_phy_init(dev);
  368. }
  369. static int pch_gbe_remove(struct udevice *dev)
  370. {
  371. struct pch_gbe_priv *priv = dev_get_priv(dev);
  372. free(priv->phydev);
  373. mdio_unregister(priv->bus);
  374. mdio_free(priv->bus);
  375. return 0;
  376. }
  377. static const struct eth_ops pch_gbe_ops = {
  378. .start = pch_gbe_start,
  379. .send = pch_gbe_send,
  380. .recv = pch_gbe_recv,
  381. .free_pkt = pch_gbe_free_pkt,
  382. .stop = pch_gbe_stop,
  383. };
  384. static const struct udevice_id pch_gbe_ids[] = {
  385. { .compatible = "intel,pch-gbe" },
  386. { }
  387. };
  388. U_BOOT_DRIVER(eth_pch_gbe) = {
  389. .name = "pch_gbe",
  390. .id = UCLASS_ETH,
  391. .of_match = pch_gbe_ids,
  392. .probe = pch_gbe_probe,
  393. .remove = pch_gbe_remove,
  394. .ops = &pch_gbe_ops,
  395. .priv_auto_alloc_size = sizeof(struct pch_gbe_priv),
  396. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  397. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  398. };
  399. U_BOOT_PCI_DEVICE(eth_pch_gbe, supported);