ns8382x.c 23 KB

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  1. /*
  2. ns8382x.c: A U-Boot driver for the NatSemi DP8382[01].
  3. ported by: Mark A. Rakes (mark_rakes@vivato.net)
  4. Adapted from:
  5. 1. an Etherboot driver for DP8381[56] written by:
  6. Copyright (C) 2001 Entity Cyber, Inc.
  7. This development of this Etherboot driver was funded by
  8. Sicom Systems: http://www.sicompos.com/
  9. Author: Marty Connor (mdc@thinguin.org)
  10. Adapted from a Linux driver which was written by Donald Becker
  11. This software may be used and distributed according to the terms
  12. of the GNU Public License (GPL), incorporated herein by reference.
  13. 2. A Linux driver by Donald Becker, ns820.c:
  14. Written/copyright 1999-2002 by Donald Becker.
  15. This software may be used and distributed according to the terms of
  16. the GNU General Public License (GPL), incorporated herein by reference.
  17. Drivers based on or derived from this code fall under the GPL and must
  18. retain the authorship, copyright and license notice. This file is not
  19. a complete program and may only be used when the entire operating
  20. system is licensed under the GPL. License for under other terms may be
  21. available. Contact the original author for details.
  22. The original author may be reached as becker@scyld.com, or at
  23. Scyld Computing Corporation
  24. 410 Severn Ave., Suite 210
  25. Annapolis MD 21403
  26. Support information and updates available at
  27. http://www.scyld.com/network/netsemi.html
  28. Datasheets available from:
  29. http://www.national.com/pf/DP/DP83820.html
  30. http://www.national.com/pf/DP/DP83821.html
  31. */
  32. /* Revision History
  33. * October 2002 mar 1.0
  34. * Initial U-Boot Release.
  35. * Tested with Netgear GA622T (83820)
  36. * and SMC9452TX (83821)
  37. * NOTE: custom boards with these chips may (likely) require
  38. * a programmed EEPROM device (if present) in order to work
  39. * correctly.
  40. */
  41. /* Includes */
  42. #include <common.h>
  43. #include <log.h>
  44. #include <malloc.h>
  45. #include <net.h>
  46. #include <netdev.h>
  47. #include <asm/io.h>
  48. #include <pci.h>
  49. #include <linux/delay.h>
  50. /* defines */
  51. #define DSIZE 0x00000FFF
  52. #define CRC_SIZE 4
  53. #define TOUT_LOOP 500000
  54. #define TX_BUF_SIZE 1536
  55. #define RX_BUF_SIZE 1536
  56. #define NUM_RX_DESC 4 /* Number of Rx descriptor registers. */
  57. enum register_offsets {
  58. ChipCmd = 0x00,
  59. ChipConfig = 0x04,
  60. EECtrl = 0x08,
  61. IntrMask = 0x14,
  62. IntrEnable = 0x18,
  63. TxRingPtr = 0x20,
  64. TxRingPtrHi = 0x24,
  65. TxConfig = 0x28,
  66. RxRingPtr = 0x30,
  67. RxRingPtrHi = 0x34,
  68. RxConfig = 0x38,
  69. PriQueue = 0x3C,
  70. RxFilterAddr = 0x48,
  71. RxFilterData = 0x4C,
  72. ClkRun = 0xCC,
  73. PCIPM = 0x44,
  74. };
  75. enum ChipCmdBits {
  76. ChipReset = 0x100,
  77. RxReset = 0x20,
  78. TxReset = 0x10,
  79. RxOff = 0x08,
  80. RxOn = 0x04,
  81. TxOff = 0x02,
  82. TxOn = 0x01
  83. };
  84. enum ChipConfigBits {
  85. LinkSts = 0x80000000,
  86. GigSpeed = 0x40000000,
  87. HundSpeed = 0x20000000,
  88. FullDuplex = 0x10000000,
  89. TBIEn = 0x01000000,
  90. Mode1000 = 0x00400000,
  91. T64En = 0x00004000,
  92. D64En = 0x00001000,
  93. M64En = 0x00000800,
  94. PhyRst = 0x00000400,
  95. PhyDis = 0x00000200,
  96. ExtStEn = 0x00000100,
  97. BEMode = 0x00000001,
  98. };
  99. #define SpeedStatus_Polarity ( GigSpeed | HundSpeed | FullDuplex)
  100. enum TxConfig_bits {
  101. TxDrthMask = 0x000000ff,
  102. TxFlthMask = 0x0000ff00,
  103. TxMxdmaMask = 0x00700000,
  104. TxMxdma_8 = 0x00100000,
  105. TxMxdma_16 = 0x00200000,
  106. TxMxdma_32 = 0x00300000,
  107. TxMxdma_64 = 0x00400000,
  108. TxMxdma_128 = 0x00500000,
  109. TxMxdma_256 = 0x00600000,
  110. TxMxdma_512 = 0x00700000,
  111. TxMxdma_1024 = 0x00000000,
  112. TxCollRetry = 0x00800000,
  113. TxAutoPad = 0x10000000,
  114. TxMacLoop = 0x20000000,
  115. TxHeartIgn = 0x40000000,
  116. TxCarrierIgn = 0x80000000
  117. };
  118. enum RxConfig_bits {
  119. RxDrthMask = 0x0000003e,
  120. RxMxdmaMask = 0x00700000,
  121. RxMxdma_8 = 0x00100000,
  122. RxMxdma_16 = 0x00200000,
  123. RxMxdma_32 = 0x00300000,
  124. RxMxdma_64 = 0x00400000,
  125. RxMxdma_128 = 0x00500000,
  126. RxMxdma_256 = 0x00600000,
  127. RxMxdma_512 = 0x00700000,
  128. RxMxdma_1024 = 0x00000000,
  129. RxAcceptLenErr = 0x04000000,
  130. RxAcceptLong = 0x08000000,
  131. RxAcceptTx = 0x10000000,
  132. RxStripCRC = 0x20000000,
  133. RxAcceptRunt = 0x40000000,
  134. RxAcceptErr = 0x80000000,
  135. };
  136. /* Bits in the RxMode register. */
  137. enum rx_mode_bits {
  138. RxFilterEnable = 0x80000000,
  139. AcceptAllBroadcast = 0x40000000,
  140. AcceptAllMulticast = 0x20000000,
  141. AcceptAllUnicast = 0x10000000,
  142. AcceptPerfectMatch = 0x08000000,
  143. };
  144. typedef struct _BufferDesc {
  145. u32 link;
  146. u32 bufptr;
  147. vu_long cmdsts;
  148. u32 extsts; /*not used here */
  149. } BufferDesc;
  150. /* Bits in network_desc.status */
  151. enum desc_status_bits {
  152. DescOwn = 0x80000000, DescMore = 0x40000000, DescIntr = 0x20000000,
  153. DescNoCRC = 0x10000000, DescPktOK = 0x08000000,
  154. DescSizeMask = 0xfff,
  155. DescTxAbort = 0x04000000, DescTxFIFO = 0x02000000,
  156. DescTxCarrier = 0x01000000, DescTxDefer = 0x00800000,
  157. DescTxExcDefer = 0x00400000, DescTxOOWCol = 0x00200000,
  158. DescTxExcColl = 0x00100000, DescTxCollCount = 0x000f0000,
  159. DescRxAbort = 0x04000000, DescRxOver = 0x02000000,
  160. DescRxDest = 0x01800000, DescRxLong = 0x00400000,
  161. DescRxRunt = 0x00200000, DescRxInvalid = 0x00100000,
  162. DescRxCRC = 0x00080000, DescRxAlign = 0x00040000,
  163. DescRxLoop = 0x00020000, DesRxColl = 0x00010000,
  164. };
  165. /* Bits in MEAR */
  166. enum mii_reg_bits {
  167. MDIO_ShiftClk = 0x0040,
  168. MDIO_EnbOutput = 0x0020,
  169. MDIO_Data = 0x0010,
  170. };
  171. /* PHY Register offsets. */
  172. enum phy_reg_offsets {
  173. BMCR = 0x00,
  174. BMSR = 0x01,
  175. PHYIDR1 = 0x02,
  176. PHYIDR2 = 0x03,
  177. ANAR = 0x04,
  178. KTCR = 0x09,
  179. };
  180. /* basic mode control register bits */
  181. enum bmcr_bits {
  182. Bmcr_Reset = 0x8000,
  183. Bmcr_Loop = 0x4000,
  184. Bmcr_Speed0 = 0x2000,
  185. Bmcr_AutoNegEn = 0x1000, /*if set ignores Duplex, Speed[01] */
  186. Bmcr_RstAutoNeg = 0x0200,
  187. Bmcr_Duplex = 0x0100,
  188. Bmcr_Speed1 = 0x0040,
  189. Bmcr_Force10H = 0x0000,
  190. Bmcr_Force10F = 0x0100,
  191. Bmcr_Force100H = 0x2000,
  192. Bmcr_Force100F = 0x2100,
  193. Bmcr_Force1000H = 0x0040,
  194. Bmcr_Force1000F = 0x0140,
  195. };
  196. /* auto negotiation advertisement register */
  197. enum anar_bits {
  198. anar_adv_100F = 0x0100,
  199. anar_adv_100H = 0x0080,
  200. anar_adv_10F = 0x0040,
  201. anar_adv_10H = 0x0020,
  202. anar_ieee_8023 = 0x0001,
  203. };
  204. /* 1K-base T control register */
  205. enum ktcr_bits {
  206. ktcr_adv_1000H = 0x0100,
  207. ktcr_adv_1000F = 0x0200,
  208. };
  209. /* Globals */
  210. static u32 SavedClkRun;
  211. static unsigned int cur_rx;
  212. static unsigned int rx_config;
  213. static unsigned int tx_config;
  214. /* Note: transmit and receive buffers and descriptors must be
  215. long long word aligned */
  216. static BufferDesc txd __attribute__ ((aligned(8)));
  217. static BufferDesc rxd[NUM_RX_DESC] __attribute__ ((aligned(8)));
  218. static unsigned char txb[TX_BUF_SIZE] __attribute__ ((aligned(8)));
  219. static unsigned char rxb[NUM_RX_DESC * RX_BUF_SIZE]
  220. __attribute__ ((aligned(8)));
  221. /* Function Prototypes */
  222. static int mdio_read(struct eth_device *dev, int phy_id, int addr);
  223. static void mdio_write(struct eth_device *dev, int phy_id, int addr, int value);
  224. static void mdio_sync(struct eth_device *dev, u32 offset);
  225. static int ns8382x_init(struct eth_device *dev, struct bd_info * bis);
  226. static void ns8382x_reset(struct eth_device *dev);
  227. static void ns8382x_init_rxfilter(struct eth_device *dev);
  228. static void ns8382x_init_txd(struct eth_device *dev);
  229. static void ns8382x_init_rxd(struct eth_device *dev);
  230. static void ns8382x_set_rx_mode(struct eth_device *dev);
  231. static void ns8382x_check_duplex(struct eth_device *dev);
  232. static int ns8382x_send(struct eth_device *dev, void *packet, int length);
  233. static int ns8382x_poll(struct eth_device *dev);
  234. static void ns8382x_disable(struct eth_device *dev);
  235. static struct pci_device_id supported[] = {
  236. {PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83820},
  237. {}
  238. };
  239. #define bus_to_phys(a) pci_mem_to_phys((pci_dev_t)dev->priv, a)
  240. #define phys_to_bus(a) pci_phys_to_mem((pci_dev_t)dev->priv, a)
  241. static inline int
  242. INW(struct eth_device *dev, u_long addr)
  243. {
  244. return le16_to_cpu(*(vu_short *) (addr + dev->iobase));
  245. }
  246. static int
  247. INL(struct eth_device *dev, u_long addr)
  248. {
  249. return le32_to_cpu(*(vu_long *) (addr + dev->iobase));
  250. }
  251. static inline void
  252. OUTW(struct eth_device *dev, int command, u_long addr)
  253. {
  254. *(vu_short *) ((addr + dev->iobase)) = cpu_to_le16(command);
  255. }
  256. static inline void
  257. OUTL(struct eth_device *dev, int command, u_long addr)
  258. {
  259. *(vu_long *) ((addr + dev->iobase)) = cpu_to_le32(command);
  260. }
  261. /* Function: ns8382x_initialize
  262. * Description: Retrieves the MAC address of the card, and sets up some
  263. * globals required by other routines, and initializes the NIC, making it
  264. * ready to send and receive packets.
  265. * Side effects: initializes ns8382xs, ready to receive packets.
  266. * Returns: int: number of cards found
  267. */
  268. int
  269. ns8382x_initialize(struct bd_info * bis)
  270. {
  271. pci_dev_t devno;
  272. int card_number = 0;
  273. struct eth_device *dev;
  274. u32 iobase, status;
  275. int i, idx = 0;
  276. u32 phyAddress;
  277. u32 tmp;
  278. u32 chip_config;
  279. while (1) { /* Find PCI device(s) */
  280. if ((devno = pci_find_devices(supported, idx++)) < 0)
  281. break;
  282. pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
  283. iobase &= ~0x3; /* 1: unused and 0:I/O Space Indicator */
  284. debug("ns8382x: NatSemi dp8382x @ 0x%x\n", iobase);
  285. pci_write_config_dword(devno, PCI_COMMAND,
  286. PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
  287. /* Check if I/O accesses and Bus Mastering are enabled. */
  288. pci_read_config_dword(devno, PCI_COMMAND, &status);
  289. if (!(status & PCI_COMMAND_MEMORY)) {
  290. printf("Error: Can not enable MEM access.\n");
  291. continue;
  292. } else if (!(status & PCI_COMMAND_MASTER)) {
  293. printf("Error: Can not enable Bus Mastering.\n");
  294. continue;
  295. }
  296. dev = (struct eth_device *) malloc(sizeof *dev);
  297. if (!dev) {
  298. printf("ns8382x: Can not allocate memory\n");
  299. break;
  300. }
  301. memset(dev, 0, sizeof(*dev));
  302. sprintf(dev->name, "dp8382x#%d", card_number);
  303. dev->iobase = bus_to_phys(iobase);
  304. dev->priv = (void *) devno;
  305. dev->init = ns8382x_init;
  306. dev->halt = ns8382x_disable;
  307. dev->send = ns8382x_send;
  308. dev->recv = ns8382x_poll;
  309. /* ns8382x has a non-standard PM control register
  310. * in PCI config space. Some boards apparently need
  311. * to be brought to D0 in this manner. */
  312. pci_read_config_dword(devno, PCIPM, &tmp);
  313. if (tmp & (0x03 | 0x100)) { /* D0 state, disable PME assertion */
  314. u32 newtmp = tmp & ~(0x03 | 0x100);
  315. pci_write_config_dword(devno, PCIPM, newtmp);
  316. }
  317. /* get MAC address */
  318. for (i = 0; i < 3; i++) {
  319. u32 data;
  320. char *mac = (char *)&dev->enetaddr[i * 2];
  321. OUTL(dev, i * 2, RxFilterAddr);
  322. data = INL(dev, RxFilterData);
  323. *mac++ = data;
  324. *mac++ = data >> 8;
  325. }
  326. /* get PHY address, can't be zero */
  327. for (phyAddress = 1; phyAddress < 32; phyAddress++) {
  328. u32 rev, phy1;
  329. phy1 = mdio_read(dev, phyAddress, PHYIDR1);
  330. if (phy1 == 0x2000) { /*check for 83861/91 */
  331. rev = mdio_read(dev, phyAddress, PHYIDR2);
  332. if ((rev & ~(0x000f)) == 0x00005c50 ||
  333. (rev & ~(0x000f)) == 0x00005c60) {
  334. debug("phy rev is %x\n", rev);
  335. debug("phy address is %x\n",
  336. phyAddress);
  337. break;
  338. }
  339. }
  340. }
  341. /* set phy to autonegotiate && advertise everything */
  342. mdio_write(dev, phyAddress, KTCR,
  343. (ktcr_adv_1000H | ktcr_adv_1000F));
  344. mdio_write(dev, phyAddress, ANAR,
  345. (anar_adv_100F | anar_adv_100H | anar_adv_10H |
  346. anar_adv_10F | anar_ieee_8023));
  347. mdio_write(dev, phyAddress, BMCR, 0x0); /*restore */
  348. mdio_write(dev, phyAddress, BMCR,
  349. (Bmcr_AutoNegEn | Bmcr_RstAutoNeg));
  350. /* Reset the chip to erase any previous misconfiguration. */
  351. OUTL(dev, (ChipReset), ChipCmd);
  352. chip_config = INL(dev, ChipConfig);
  353. /* reset the phy */
  354. OUTL(dev, (chip_config | PhyRst), ChipConfig);
  355. /* power up and initialize transceiver */
  356. OUTL(dev, (chip_config & ~(PhyDis)), ChipConfig);
  357. mdio_sync(dev, EECtrl);
  358. {
  359. u32 chpcfg =
  360. INL(dev, ChipConfig) ^ SpeedStatus_Polarity;
  361. debug("%s: Transceiver 10%s %s duplex.\n", dev->name,
  362. (chpcfg & GigSpeed) ? "00" : (chpcfg & HundSpeed)
  363. ? "0" : "",
  364. chpcfg & FullDuplex ? "full" : "half");
  365. debug("%s: %02x:%02x:%02x:%02x:%02x:%02x\n", dev->name,
  366. dev->enetaddr[0], dev->enetaddr[1],
  367. dev->enetaddr[2], dev->enetaddr[3],
  368. dev->enetaddr[4], dev->enetaddr[5]);
  369. }
  370. /* Disable PME:
  371. * The PME bit is initialized from the EEPROM contents.
  372. * PCI cards probably have PME disabled, but motherboard
  373. * implementations may have PME set to enable WakeOnLan.
  374. * With PME set the chip will scan incoming packets but
  375. * nothing will be written to memory. */
  376. SavedClkRun = INL(dev, ClkRun);
  377. OUTL(dev, SavedClkRun & ~0x100, ClkRun);
  378. eth_register(dev);
  379. card_number++;
  380. pci_write_config_byte(devno, PCI_LATENCY_TIMER, 0x60);
  381. udelay(10 * 1000);
  382. }
  383. return card_number;
  384. }
  385. /* MII transceiver control section.
  386. Read and write MII registers using software-generated serial MDIO
  387. protocol. See the MII specifications or DP83840A data sheet for details.
  388. The maximum data clock rate is 2.5 MHz. To meet minimum timing we
  389. must flush writes to the PCI bus with a PCI read. */
  390. #define mdio_delay(mdio_addr) INL(dev, mdio_addr)
  391. #define MDIO_EnbIn (0)
  392. #define MDIO_WRITE0 (MDIO_EnbOutput)
  393. #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
  394. /* Generate the preamble required for initial synchronization and
  395. a few older transceivers. */
  396. static void
  397. mdio_sync(struct eth_device *dev, u32 offset)
  398. {
  399. int bits = 32;
  400. /* Establish sync by sending at least 32 logic ones. */
  401. while (--bits >= 0) {
  402. OUTL(dev, MDIO_WRITE1, offset);
  403. mdio_delay(offset);
  404. OUTL(dev, MDIO_WRITE1 | MDIO_ShiftClk, offset);
  405. mdio_delay(offset);
  406. }
  407. }
  408. static int
  409. mdio_read(struct eth_device *dev, int phy_id, int addr)
  410. {
  411. int mii_cmd = (0xf6 << 10) | (phy_id << 5) | addr;
  412. int i, retval = 0;
  413. /* Shift the read command bits out. */
  414. for (i = 15; i >= 0; i--) {
  415. int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
  416. OUTL(dev, dataval, EECtrl);
  417. mdio_delay(EECtrl);
  418. OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
  419. mdio_delay(EECtrl);
  420. }
  421. /* Read the two transition, 16 data, and wire-idle bits. */
  422. for (i = 19; i > 0; i--) {
  423. OUTL(dev, MDIO_EnbIn, EECtrl);
  424. mdio_delay(EECtrl);
  425. retval =
  426. (retval << 1) | ((INL(dev, EECtrl) & MDIO_Data) ? 1 : 0);
  427. OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
  428. mdio_delay(EECtrl);
  429. }
  430. return (retval >> 1) & 0xffff;
  431. }
  432. static void
  433. mdio_write(struct eth_device *dev, int phy_id, int addr, int value)
  434. {
  435. int mii_cmd = (0x5002 << 16) | (phy_id << 23) | (addr << 18) | value;
  436. int i;
  437. /* Shift the command bits out. */
  438. for (i = 31; i >= 0; i--) {
  439. int dataval = (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
  440. OUTL(dev, dataval, EECtrl);
  441. mdio_delay(EECtrl);
  442. OUTL(dev, dataval | MDIO_ShiftClk, EECtrl);
  443. mdio_delay(EECtrl);
  444. }
  445. /* Clear out extra bits. */
  446. for (i = 2; i > 0; i--) {
  447. OUTL(dev, MDIO_EnbIn, EECtrl);
  448. mdio_delay(EECtrl);
  449. OUTL(dev, MDIO_EnbIn | MDIO_ShiftClk, EECtrl);
  450. mdio_delay(EECtrl);
  451. }
  452. return;
  453. }
  454. /* Function: ns8382x_init
  455. * Description: resets the ethernet controller chip and configures
  456. * registers and data structures required for sending and receiving packets.
  457. * Arguments: struct eth_device *dev: NIC data structure
  458. * returns: int.
  459. */
  460. static int
  461. ns8382x_init(struct eth_device *dev, struct bd_info * bis)
  462. {
  463. u32 config;
  464. ns8382x_reset(dev);
  465. /* Disable PME:
  466. * The PME bit is initialized from the EEPROM contents.
  467. * PCI cards probably have PME disabled, but motherboard
  468. * implementations may have PME set to enable WakeOnLan.
  469. * With PME set the chip will scan incoming packets but
  470. * nothing will be written to memory. */
  471. OUTL(dev, SavedClkRun & ~0x100, ClkRun);
  472. ns8382x_init_rxfilter(dev);
  473. ns8382x_init_txd(dev);
  474. ns8382x_init_rxd(dev);
  475. /*set up ChipConfig */
  476. config = INL(dev, ChipConfig);
  477. /*turn off 64 bit ops && Ten-bit interface
  478. * && big-endian mode && extended status */
  479. config &= ~(TBIEn | Mode1000 | T64En | D64En | M64En | BEMode | PhyDis | ExtStEn);
  480. OUTL(dev, config, ChipConfig);
  481. /* Configure the PCI bus bursts and FIFO thresholds. */
  482. tx_config = TxCarrierIgn | TxHeartIgn | TxAutoPad
  483. | TxCollRetry | TxMxdma_1024 | (0x1002);
  484. rx_config = RxMxdma_1024 | 0x20;
  485. debug("%s: Setting TxConfig Register %#08X\n", dev->name, tx_config);
  486. debug("%s: Setting RxConfig Register %#08X\n", dev->name, rx_config);
  487. OUTL(dev, tx_config, TxConfig);
  488. OUTL(dev, rx_config, RxConfig);
  489. /*turn off priority queueing */
  490. OUTL(dev, 0x0, PriQueue);
  491. ns8382x_check_duplex(dev);
  492. ns8382x_set_rx_mode(dev);
  493. OUTL(dev, (RxOn | TxOn), ChipCmd);
  494. return 1;
  495. }
  496. /* Function: ns8382x_reset
  497. * Description: soft resets the controller chip
  498. * Arguments: struct eth_device *dev: NIC data structure
  499. * Returns: void.
  500. */
  501. static void
  502. ns8382x_reset(struct eth_device *dev)
  503. {
  504. OUTL(dev, ChipReset, ChipCmd);
  505. while (INL(dev, ChipCmd))
  506. /*wait until done */ ;
  507. OUTL(dev, 0, IntrMask);
  508. OUTL(dev, 0, IntrEnable);
  509. }
  510. /* Function: ns8382x_init_rxfilter
  511. * Description: sets receive filter address to our MAC address
  512. * Arguments: struct eth_device *dev: NIC data structure
  513. * returns: void.
  514. */
  515. static void
  516. ns8382x_init_rxfilter(struct eth_device *dev)
  517. {
  518. int i;
  519. for (i = 0; i < ETH_ALEN; i += 2) {
  520. OUTL(dev, i, RxFilterAddr);
  521. OUTW(dev, dev->enetaddr[i] + (dev->enetaddr[i + 1] << 8),
  522. RxFilterData);
  523. }
  524. }
  525. /* Function: ns8382x_init_txd
  526. * Description: initializes the Tx descriptor
  527. * Arguments: struct eth_device *dev: NIC data structure
  528. * returns: void.
  529. */
  530. static void
  531. ns8382x_init_txd(struct eth_device *dev)
  532. {
  533. txd.link = (u32) 0;
  534. txd.bufptr = cpu_to_le32((u32) & txb[0]);
  535. txd.cmdsts = (u32) 0;
  536. txd.extsts = (u32) 0;
  537. OUTL(dev, 0x0, TxRingPtrHi);
  538. OUTL(dev, phys_to_bus((u32)&txd), TxRingPtr);
  539. debug("ns8382x_init_txd: TX descriptor register loaded with: %#08X (&txd: %p)\n",
  540. INL(dev, TxRingPtr), &txd);
  541. }
  542. /* Function: ns8382x_init_rxd
  543. * Description: initializes the Rx descriptor ring
  544. * Arguments: struct eth_device *dev: NIC data structure
  545. * Returns: void.
  546. */
  547. static void
  548. ns8382x_init_rxd(struct eth_device *dev)
  549. {
  550. int i;
  551. OUTL(dev, 0x0, RxRingPtrHi);
  552. cur_rx = 0;
  553. for (i = 0; i < NUM_RX_DESC; i++) {
  554. rxd[i].link =
  555. cpu_to_le32((i + 1 <
  556. NUM_RX_DESC) ? (u32) & rxd[i +
  557. 1] : (u32) &
  558. rxd[0]);
  559. rxd[i].extsts = cpu_to_le32((u32) 0x0);
  560. rxd[i].cmdsts = cpu_to_le32((u32) RX_BUF_SIZE);
  561. rxd[i].bufptr = cpu_to_le32((u32) & rxb[i * RX_BUF_SIZE]);
  562. debug
  563. ("ns8382x_init_rxd: rxd[%d]=%p link=%X cmdsts=%X bufptr=%X\n",
  564. i, &rxd[i], le32_to_cpu(rxd[i].link),
  565. le32_to_cpu(rxd[i].cmdsts), le32_to_cpu(rxd[i].bufptr));
  566. }
  567. OUTL(dev, phys_to_bus((u32) & rxd), RxRingPtr);
  568. debug("ns8382x_init_rxd: RX descriptor register loaded with: %X\n",
  569. INL(dev, RxRingPtr));
  570. }
  571. /* Function: ns8382x_set_rx_mode
  572. * Description:
  573. * sets the receive mode to accept all broadcast packets and packets
  574. * with our MAC address, and reject all multicast packets.
  575. * Arguments: struct eth_device *dev: NIC data structure
  576. * Returns: void.
  577. */
  578. static void
  579. ns8382x_set_rx_mode(struct eth_device *dev)
  580. {
  581. u32 rx_mode = 0x0;
  582. /*spec says RxFilterEnable has to be 0 for rest of
  583. * this stuff to be properly configured. Linux driver
  584. * seems to support this*/
  585. /* OUTL(dev, rx_mode, RxFilterAddr);*/
  586. rx_mode = (RxFilterEnable | AcceptAllBroadcast | AcceptPerfectMatch);
  587. OUTL(dev, rx_mode, RxFilterAddr);
  588. printf("ns8382x_set_rx_mode: set to %X\n", rx_mode);
  589. /*now we turn RxFilterEnable back on */
  590. /*rx_mode |= RxFilterEnable;
  591. OUTL(dev, rx_mode, RxFilterAddr);*/
  592. }
  593. static void
  594. ns8382x_check_duplex(struct eth_device *dev)
  595. {
  596. int gig = 0;
  597. int hun = 0;
  598. int duplex = 0;
  599. int config = (INL(dev, ChipConfig) ^ SpeedStatus_Polarity);
  600. duplex = (config & FullDuplex) ? 1 : 0;
  601. gig = (config & GigSpeed) ? 1 : 0;
  602. hun = (config & HundSpeed) ? 1 : 0;
  603. debug("%s: Setting 10%s %s-duplex based on negotiated link"
  604. " capability.\n", dev->name, (gig) ? "00" : (hun) ? "0" : "",
  605. duplex ? "full" : "half");
  606. if (duplex) {
  607. rx_config |= RxAcceptTx;
  608. tx_config |= (TxCarrierIgn | TxHeartIgn);
  609. } else {
  610. rx_config &= ~RxAcceptTx;
  611. tx_config &= ~(TxCarrierIgn | TxHeartIgn);
  612. }
  613. debug("%s: Resetting TxConfig Register %#08X\n", dev->name, tx_config);
  614. debug("%s: Resetting RxConfig Register %#08X\n", dev->name, rx_config);
  615. OUTL(dev, tx_config, TxConfig);
  616. OUTL(dev, rx_config, RxConfig);
  617. /*if speed is 10 or 100, remove MODE1000,
  618. * if it's 1000, then set it */
  619. config = INL(dev, ChipConfig);
  620. if (gig)
  621. config |= Mode1000;
  622. else
  623. config &= ~Mode1000;
  624. debug("%s: %setting Mode1000\n", dev->name, (gig) ? "S" : "Uns");
  625. OUTL(dev, config, ChipConfig);
  626. }
  627. /* Function: ns8382x_send
  628. * Description: transmits a packet and waits for completion or timeout.
  629. * Returns: void. */
  630. static int ns8382x_send(struct eth_device *dev, void *packet, int length)
  631. {
  632. u32 i, status = 0;
  633. vu_long tx_stat = 0;
  634. /* Stop the transmitter */
  635. OUTL(dev, TxOff, ChipCmd);
  636. debug("ns8382x_send: sending %d bytes\n", (int)length);
  637. /* set the transmit buffer descriptor and enable Transmit State Machine */
  638. txd.link = cpu_to_le32(0x0);
  639. txd.bufptr = cpu_to_le32(phys_to_bus((u32)packet));
  640. txd.extsts = cpu_to_le32(0x0);
  641. txd.cmdsts = cpu_to_le32(DescOwn | length);
  642. /* load Transmit Descriptor Register */
  643. OUTL(dev, phys_to_bus((u32) & txd), TxRingPtr);
  644. debug("ns8382x_send: TX descriptor register loaded with: %#08X\n",
  645. INL(dev, TxRingPtr));
  646. debug("\ttxd.link:%X\tbufp:%X\texsts:%X\tcmdsts:%X\n",
  647. le32_to_cpu(txd.link), le32_to_cpu(txd.bufptr),
  648. le32_to_cpu(txd.extsts), le32_to_cpu(txd.cmdsts));
  649. /* restart the transmitter */
  650. OUTL(dev, TxOn, ChipCmd);
  651. for (i = 0; (tx_stat = le32_to_cpu(txd.cmdsts)) & DescOwn; i++) {
  652. if (i >= TOUT_LOOP) {
  653. printf ("%s: tx error buffer not ready: txd.cmdsts %#lX\n",
  654. dev->name, tx_stat);
  655. goto Done;
  656. }
  657. }
  658. if (!(tx_stat & DescPktOK)) {
  659. printf("ns8382x_send: Transmit error, Tx status %lX.\n", tx_stat);
  660. goto Done;
  661. }
  662. debug("ns8382x_send: tx_stat: %#08lX\n", tx_stat);
  663. status = 1;
  664. Done:
  665. return status;
  666. }
  667. /* Function: ns8382x_poll
  668. * Description: checks for a received packet and returns it if found.
  669. * Arguments: struct eth_device *dev: NIC data structure
  670. * Returns: 1 if packet was received.
  671. * 0 if no packet was received.
  672. * Side effects:
  673. * Returns (copies) the packet to the array dev->packet.
  674. * Returns the length of the packet.
  675. */
  676. static int
  677. ns8382x_poll(struct eth_device *dev)
  678. {
  679. int retstat = 0;
  680. int length = 0;
  681. vu_long rx_status = le32_to_cpu(rxd[cur_rx].cmdsts);
  682. if (!(rx_status & (u32) DescOwn))
  683. return retstat;
  684. debug("ns8382x_poll: got a packet: cur_rx:%u, status:%lx\n",
  685. cur_rx, rx_status);
  686. length = (rx_status & DSIZE) - CRC_SIZE;
  687. if ((rx_status & (DescMore | DescPktOK | DescRxLong)) != DescPktOK) {
  688. /* corrupted packet received */
  689. printf("ns8382x_poll: Corrupted packet, status:%lx\n",
  690. rx_status);
  691. retstat = 0;
  692. } else {
  693. /* give packet to higher level routine */
  694. net_process_received_packet((rxb + cur_rx * RX_BUF_SIZE),
  695. length);
  696. retstat = 1;
  697. }
  698. /* return the descriptor and buffer to receive ring */
  699. rxd[cur_rx].cmdsts = cpu_to_le32(RX_BUF_SIZE);
  700. rxd[cur_rx].bufptr = cpu_to_le32((u32) & rxb[cur_rx * RX_BUF_SIZE]);
  701. if (++cur_rx == NUM_RX_DESC)
  702. cur_rx = 0;
  703. /* re-enable the potentially idle receive state machine */
  704. OUTL(dev, RxOn, ChipCmd);
  705. return retstat;
  706. }
  707. /* Function: ns8382x_disable
  708. * Description: Turns off interrupts and stops Tx and Rx engines
  709. * Arguments: struct eth_device *dev: NIC data structure
  710. * Returns: void.
  711. */
  712. static void
  713. ns8382x_disable(struct eth_device *dev)
  714. {
  715. /* Disable interrupts using the mask. */
  716. OUTL(dev, 0, IntrMask);
  717. OUTL(dev, 0, IntrEnable);
  718. /* Stop the chip's Tx and Rx processes. */
  719. OUTL(dev, (RxOff | TxOff), ChipCmd);
  720. /* Restore PME enable bit */
  721. OUTL(dev, SavedClkRun, ClkRun);
  722. }