mvgbe.c 26 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009
  4. * Marvell Semiconductor <www.marvell.com>
  5. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  6. *
  7. * (C) Copyright 2003
  8. * Ingo Assmus <ingo.assmus@keymile.com>
  9. *
  10. * based on - Driver for MV64360X ethernet ports
  11. * Copyright (C) 2002 rabeeh@galileo.co.il
  12. */
  13. #include <common.h>
  14. #include <dm.h>
  15. #include <log.h>
  16. #include <net.h>
  17. #include <malloc.h>
  18. #include <miiphy.h>
  19. #include <wait_bit.h>
  20. #include <asm/io.h>
  21. #include <linux/delay.h>
  22. #include <linux/errno.h>
  23. #include <asm/types.h>
  24. #include <asm/system.h>
  25. #include <asm/byteorder.h>
  26. #include <asm/arch/cpu.h>
  27. #if defined(CONFIG_ARCH_KIRKWOOD)
  28. #include <asm/arch/soc.h>
  29. #elif defined(CONFIG_ARCH_ORION5X)
  30. #include <asm/arch/orion5x.h>
  31. #endif
  32. #include "mvgbe.h"
  33. DECLARE_GLOBAL_DATA_PTR;
  34. #ifndef CONFIG_MVGBE_PORTS
  35. # define CONFIG_MVGBE_PORTS {0, 0}
  36. #endif
  37. #define MV_PHY_ADR_REQUEST 0xee
  38. #define MVGBE_SMI_REG (((struct mvgbe_registers *)MVGBE0_BASE)->smi)
  39. #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  40. static int smi_wait_ready(struct mvgbe_device *dmvgbe)
  41. {
  42. int ret;
  43. ret = wait_for_bit_le32(&MVGBE_SMI_REG, MVGBE_PHY_SMI_BUSY_MASK, false,
  44. MVGBE_PHY_SMI_TIMEOUT_MS, false);
  45. if (ret) {
  46. printf("Error: SMI busy timeout\n");
  47. return ret;
  48. }
  49. return 0;
  50. }
  51. static int __mvgbe_mdio_read(struct mvgbe_device *dmvgbe, int phy_adr,
  52. int devad, int reg_ofs)
  53. {
  54. struct mvgbe_registers *regs = dmvgbe->regs;
  55. u32 smi_reg;
  56. u32 timeout;
  57. u16 data = 0;
  58. /* Phyadr read request */
  59. if (phy_adr == MV_PHY_ADR_REQUEST &&
  60. reg_ofs == MV_PHY_ADR_REQUEST) {
  61. /* */
  62. data = (u16) (MVGBE_REG_RD(regs->phyadr) & PHYADR_MASK);
  63. return data;
  64. }
  65. /* check parameters */
  66. if (phy_adr > PHYADR_MASK) {
  67. printf("Err..(%s) Invalid PHY address %d\n",
  68. __func__, phy_adr);
  69. return -EFAULT;
  70. }
  71. if (reg_ofs > PHYREG_MASK) {
  72. printf("Err..(%s) Invalid register offset %d\n",
  73. __func__, reg_ofs);
  74. return -EFAULT;
  75. }
  76. /* wait till the SMI is not busy */
  77. if (smi_wait_ready(dmvgbe) < 0)
  78. return -EFAULT;
  79. /* fill the phy address and regiser offset and read opcode */
  80. smi_reg = (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
  81. | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS)
  82. | MVGBE_PHY_SMI_OPCODE_READ;
  83. /* write the smi register */
  84. MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
  85. /*wait till read value is ready */
  86. timeout = MVGBE_PHY_SMI_TIMEOUT;
  87. do {
  88. /* read smi register */
  89. smi_reg = MVGBE_REG_RD(MVGBE_SMI_REG);
  90. if (timeout-- == 0) {
  91. printf("Err..(%s) SMI read ready timeout\n",
  92. __func__);
  93. return -EFAULT;
  94. }
  95. } while (!(smi_reg & MVGBE_PHY_SMI_READ_VALID_MASK));
  96. /* Wait for the data to update in the SMI register */
  97. for (timeout = 0; timeout < MVGBE_PHY_SMI_TIMEOUT; timeout++)
  98. ;
  99. data = (u16) (MVGBE_REG_RD(MVGBE_SMI_REG) & MVGBE_PHY_SMI_DATA_MASK);
  100. debug("%s:(adr %d, off %d) value= %04x\n", __func__, phy_adr, reg_ofs,
  101. data);
  102. return data;
  103. }
  104. /*
  105. * smi_reg_read - miiphy_read callback function.
  106. *
  107. * Returns 16bit phy register value, or -EFAULT on error
  108. */
  109. static int smi_reg_read(struct mii_dev *bus, int phy_adr, int devad,
  110. int reg_ofs)
  111. {
  112. #ifdef CONFIG_DM_ETH
  113. struct mvgbe_device *dmvgbe = bus->priv;
  114. #else
  115. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  116. struct mvgbe_device *dmvgbe = to_mvgbe(dev);
  117. #endif
  118. return __mvgbe_mdio_read(dmvgbe, phy_adr, devad, reg_ofs);
  119. }
  120. static int __mvgbe_mdio_write(struct mvgbe_device *dmvgbe, int phy_adr,
  121. int devad, int reg_ofs, u16 data)
  122. {
  123. struct mvgbe_registers *regs = dmvgbe->regs;
  124. u32 smi_reg;
  125. /* Phyadr write request*/
  126. if (phy_adr == MV_PHY_ADR_REQUEST &&
  127. reg_ofs == MV_PHY_ADR_REQUEST) {
  128. MVGBE_REG_WR(regs->phyadr, data);
  129. return 0;
  130. }
  131. /* check parameters */
  132. if (phy_adr > PHYADR_MASK) {
  133. printf("Err..(%s) Invalid phy address\n", __func__);
  134. return -EINVAL;
  135. }
  136. if (reg_ofs > PHYREG_MASK) {
  137. printf("Err..(%s) Invalid register offset\n", __func__);
  138. return -EFAULT;
  139. }
  140. /* wait till the SMI is not busy */
  141. if (smi_wait_ready(dmvgbe) < 0)
  142. return -EFAULT;
  143. /* fill the phy addr and reg offset and write opcode and data */
  144. smi_reg = (data << MVGBE_PHY_SMI_DATA_OFFS);
  145. smi_reg |= (phy_adr << MVGBE_PHY_SMI_DEV_ADDR_OFFS)
  146. | (reg_ofs << MVGBE_SMI_REG_ADDR_OFFS);
  147. smi_reg &= ~MVGBE_PHY_SMI_OPCODE_READ;
  148. /* write the smi register */
  149. MVGBE_REG_WR(MVGBE_SMI_REG, smi_reg);
  150. return 0;
  151. }
  152. /*
  153. * smi_reg_write - miiphy_write callback function.
  154. *
  155. * Returns 0 if write succeed, -EFAULT on error
  156. */
  157. static int smi_reg_write(struct mii_dev *bus, int phy_adr, int devad,
  158. int reg_ofs, u16 data)
  159. {
  160. #ifdef CONFIG_DM_ETH
  161. struct mvgbe_device *dmvgbe = bus->priv;
  162. #else
  163. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  164. struct mvgbe_device *dmvgbe = to_mvgbe(dev);
  165. #endif
  166. return __mvgbe_mdio_write(dmvgbe, phy_adr, devad, reg_ofs, data);
  167. }
  168. #endif
  169. /* Stop and checks all queues */
  170. static void stop_queue(u32 * qreg)
  171. {
  172. u32 reg_data;
  173. reg_data = readl(qreg);
  174. if (reg_data & 0xFF) {
  175. /* Issue stop command for active channels only */
  176. writel((reg_data << 8), qreg);
  177. /* Wait for all queue activity to terminate. */
  178. do {
  179. /*
  180. * Check port cause register that all queues
  181. * are stopped
  182. */
  183. reg_data = readl(qreg);
  184. }
  185. while (reg_data & 0xFF);
  186. }
  187. }
  188. /*
  189. * set_access_control - Config address decode parameters for Ethernet unit
  190. *
  191. * This function configures the address decode parameters for the Gigabit
  192. * Ethernet Controller according the given parameters struct.
  193. *
  194. * @regs Register struct pointer.
  195. * @param Address decode parameter struct.
  196. */
  197. static void set_access_control(struct mvgbe_registers *regs,
  198. struct mvgbe_winparam *param)
  199. {
  200. u32 access_prot_reg;
  201. /* Set access control register */
  202. access_prot_reg = MVGBE_REG_RD(regs->epap);
  203. /* clear window permission */
  204. access_prot_reg &= (~(3 << (param->win * 2)));
  205. access_prot_reg |= (param->access_ctrl << (param->win * 2));
  206. MVGBE_REG_WR(regs->epap, access_prot_reg);
  207. /* Set window Size reg (SR) */
  208. MVGBE_REG_WR(regs->barsz[param->win].size,
  209. (((param->size / 0x10000) - 1) << 16));
  210. /* Set window Base address reg (BA) */
  211. MVGBE_REG_WR(regs->barsz[param->win].bar,
  212. (param->target | param->attrib | param->base_addr));
  213. /* High address remap reg (HARR) */
  214. if (param->win < 4)
  215. MVGBE_REG_WR(regs->ha_remap[param->win], param->high_addr);
  216. /* Base address enable reg (BARER) */
  217. if (param->enable == 1)
  218. MVGBE_REG_BITS_RESET(regs->bare, (1 << param->win));
  219. else
  220. MVGBE_REG_BITS_SET(regs->bare, (1 << param->win));
  221. }
  222. static void set_dram_access(struct mvgbe_registers *regs)
  223. {
  224. struct mvgbe_winparam win_param;
  225. int i;
  226. for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  227. /* Set access parameters for DRAM bank i */
  228. win_param.win = i; /* Use Ethernet window i */
  229. /* Window target - DDR */
  230. win_param.target = MVGBE_TARGET_DRAM;
  231. /* Enable full access */
  232. win_param.access_ctrl = EWIN_ACCESS_FULL;
  233. win_param.high_addr = 0;
  234. /* Get bank base and size */
  235. win_param.base_addr = gd->bd->bi_dram[i].start;
  236. win_param.size = gd->bd->bi_dram[i].size;
  237. if (win_param.size == 0)
  238. win_param.enable = 0;
  239. else
  240. win_param.enable = 1; /* Enable the access */
  241. /* Enable DRAM bank */
  242. switch (i) {
  243. case 0:
  244. win_param.attrib = EBAR_DRAM_CS0;
  245. break;
  246. case 1:
  247. win_param.attrib = EBAR_DRAM_CS1;
  248. break;
  249. case 2:
  250. win_param.attrib = EBAR_DRAM_CS2;
  251. break;
  252. case 3:
  253. win_param.attrib = EBAR_DRAM_CS3;
  254. break;
  255. default:
  256. /* invalid bank, disable access */
  257. win_param.enable = 0;
  258. win_param.attrib = 0;
  259. break;
  260. }
  261. /* Set the access control for address window(EPAPR) RD/WR */
  262. set_access_control(regs, &win_param);
  263. }
  264. }
  265. /*
  266. * port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables
  267. *
  268. * Go through all the DA filter tables (Unicast, Special Multicast & Other
  269. * Multicast) and set each entry to 0.
  270. */
  271. static void port_init_mac_tables(struct mvgbe_registers *regs)
  272. {
  273. int table_index;
  274. /* Clear DA filter unicast table (Ex_dFUT) */
  275. for (table_index = 0; table_index < 4; ++table_index)
  276. MVGBE_REG_WR(regs->dfut[table_index], 0);
  277. for (table_index = 0; table_index < 64; ++table_index) {
  278. /* Clear DA filter special multicast table (Ex_dFSMT) */
  279. MVGBE_REG_WR(regs->dfsmt[table_index], 0);
  280. /* Clear DA filter other multicast table (Ex_dFOMT) */
  281. MVGBE_REG_WR(regs->dfomt[table_index], 0);
  282. }
  283. }
  284. /*
  285. * port_uc_addr - This function Set the port unicast address table
  286. *
  287. * This function locates the proper entry in the Unicast table for the
  288. * specified MAC nibble and sets its properties according to function
  289. * parameters.
  290. * This function add/removes MAC addresses from the port unicast address
  291. * table.
  292. *
  293. * @uc_nibble Unicast MAC Address last nibble.
  294. * @option 0 = Add, 1 = remove address.
  295. *
  296. * RETURN: 1 if output succeeded. 0 if option parameter is invalid.
  297. */
  298. static int port_uc_addr(struct mvgbe_registers *regs, u8 uc_nibble,
  299. int option)
  300. {
  301. u32 unicast_reg;
  302. u32 tbl_offset;
  303. u32 reg_offset;
  304. /* Locate the Unicast table entry */
  305. uc_nibble = (0xf & uc_nibble);
  306. /* Register offset from unicast table base */
  307. tbl_offset = (uc_nibble / 4);
  308. /* Entry offset within the above register */
  309. reg_offset = uc_nibble % 4;
  310. switch (option) {
  311. case REJECT_MAC_ADDR:
  312. /*
  313. * Clear accepts frame bit at specified unicast
  314. * DA table entry
  315. */
  316. unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
  317. unicast_reg &= (0xFF << (8 * reg_offset));
  318. MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
  319. break;
  320. case ACCEPT_MAC_ADDR:
  321. /* Set accepts frame bit at unicast DA filter table entry */
  322. unicast_reg = MVGBE_REG_RD(regs->dfut[tbl_offset]);
  323. unicast_reg &= (0xFF << (8 * reg_offset));
  324. unicast_reg |= ((0x01 | (RXUQ << 1)) << (8 * reg_offset));
  325. MVGBE_REG_WR(regs->dfut[tbl_offset], unicast_reg);
  326. break;
  327. default:
  328. return 0;
  329. }
  330. return 1;
  331. }
  332. /*
  333. * port_uc_addr_set - This function Set the port Unicast address.
  334. */
  335. static void port_uc_addr_set(struct mvgbe_device *dmvgbe, u8 *p_addr)
  336. {
  337. struct mvgbe_registers *regs = dmvgbe->regs;
  338. u32 mac_h;
  339. u32 mac_l;
  340. mac_l = (p_addr[4] << 8) | (p_addr[5]);
  341. mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | (p_addr[2] << 8) |
  342. (p_addr[3] << 0);
  343. MVGBE_REG_WR(regs->macal, mac_l);
  344. MVGBE_REG_WR(regs->macah, mac_h);
  345. /* Accept frames of this address */
  346. port_uc_addr(regs, p_addr[5], ACCEPT_MAC_ADDR);
  347. }
  348. /*
  349. * mvgbe_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory.
  350. */
  351. static void mvgbe_init_rx_desc_ring(struct mvgbe_device *dmvgbe)
  352. {
  353. struct mvgbe_rxdesc *p_rx_desc;
  354. int i;
  355. /* initialize the Rx descriptors ring */
  356. p_rx_desc = dmvgbe->p_rxdesc;
  357. for (i = 0; i < RINGSZ; i++) {
  358. p_rx_desc->cmd_sts =
  359. MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
  360. p_rx_desc->buf_size = PKTSIZE_ALIGN;
  361. p_rx_desc->byte_cnt = 0;
  362. p_rx_desc->buf_ptr = dmvgbe->p_rxbuf + i * PKTSIZE_ALIGN;
  363. if (i == (RINGSZ - 1))
  364. p_rx_desc->nxtdesc_p = dmvgbe->p_rxdesc;
  365. else {
  366. p_rx_desc->nxtdesc_p = (struct mvgbe_rxdesc *)
  367. ((u32) p_rx_desc + MV_RXQ_DESC_ALIGNED_SIZE);
  368. p_rx_desc = p_rx_desc->nxtdesc_p;
  369. }
  370. }
  371. dmvgbe->p_rxdesc_curr = dmvgbe->p_rxdesc;
  372. }
  373. static int __mvgbe_init(struct mvgbe_device *dmvgbe, u8 *enetaddr,
  374. const char *name)
  375. {
  376. struct mvgbe_registers *regs = dmvgbe->regs;
  377. #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
  378. !defined(CONFIG_PHYLIB) && \
  379. !defined(CONFIG_DM_ETH) && \
  380. defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
  381. int i;
  382. #endif
  383. /* setup RX rings */
  384. mvgbe_init_rx_desc_ring(dmvgbe);
  385. /* Clear the ethernet port interrupts */
  386. MVGBE_REG_WR(regs->ic, 0);
  387. MVGBE_REG_WR(regs->ice, 0);
  388. /* Unmask RX buffer and TX end interrupt */
  389. MVGBE_REG_WR(regs->pim, INT_CAUSE_UNMASK_ALL);
  390. /* Unmask phy and link status changes interrupts */
  391. MVGBE_REG_WR(regs->peim, INT_CAUSE_UNMASK_ALL_EXT);
  392. set_dram_access(regs);
  393. port_init_mac_tables(regs);
  394. port_uc_addr_set(dmvgbe, enetaddr);
  395. /* Assign port configuration and command. */
  396. MVGBE_REG_WR(regs->pxc, PRT_CFG_VAL);
  397. MVGBE_REG_WR(regs->pxcx, PORT_CFG_EXTEND_VALUE);
  398. MVGBE_REG_WR(regs->psc0, PORT_SERIAL_CONTROL_VALUE);
  399. /* Assign port SDMA configuration */
  400. MVGBE_REG_WR(regs->sdc, PORT_SDMA_CFG_VALUE);
  401. MVGBE_REG_WR(regs->tqx[0].qxttbc, QTKNBKT_DEF_VAL);
  402. MVGBE_REG_WR(regs->tqx[0].tqxtbc,
  403. (QMTBS_DEF_VAL << 16) | QTKNRT_DEF_VAL);
  404. /* Turn off the port/RXUQ bandwidth limitation */
  405. MVGBE_REG_WR(regs->pmtu, 0);
  406. /* Set maximum receive buffer to 9700 bytes */
  407. MVGBE_REG_WR(regs->psc0, MVGBE_MAX_RX_PACKET_9700BYTE
  408. | (MVGBE_REG_RD(regs->psc0) & MRU_MASK));
  409. /* Enable port initially */
  410. MVGBE_REG_BITS_SET(regs->psc0, MVGBE_SERIAL_PORT_EN);
  411. /*
  412. * Set ethernet MTU for leaky bucket mechanism to 0 - this will
  413. * disable the leaky bucket mechanism .
  414. */
  415. MVGBE_REG_WR(regs->pmtu, 0);
  416. /* Assignment of Rx CRDB of given RXUQ */
  417. MVGBE_REG_WR(regs->rxcdp[RXUQ], (u32) dmvgbe->p_rxdesc_curr);
  418. /* ensure previous write is done before enabling Rx DMA */
  419. isb();
  420. /* Enable port Rx. */
  421. MVGBE_REG_WR(regs->rqc, (1 << RXUQ));
  422. #if (defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) && \
  423. !defined(CONFIG_PHYLIB) && \
  424. !defined(CONFIG_DM_ETH) && \
  425. defined(CONFIG_SYS_FAULT_ECHO_LINK_DOWN)
  426. /* Wait up to 5s for the link status */
  427. for (i = 0; i < 5; i++) {
  428. u16 phyadr;
  429. miiphy_read(name, MV_PHY_ADR_REQUEST,
  430. MV_PHY_ADR_REQUEST, &phyadr);
  431. /* Return if we get link up */
  432. if (miiphy_link(name, phyadr))
  433. return 0;
  434. udelay(1000000);
  435. }
  436. printf("No link on %s\n", name);
  437. return -1;
  438. #endif
  439. return 0;
  440. }
  441. #ifndef CONFIG_DM_ETH
  442. static int mvgbe_init(struct eth_device *dev)
  443. {
  444. struct mvgbe_device *dmvgbe = to_mvgbe(dev);
  445. return __mvgbe_init(dmvgbe, dmvgbe->dev.enetaddr, dmvgbe->dev.name);
  446. }
  447. #endif
  448. static void __mvgbe_halt(struct mvgbe_device *dmvgbe)
  449. {
  450. struct mvgbe_registers *regs = dmvgbe->regs;
  451. /* Disable all gigE address decoder */
  452. MVGBE_REG_WR(regs->bare, 0x3f);
  453. stop_queue(&regs->tqc);
  454. stop_queue(&regs->rqc);
  455. /* Disable port */
  456. MVGBE_REG_BITS_RESET(regs->psc0, MVGBE_SERIAL_PORT_EN);
  457. /* Set port is not reset */
  458. MVGBE_REG_BITS_RESET(regs->psc1, 1 << 4);
  459. #ifdef CONFIG_SYS_MII_MODE
  460. /* Set MMI interface up */
  461. MVGBE_REG_BITS_RESET(regs->psc1, 1 << 3);
  462. #endif
  463. /* Disable & mask ethernet port interrupts */
  464. MVGBE_REG_WR(regs->ic, 0);
  465. MVGBE_REG_WR(regs->ice, 0);
  466. MVGBE_REG_WR(regs->pim, 0);
  467. MVGBE_REG_WR(regs->peim, 0);
  468. }
  469. #ifndef CONFIG_DM_ETH
  470. static int mvgbe_halt(struct eth_device *dev)
  471. {
  472. struct mvgbe_device *dmvgbe = to_mvgbe(dev);
  473. __mvgbe_halt(dmvgbe);
  474. return 0;
  475. }
  476. #endif
  477. #ifdef CONFIG_DM_ETH
  478. static int mvgbe_write_hwaddr(struct udevice *dev)
  479. {
  480. struct eth_pdata *pdata = dev_get_platdata(dev);
  481. port_uc_addr_set(dev_get_priv(dev), pdata->enetaddr);
  482. return 0;
  483. }
  484. #else
  485. static int mvgbe_write_hwaddr(struct eth_device *dev)
  486. {
  487. struct mvgbe_device *dmvgbe = to_mvgbe(dev);
  488. /* Programs net device MAC address after initialization */
  489. port_uc_addr_set(dmvgbe, dmvgbe->dev.enetaddr);
  490. return 0;
  491. }
  492. #endif
  493. static int __mvgbe_send(struct mvgbe_device *dmvgbe, void *dataptr,
  494. int datasize)
  495. {
  496. struct mvgbe_registers *regs = dmvgbe->regs;
  497. struct mvgbe_txdesc *p_txdesc = dmvgbe->p_txdesc;
  498. void *p = (void *)dataptr;
  499. u32 cmd_sts;
  500. u32 txuq0_reg_addr;
  501. /* Copy buffer if it's misaligned */
  502. if ((u32) dataptr & 0x07) {
  503. if (datasize > PKTSIZE_ALIGN) {
  504. printf("Non-aligned data too large (%d)\n",
  505. datasize);
  506. return -1;
  507. }
  508. memcpy(dmvgbe->p_aligned_txbuf, p, datasize);
  509. p = dmvgbe->p_aligned_txbuf;
  510. }
  511. p_txdesc->cmd_sts = MVGBE_ZERO_PADDING | MVGBE_GEN_CRC;
  512. p_txdesc->cmd_sts |= MVGBE_TX_FIRST_DESC | MVGBE_TX_LAST_DESC;
  513. p_txdesc->cmd_sts |= MVGBE_BUFFER_OWNED_BY_DMA;
  514. p_txdesc->cmd_sts |= MVGBE_TX_EN_INTERRUPT;
  515. p_txdesc->buf_ptr = (u8 *) p;
  516. p_txdesc->byte_cnt = datasize;
  517. /* Set this tc desc as zeroth TXUQ */
  518. txuq0_reg_addr = (u32)&regs->tcqdp[TXUQ];
  519. writel((u32) p_txdesc, txuq0_reg_addr);
  520. /* ensure tx desc writes above are performed before we start Tx DMA */
  521. isb();
  522. /* Apply send command using zeroth TXUQ */
  523. MVGBE_REG_WR(regs->tqc, (1 << TXUQ));
  524. /*
  525. * wait for packet xmit completion
  526. */
  527. cmd_sts = readl(&p_txdesc->cmd_sts);
  528. while (cmd_sts & MVGBE_BUFFER_OWNED_BY_DMA) {
  529. /* return fail if error is detected */
  530. if ((cmd_sts & (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME)) ==
  531. (MVGBE_ERROR_SUMMARY | MVGBE_TX_LAST_FRAME) &&
  532. cmd_sts & (MVGBE_UR_ERROR | MVGBE_RL_ERROR)) {
  533. printf("Err..(%s) in xmit packet\n", __func__);
  534. return -1;
  535. }
  536. cmd_sts = readl(&p_txdesc->cmd_sts);
  537. };
  538. return 0;
  539. }
  540. #ifndef CONFIG_DM_ETH
  541. static int mvgbe_send(struct eth_device *dev, void *dataptr, int datasize)
  542. {
  543. struct mvgbe_device *dmvgbe = to_mvgbe(dev);
  544. return __mvgbe_send(dmvgbe, dataptr, datasize);
  545. }
  546. #endif
  547. static int __mvgbe_recv(struct mvgbe_device *dmvgbe, uchar **packetp)
  548. {
  549. struct mvgbe_rxdesc *p_rxdesc_curr = dmvgbe->p_rxdesc_curr;
  550. u32 cmd_sts;
  551. u32 timeout = 0;
  552. u32 rxdesc_curr_addr;
  553. unsigned char *data;
  554. int rx_bytes = 0;
  555. *packetp = NULL;
  556. /* wait untill rx packet available or timeout */
  557. do {
  558. if (timeout < MVGBE_PHY_SMI_TIMEOUT)
  559. timeout++;
  560. else {
  561. debug("%s time out...\n", __func__);
  562. return -1;
  563. }
  564. } while (readl(&p_rxdesc_curr->cmd_sts) & MVGBE_BUFFER_OWNED_BY_DMA);
  565. if (p_rxdesc_curr->byte_cnt != 0) {
  566. debug("%s: Received %d byte Packet @ 0x%x (cmd_sts= %08x)\n",
  567. __func__, (u32) p_rxdesc_curr->byte_cnt,
  568. (u32) p_rxdesc_curr->buf_ptr,
  569. (u32) p_rxdesc_curr->cmd_sts);
  570. }
  571. /*
  572. * In case received a packet without first/last bits on
  573. * OR the error summary bit is on,
  574. * the packets needs to be dropeed.
  575. */
  576. cmd_sts = readl(&p_rxdesc_curr->cmd_sts);
  577. if ((cmd_sts &
  578. (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC))
  579. != (MVGBE_RX_FIRST_DESC | MVGBE_RX_LAST_DESC)) {
  580. printf("Err..(%s) Dropping packet spread on"
  581. " multiple descriptors\n", __func__);
  582. } else if (cmd_sts & MVGBE_ERROR_SUMMARY) {
  583. printf("Err..(%s) Dropping packet with errors\n",
  584. __func__);
  585. } else {
  586. /* !!! call higher layer processing */
  587. debug("%s: Sending Received packet to"
  588. " upper layer (net_process_received_packet)\n",
  589. __func__);
  590. data = (p_rxdesc_curr->buf_ptr + RX_BUF_OFFSET);
  591. rx_bytes = (int)(p_rxdesc_curr->byte_cnt -
  592. RX_BUF_OFFSET);
  593. *packetp = data;
  594. }
  595. /*
  596. * free these descriptors and point next in the ring
  597. */
  598. p_rxdesc_curr->cmd_sts =
  599. MVGBE_BUFFER_OWNED_BY_DMA | MVGBE_RX_EN_INTERRUPT;
  600. p_rxdesc_curr->buf_size = PKTSIZE_ALIGN;
  601. p_rxdesc_curr->byte_cnt = 0;
  602. rxdesc_curr_addr = (u32)&dmvgbe->p_rxdesc_curr;
  603. writel((unsigned)p_rxdesc_curr->nxtdesc_p, rxdesc_curr_addr);
  604. return rx_bytes;
  605. }
  606. #ifndef CONFIG_DM_ETH
  607. static int mvgbe_recv(struct eth_device *dev)
  608. {
  609. struct mvgbe_device *dmvgbe = to_mvgbe(dev);
  610. uchar *packet;
  611. int ret;
  612. ret = __mvgbe_recv(dmvgbe, &packet);
  613. if (ret < 0)
  614. return ret;
  615. net_process_received_packet(packet, ret);
  616. return 0;
  617. }
  618. #endif
  619. #if defined(CONFIG_PHYLIB) || defined(CONFIG_DM_ETH)
  620. #if defined(CONFIG_DM_ETH)
  621. static struct phy_device *__mvgbe_phy_init(struct udevice *dev,
  622. struct mii_dev *bus,
  623. phy_interface_t phy_interface,
  624. int phyid)
  625. #else
  626. static struct phy_device *__mvgbe_phy_init(struct eth_device *dev,
  627. struct mii_dev *bus,
  628. phy_interface_t phy_interface,
  629. int phyid)
  630. #endif
  631. {
  632. struct phy_device *phydev;
  633. /* Set phy address of the port */
  634. miiphy_write(dev->name, MV_PHY_ADR_REQUEST, MV_PHY_ADR_REQUEST,
  635. phyid);
  636. phydev = phy_connect(bus, phyid, dev, phy_interface);
  637. if (!phydev) {
  638. printf("phy_connect failed\n");
  639. return NULL;
  640. }
  641. phy_config(phydev);
  642. phy_startup(phydev);
  643. return phydev;
  644. }
  645. #endif /* CONFIG_PHYLIB || CONFIG_DM_ETH */
  646. #if defined(CONFIG_PHYLIB) && !defined(CONFIG_DM_ETH)
  647. int mvgbe_phylib_init(struct eth_device *dev, int phyid)
  648. {
  649. struct mii_dev *bus;
  650. struct phy_device *phydev;
  651. int ret;
  652. bus = mdio_alloc();
  653. if (!bus) {
  654. printf("mdio_alloc failed\n");
  655. return -ENOMEM;
  656. }
  657. bus->read = smi_reg_read;
  658. bus->write = smi_reg_write;
  659. strcpy(bus->name, dev->name);
  660. ret = mdio_register(bus);
  661. if (ret) {
  662. printf("mdio_register failed\n");
  663. free(bus);
  664. return -ENOMEM;
  665. }
  666. phydev = __mvgbe_phy_init(dev, bus, PHY_INTERFACE_MODE_RGMII, phyid);
  667. if (!phydev)
  668. return -ENODEV;
  669. return 0;
  670. }
  671. #endif
  672. static int mvgbe_alloc_buffers(struct mvgbe_device *dmvgbe)
  673. {
  674. dmvgbe->p_rxdesc = memalign(PKTALIGN,
  675. MV_RXQ_DESC_ALIGNED_SIZE * RINGSZ + 1);
  676. if (!dmvgbe->p_rxdesc)
  677. goto error1;
  678. dmvgbe->p_rxbuf = memalign(PKTALIGN,
  679. RINGSZ * PKTSIZE_ALIGN + 1);
  680. if (!dmvgbe->p_rxbuf)
  681. goto error2;
  682. dmvgbe->p_aligned_txbuf = memalign(8, PKTSIZE_ALIGN);
  683. if (!dmvgbe->p_aligned_txbuf)
  684. goto error3;
  685. dmvgbe->p_txdesc = memalign(PKTALIGN, sizeof(struct mvgbe_txdesc) + 1);
  686. if (!dmvgbe->p_txdesc)
  687. goto error4;
  688. return 0;
  689. error4:
  690. free(dmvgbe->p_aligned_txbuf);
  691. error3:
  692. free(dmvgbe->p_rxbuf);
  693. error2:
  694. free(dmvgbe->p_rxdesc);
  695. error1:
  696. return -ENOMEM;
  697. }
  698. #ifndef CONFIG_DM_ETH
  699. int mvgbe_initialize(struct bd_info *bis)
  700. {
  701. struct mvgbe_device *dmvgbe;
  702. struct eth_device *dev;
  703. int devnum;
  704. int ret;
  705. u8 used_ports[MAX_MVGBE_DEVS] = CONFIG_MVGBE_PORTS;
  706. for (devnum = 0; devnum < MAX_MVGBE_DEVS; devnum++) {
  707. /*skip if port is configured not to use */
  708. if (used_ports[devnum] == 0)
  709. continue;
  710. dmvgbe = malloc(sizeof(struct mvgbe_device));
  711. if (!dmvgbe)
  712. return -ENOMEM;
  713. memset(dmvgbe, 0, sizeof(struct mvgbe_device));
  714. ret = mvgbe_alloc_buffers(dmvgbe);
  715. if (ret) {
  716. printf("Err.. %s Failed to allocate memory\n",
  717. __func__);
  718. free(dmvgbe);
  719. return ret;
  720. }
  721. dev = &dmvgbe->dev;
  722. /* must be less than sizeof(dev->name) */
  723. sprintf(dev->name, "egiga%d", devnum);
  724. switch (devnum) {
  725. case 0:
  726. dmvgbe->regs = (void *)MVGBE0_BASE;
  727. break;
  728. #if defined(MVGBE1_BASE)
  729. case 1:
  730. dmvgbe->regs = (void *)MVGBE1_BASE;
  731. break;
  732. #endif
  733. default: /* this should never happen */
  734. printf("Err..(%s) Invalid device number %d\n",
  735. __func__, devnum);
  736. return -1;
  737. }
  738. dev->init = (void *)mvgbe_init;
  739. dev->halt = (void *)mvgbe_halt;
  740. dev->send = (void *)mvgbe_send;
  741. dev->recv = (void *)mvgbe_recv;
  742. dev->write_hwaddr = (void *)mvgbe_write_hwaddr;
  743. eth_register(dev);
  744. #if defined(CONFIG_PHYLIB)
  745. mvgbe_phylib_init(dev, PHY_BASE_ADR + devnum);
  746. #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  747. int retval;
  748. struct mii_dev *mdiodev = mdio_alloc();
  749. if (!mdiodev)
  750. return -ENOMEM;
  751. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  752. mdiodev->read = smi_reg_read;
  753. mdiodev->write = smi_reg_write;
  754. retval = mdio_register(mdiodev);
  755. if (retval < 0)
  756. return retval;
  757. /* Set phy address of the port */
  758. miiphy_write(dev->name, MV_PHY_ADR_REQUEST,
  759. MV_PHY_ADR_REQUEST, PHY_BASE_ADR + devnum);
  760. #endif
  761. }
  762. return 0;
  763. }
  764. #endif
  765. #ifdef CONFIG_DM_ETH
  766. static int mvgbe_port_is_fixed_link(struct mvgbe_device *dmvgbe)
  767. {
  768. return dmvgbe->phyaddr > PHY_MAX_ADDR;
  769. }
  770. static int mvgbe_start(struct udevice *dev)
  771. {
  772. struct eth_pdata *pdata = dev_get_platdata(dev);
  773. struct mvgbe_device *dmvgbe = dev_get_priv(dev);
  774. int ret;
  775. ret = __mvgbe_init(dmvgbe, pdata->enetaddr, dev->name);
  776. if (ret)
  777. return ret;
  778. if (!mvgbe_port_is_fixed_link(dmvgbe)) {
  779. dmvgbe->phydev = __mvgbe_phy_init(dev, dmvgbe->bus,
  780. dmvgbe->phy_interface,
  781. dmvgbe->phyaddr);
  782. if (!dmvgbe->phydev)
  783. return -ENODEV;
  784. }
  785. return 0;
  786. }
  787. static int mvgbe_send(struct udevice *dev, void *packet, int length)
  788. {
  789. struct mvgbe_device *dmvgbe = dev_get_priv(dev);
  790. return __mvgbe_send(dmvgbe, packet, length);
  791. }
  792. static int mvgbe_recv(struct udevice *dev, int flags, uchar **packetp)
  793. {
  794. struct mvgbe_device *dmvgbe = dev_get_priv(dev);
  795. return __mvgbe_recv(dmvgbe, packetp);
  796. }
  797. static void mvgbe_stop(struct udevice *dev)
  798. {
  799. struct mvgbe_device *dmvgbe = dev_get_priv(dev);
  800. __mvgbe_halt(dmvgbe);
  801. }
  802. static int mvgbe_probe(struct udevice *dev)
  803. {
  804. struct eth_pdata *pdata = dev_get_platdata(dev);
  805. struct mvgbe_device *dmvgbe = dev_get_priv(dev);
  806. struct mii_dev *bus;
  807. int ret;
  808. ret = mvgbe_alloc_buffers(dmvgbe);
  809. if (ret)
  810. return ret;
  811. dmvgbe->regs = (void __iomem *)pdata->iobase;
  812. bus = mdio_alloc();
  813. if (!bus) {
  814. printf("Failed to allocate MDIO bus\n");
  815. return -ENOMEM;
  816. }
  817. bus->read = smi_reg_read;
  818. bus->write = smi_reg_write;
  819. snprintf(bus->name, sizeof(bus->name), dev->name);
  820. bus->priv = dmvgbe;
  821. dmvgbe->bus = bus;
  822. ret = mdio_register(bus);
  823. if (ret < 0)
  824. return ret;
  825. return 0;
  826. }
  827. static const struct eth_ops mvgbe_ops = {
  828. .start = mvgbe_start,
  829. .send = mvgbe_send,
  830. .recv = mvgbe_recv,
  831. .stop = mvgbe_stop,
  832. .write_hwaddr = mvgbe_write_hwaddr,
  833. };
  834. static int mvgbe_ofdata_to_platdata(struct udevice *dev)
  835. {
  836. struct eth_pdata *pdata = dev_get_platdata(dev);
  837. struct mvgbe_device *dmvgbe = dev_get_priv(dev);
  838. void *blob = (void *)gd->fdt_blob;
  839. int node = dev_of_offset(dev);
  840. const char *phy_mode;
  841. int fl_node;
  842. int pnode;
  843. unsigned long addr;
  844. pdata->iobase = dev_read_addr(dev);
  845. pdata->phy_interface = -1;
  846. pnode = fdt_node_offset_by_compatible(blob, node,
  847. "marvell,kirkwood-eth-port");
  848. /* Get phy-mode / phy_interface from DT */
  849. phy_mode = fdt_getprop(gd->fdt_blob, pnode, "phy-mode", NULL);
  850. if (phy_mode)
  851. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  852. else
  853. pdata->phy_interface = PHY_INTERFACE_MODE_GMII;
  854. dmvgbe->phy_interface = pdata->phy_interface;
  855. /* fetch 'fixed-link' property */
  856. fl_node = fdt_subnode_offset(blob, pnode, "fixed-link");
  857. if (fl_node != -FDT_ERR_NOTFOUND) {
  858. /* set phy_addr to invalid value for fixed link */
  859. dmvgbe->phyaddr = PHY_MAX_ADDR + 1;
  860. dmvgbe->duplex = fdtdec_get_bool(blob, fl_node, "full-duplex");
  861. dmvgbe->speed = fdtdec_get_int(blob, fl_node, "speed", 0);
  862. } else {
  863. /* Now read phyaddr from DT */
  864. addr = fdtdec_lookup_phandle(blob, pnode, "phy-handle");
  865. if (addr > 0)
  866. dmvgbe->phyaddr = fdtdec_get_int(blob, addr, "reg", 0);
  867. }
  868. return 0;
  869. }
  870. static const struct udevice_id mvgbe_ids[] = {
  871. { .compatible = "marvell,kirkwood-eth" },
  872. { }
  873. };
  874. U_BOOT_DRIVER(mvgbe) = {
  875. .name = "mvgbe",
  876. .id = UCLASS_ETH,
  877. .of_match = mvgbe_ids,
  878. .ofdata_to_platdata = mvgbe_ofdata_to_platdata,
  879. .probe = mvgbe_probe,
  880. .ops = &mvgbe_ops,
  881. .priv_auto_alloc_size = sizeof(struct mvgbe_device),
  882. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  883. };
  884. #endif /* CONFIG_DM_ETH */