lpc32xx_eth.c 19 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * LPC32xx Ethernet MAC interface driver
  4. *
  5. * (C) Copyright 2014 DENX Software Engineering GmbH
  6. * Written-by: Albert ARIBAUD - 3ADEV <albert.aribaud@3adev.fr>
  7. */
  8. #include <common.h>
  9. #include <log.h>
  10. #include <net.h>
  11. #include <malloc.h>
  12. #include <miiphy.h>
  13. #include <asm/io.h>
  14. #include <linux/delay.h>
  15. #include <linux/errno.h>
  16. #include <asm/types.h>
  17. #include <asm/system.h>
  18. #include <asm/byteorder.h>
  19. #include <asm/arch/cpu.h>
  20. #include <asm/arch/config.h>
  21. /*
  22. * Notes:
  23. *
  24. * 1. Unless specified otherwise, all references to tables or paragraphs
  25. * are to UM10326, "LPC32x0 and LPC32x0/01 User manual".
  26. *
  27. * 2. Only bitfield masks/values which are actually used by the driver
  28. * are defined.
  29. */
  30. /* a single RX descriptor. The controller has an array of these */
  31. struct lpc32xx_eth_rxdesc {
  32. u32 packet; /* Receive packet pointer */
  33. u32 control; /* Descriptor command status */
  34. };
  35. #define LPC32XX_ETH_RX_DESC_SIZE (sizeof(struct lpc32xx_eth_rxdesc))
  36. /* RX control bitfields/masks (see Table 330) */
  37. #define LPC32XX_ETH_RX_CTRL_SIZE_MASK 0x000007FF
  38. #define LPC32XX_ETH_RX_CTRL_UNUSED 0x7FFFF800
  39. #define LPC32XX_ETH_RX_CTRL_INTERRUPT 0x80000000
  40. /* a single RX status. The controller has an array of these */
  41. struct lpc32xx_eth_rxstat {
  42. u32 statusinfo; /* Transmit Descriptor status */
  43. u32 statushashcrc; /* Transmit Descriptor CRCs */
  44. };
  45. #define LPC32XX_ETH_RX_STAT_SIZE (sizeof(struct lpc32xx_eth_rxstat))
  46. /* RX statusinfo bitfields/masks (see Table 333) */
  47. #define RX_STAT_RXSIZE 0x000007FF
  48. /* Helper: OR of all errors except RANGE */
  49. #define RX_STAT_ERRORS 0x1B800000
  50. /* a single TX descriptor. The controller has an array of these */
  51. struct lpc32xx_eth_txdesc {
  52. u32 packet; /* Transmit packet pointer */
  53. u32 control; /* Descriptor control */
  54. };
  55. #define LPC32XX_ETH_TX_DESC_SIZE (sizeof(struct lpc32xx_eth_txdesc))
  56. /* TX control bitfields/masks (see Table 335) */
  57. #define TX_CTRL_TXSIZE 0x000007FF
  58. #define TX_CTRL_LAST 0x40000000
  59. /* a single TX status. The controller has an array of these */
  60. struct lpc32xx_eth_txstat {
  61. u32 statusinfo; /* Transmit Descriptor status */
  62. };
  63. #define LPC32XX_ETH_TX_STAT_SIZE (sizeof(struct lpc32xx_eth_txstat))
  64. /* Ethernet MAC interface registers (see Table 283) */
  65. struct lpc32xx_eth_registers {
  66. /* MAC registers - 0x3106_0000 to 0x3106_01FC */
  67. u32 mac1; /* MAC configuration register 1 */
  68. u32 mac2; /* MAC configuration register 2 */
  69. u32 ipgt; /* Back-to-back Inter-Packet Gap reg. */
  70. u32 ipgr; /* Non-back-to-back IPG register */
  71. u32 clrt; /* Collision Window / Retry register */
  72. u32 maxf; /* Maximum Frame register */
  73. u32 supp; /* Phy Support register */
  74. u32 test;
  75. u32 mcfg; /* MII management configuration reg. */
  76. u32 mcmd; /* MII management command register */
  77. u32 madr; /* MII management address register */
  78. u32 mwtd; /* MII management wite data register */
  79. u32 mrdd; /* MII management read data register */
  80. u32 mind; /* MII management indicators register */
  81. u32 reserved1[2];
  82. u32 sa0; /* Station address register 0 */
  83. u32 sa1; /* Station address register 1 */
  84. u32 sa2; /* Station address register 2 */
  85. u32 reserved2[45];
  86. /* Control registers */
  87. u32 command;
  88. u32 status;
  89. u32 rxdescriptor;
  90. u32 rxstatus;
  91. u32 rxdescriptornumber; /* actually, number MINUS ONE */
  92. u32 rxproduceindex; /* head of rx desc fifo */
  93. u32 rxconsumeindex; /* tail of rx desc fifo */
  94. u32 txdescriptor;
  95. u32 txstatus;
  96. u32 txdescriptornumber; /* actually, number MINUS ONE */
  97. u32 txproduceindex; /* head of rx desc fifo */
  98. u32 txconsumeindex; /* tail of rx desc fifo */
  99. u32 reserved3[10];
  100. u32 tsv0; /* Transmit status vector register 0 */
  101. u32 tsv1; /* Transmit status vector register 1 */
  102. u32 rsv; /* Receive status vector register */
  103. u32 reserved4[3];
  104. u32 flowcontrolcounter;
  105. u32 flowcontrolstatus;
  106. u32 reserved5[34];
  107. /* RX filter registers - 0x3106_0200 to 0x3106_0FDC */
  108. u32 rxfilterctrl;
  109. u32 rxfilterwolstatus;
  110. u32 rxfilterwolclear;
  111. u32 reserved6;
  112. u32 hashfilterl;
  113. u32 hashfilterh;
  114. u32 reserved7[882];
  115. /* Module control registers - 0x3106_0FE0 to 0x3106_0FF8 */
  116. u32 intstatus; /* Interrupt status register */
  117. u32 intenable;
  118. u32 intclear;
  119. u32 intset;
  120. u32 reserved8;
  121. u32 powerdown;
  122. u32 reserved9;
  123. };
  124. /* MAC1 register bitfields/masks and offsets (see Table 283) */
  125. #define MAC1_RECV_ENABLE 0x00000001
  126. #define MAC1_PASS_ALL_RX_FRAMES 0x00000002
  127. #define MAC1_SOFT_RESET 0x00008000
  128. /* Helper: general reset */
  129. #define MAC1_RESETS 0x0000CF00
  130. /* MAC2 register bitfields/masks and offsets (see Table 284) */
  131. #define MAC2_FULL_DUPLEX 0x00000001
  132. #define MAC2_CRC_ENABLE 0x00000010
  133. #define MAC2_PAD_CRC_ENABLE 0x00000020
  134. /* SUPP register bitfields/masks and offsets (see Table 290) */
  135. #define SUPP_SPEED 0x00000100
  136. /* MCFG register bitfields/masks and offsets (see Table 292) */
  137. #define MCFG_RESET_MII_MGMT 0x00008000
  138. /* divide clock by 28 (see Table 293) */
  139. #define MCFG_CLOCK_SELECT_DIV28 0x0000001C
  140. /* MADR register bitfields/masks and offsets (see Table 295) */
  141. #define MADR_REG_MASK 0x0000001F
  142. #define MADR_PHY_MASK 0x00001F00
  143. #define MADR_REG_OFFSET 0
  144. #define MADR_PHY_OFFSET 8
  145. /* MIND register bitfields/masks (see Table 298) */
  146. #define MIND_BUSY 0x00000001
  147. /* COMMAND register bitfields/masks and offsets (see Table 283) */
  148. #define COMMAND_RXENABLE 0x00000001
  149. #define COMMAND_TXENABLE 0x00000002
  150. #define COMMAND_PASSRUNTFRAME 0x00000040
  151. #define COMMAND_RMII 0x00000200
  152. #define COMMAND_FULL_DUPLEX 0x00000400
  153. /* Helper: general reset */
  154. #define COMMAND_RESETS 0x00000038
  155. /* STATUS register bitfields/masks and offsets (see Table 283) */
  156. #define STATUS_RXSTATUS 0x00000001
  157. #define STATUS_TXSTATUS 0x00000002
  158. /* RXFILTERCTRL register bitfields/masks (see Table 319) */
  159. #define RXFILTERCTRL_ACCEPTBROADCAST 0x00000002
  160. #define RXFILTERCTRL_ACCEPTPERFECT 0x00000020
  161. /* Buffers and descriptors */
  162. #define ATTRS(n) __aligned(n)
  163. #define TX_BUF_COUNT 4
  164. #define RX_BUF_COUNT 4
  165. struct lpc32xx_eth_buffers {
  166. ATTRS(4) struct lpc32xx_eth_txdesc tx_desc[TX_BUF_COUNT];
  167. ATTRS(4) struct lpc32xx_eth_txstat tx_stat[TX_BUF_COUNT];
  168. ATTRS(PKTALIGN) u8 tx_buf[TX_BUF_COUNT*PKTSIZE_ALIGN];
  169. ATTRS(4) struct lpc32xx_eth_rxdesc rx_desc[RX_BUF_COUNT];
  170. ATTRS(8) struct lpc32xx_eth_rxstat rx_stat[RX_BUF_COUNT];
  171. ATTRS(PKTALIGN) u8 rx_buf[RX_BUF_COUNT*PKTSIZE_ALIGN];
  172. };
  173. /* port device data struct */
  174. struct lpc32xx_eth_device {
  175. struct eth_device dev;
  176. struct lpc32xx_eth_registers *regs;
  177. struct lpc32xx_eth_buffers *bufs;
  178. bool phy_rmii;
  179. };
  180. #define LPC32XX_ETH_DEVICE_SIZE (sizeof(struct lpc32xx_eth_device))
  181. /* generic macros */
  182. #define to_lpc32xx_eth(_d) container_of(_d, struct lpc32xx_eth_device, dev)
  183. /* timeout for MII polling */
  184. #define MII_TIMEOUT 10000000
  185. /* limits for PHY and register addresses */
  186. #define MII_MAX_REG (MADR_REG_MASK >> MADR_REG_OFFSET)
  187. #define MII_MAX_PHY (MADR_PHY_MASK >> MADR_PHY_OFFSET)
  188. #if defined(CONFIG_PHYLIB) || defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  189. /*
  190. * mii_reg_read - miiphy_read callback function.
  191. *
  192. * Returns 16bit phy register value, or 0xffff on error
  193. */
  194. static int mii_reg_read(struct mii_dev *bus, int phy_adr, int devad,
  195. int reg_ofs)
  196. {
  197. u16 data = 0;
  198. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  199. struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
  200. struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
  201. u32 mind_reg;
  202. u32 timeout;
  203. /* check parameters */
  204. if (phy_adr > MII_MAX_PHY) {
  205. printf("%s:%u: Invalid PHY address %d\n",
  206. __func__, __LINE__, phy_adr);
  207. return -EFAULT;
  208. }
  209. if (reg_ofs > MII_MAX_REG) {
  210. printf("%s:%u: Invalid register offset %d\n",
  211. __func__, __LINE__, reg_ofs);
  212. return -EFAULT;
  213. }
  214. /* write the phy and reg addressse into the MII address reg */
  215. writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
  216. &regs->madr);
  217. /* write 1 to the MII command register to cause a read */
  218. writel(1, &regs->mcmd);
  219. /* wait till the MII is not busy */
  220. timeout = MII_TIMEOUT;
  221. do {
  222. /* read MII indicators register */
  223. mind_reg = readl(&regs->mind);
  224. if (--timeout == 0)
  225. break;
  226. } while (mind_reg & MIND_BUSY);
  227. /* write 0 to the MII command register to finish the read */
  228. writel(0, &regs->mcmd);
  229. if (timeout == 0) {
  230. printf("%s:%u: MII busy timeout\n", __func__, __LINE__);
  231. return -EFAULT;
  232. }
  233. data = (u16) readl(&regs->mrdd);
  234. debug("%s:(adr %d, off %d) => %04x\n", __func__, phy_adr,
  235. reg_ofs, data);
  236. return data;
  237. }
  238. /*
  239. * mii_reg_write - imiiphy_write callback function.
  240. *
  241. * Returns 0 if write succeed, -EINVAL on bad parameters
  242. * -ETIME on timeout
  243. */
  244. static int mii_reg_write(struct mii_dev *bus, int phy_adr, int devad,
  245. int reg_ofs, u16 data)
  246. {
  247. struct eth_device *dev = eth_get_dev_by_name(bus->name);
  248. struct lpc32xx_eth_device *dlpc32xx_eth = to_lpc32xx_eth(dev);
  249. struct lpc32xx_eth_registers *regs = dlpc32xx_eth->regs;
  250. u32 mind_reg;
  251. u32 timeout;
  252. /* check parameters */
  253. if (phy_adr > MII_MAX_PHY) {
  254. printf("%s:%u: Invalid PHY address %d\n",
  255. __func__, __LINE__, phy_adr);
  256. return -EFAULT;
  257. }
  258. if (reg_ofs > MII_MAX_REG) {
  259. printf("%s:%u: Invalid register offset %d\n",
  260. __func__, __LINE__, reg_ofs);
  261. return -EFAULT;
  262. }
  263. /* write the phy and reg addressse into the MII address reg */
  264. writel((phy_adr << MADR_PHY_OFFSET) | (reg_ofs << MADR_REG_OFFSET),
  265. &regs->madr);
  266. /* write data to the MII write register */
  267. writel(data, &regs->mwtd);
  268. /* wait till the MII is not busy */
  269. timeout = MII_TIMEOUT;
  270. do {
  271. /* read MII indicators register */
  272. mind_reg = readl(&regs->mind);
  273. if (--timeout == 0)
  274. break;
  275. } while (mind_reg & MIND_BUSY);
  276. if (timeout == 0) {
  277. printf("%s:%u: MII busy timeout\n", __func__,
  278. __LINE__);
  279. return -EFAULT;
  280. }
  281. /*debug("%s:(adr %d, off %d) <= %04x\n", __func__, phy_adr,
  282. reg_ofs, data);*/
  283. return 0;
  284. }
  285. #endif
  286. /*
  287. * Provide default Ethernet buffers base address if target did not.
  288. * Locate buffers in SRAM at 0x00001000 to avoid cache issues and
  289. * maximize throughput.
  290. */
  291. #if !defined(CONFIG_LPC32XX_ETH_BUFS_BASE)
  292. #define CONFIG_LPC32XX_ETH_BUFS_BASE 0x00001000
  293. #endif
  294. static struct lpc32xx_eth_device lpc32xx_eth = {
  295. .regs = (struct lpc32xx_eth_registers *)LPC32XX_ETH_BASE,
  296. .bufs = (struct lpc32xx_eth_buffers *)CONFIG_LPC32XX_ETH_BUFS_BASE,
  297. #if defined(CONFIG_RMII)
  298. .phy_rmii = true,
  299. #endif
  300. };
  301. #define TX_TIMEOUT 10000
  302. static int lpc32xx_eth_send(struct eth_device *dev, void *dataptr, int datasize)
  303. {
  304. struct lpc32xx_eth_device *lpc32xx_eth_device =
  305. container_of(dev, struct lpc32xx_eth_device, dev);
  306. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  307. struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
  308. int timeout, tx_index;
  309. /* time out if transmit descriptor array remains full too long */
  310. timeout = TX_TIMEOUT;
  311. while ((readl(&regs->status) & STATUS_TXSTATUS) &&
  312. (readl(&regs->txconsumeindex)
  313. == readl(&regs->txproduceindex))) {
  314. if (timeout-- == 0)
  315. return -1;
  316. }
  317. /* determine next transmit packet index to use */
  318. tx_index = readl(&regs->txproduceindex);
  319. /* set up transmit packet */
  320. memcpy((void *)&bufs->tx_buf[tx_index * PKTSIZE_ALIGN],
  321. (void *)dataptr, datasize);
  322. writel(TX_CTRL_LAST | ((datasize - 1) & TX_CTRL_TXSIZE),
  323. &bufs->tx_desc[tx_index].control);
  324. writel(0, &bufs->tx_stat[tx_index].statusinfo);
  325. /* pass transmit packet to DMA engine */
  326. tx_index = (tx_index + 1) % TX_BUF_COUNT;
  327. writel(tx_index, &regs->txproduceindex);
  328. /* transmission succeeded */
  329. return 0;
  330. }
  331. #define RX_TIMEOUT 1000000
  332. static int lpc32xx_eth_recv(struct eth_device *dev)
  333. {
  334. struct lpc32xx_eth_device *lpc32xx_eth_device =
  335. container_of(dev, struct lpc32xx_eth_device, dev);
  336. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  337. struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
  338. int timeout, rx_index;
  339. /* time out if receive descriptor array remains empty too long */
  340. timeout = RX_TIMEOUT;
  341. while (readl(&regs->rxproduceindex) == readl(&regs->rxconsumeindex)) {
  342. if (timeout-- == 0)
  343. return -1;
  344. }
  345. /* determine next receive packet index to use */
  346. rx_index = readl(&regs->rxconsumeindex);
  347. /* if data was valid, pass it on */
  348. if (!(bufs->rx_stat[rx_index].statusinfo & RX_STAT_ERRORS)) {
  349. net_process_received_packet(
  350. &(bufs->rx_buf[rx_index * PKTSIZE_ALIGN]),
  351. (bufs->rx_stat[rx_index].statusinfo
  352. & RX_STAT_RXSIZE) + 1);
  353. }
  354. /* pass receive slot back to DMA engine */
  355. rx_index = (rx_index + 1) % RX_BUF_COUNT;
  356. writel(rx_index, &regs->rxconsumeindex);
  357. /* reception successful */
  358. return 0;
  359. }
  360. static int lpc32xx_eth_write_hwaddr(struct eth_device *dev)
  361. {
  362. struct lpc32xx_eth_device *lpc32xx_eth_device =
  363. container_of(dev, struct lpc32xx_eth_device, dev);
  364. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  365. /* Save station address */
  366. writel((unsigned long) (dev->enetaddr[0] |
  367. (dev->enetaddr[1] << 8)), &regs->sa2);
  368. writel((unsigned long) (dev->enetaddr[2] |
  369. (dev->enetaddr[3] << 8)), &regs->sa1);
  370. writel((unsigned long) (dev->enetaddr[4] |
  371. (dev->enetaddr[5] << 8)), &regs->sa0);
  372. return 0;
  373. }
  374. static int lpc32xx_eth_init(struct eth_device *dev)
  375. {
  376. struct lpc32xx_eth_device *lpc32xx_eth_device =
  377. container_of(dev, struct lpc32xx_eth_device, dev);
  378. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  379. struct lpc32xx_eth_buffers *bufs = lpc32xx_eth_device->bufs;
  380. int index;
  381. /* Initial MAC initialization */
  382. writel(MAC1_PASS_ALL_RX_FRAMES, &regs->mac1);
  383. writel(MAC2_PAD_CRC_ENABLE | MAC2_CRC_ENABLE, &regs->mac2);
  384. writel(PKTSIZE_ALIGN, &regs->maxf);
  385. /* Retries: 15 (0xF). Collision window: 57 (0x37). */
  386. writel(0x370F, &regs->clrt);
  387. /* Set IP gap pt 2 to default 0x12 but pt 1 to non-default 0 */
  388. writel(0x0012, &regs->ipgr);
  389. /* pass runt (smaller than 64 bytes) frames */
  390. if (lpc32xx_eth_device->phy_rmii)
  391. writel(COMMAND_PASSRUNTFRAME | COMMAND_RMII, &regs->command);
  392. else
  393. writel(COMMAND_PASSRUNTFRAME, &regs->command);
  394. /* Configure Full/Half Duplex mode */
  395. if (miiphy_duplex(dev->name, CONFIG_PHY_ADDR) == FULL) {
  396. setbits_le32(&regs->mac2, MAC2_FULL_DUPLEX);
  397. setbits_le32(&regs->command, COMMAND_FULL_DUPLEX);
  398. writel(0x15, &regs->ipgt);
  399. } else {
  400. writel(0x12, &regs->ipgt);
  401. }
  402. /* Configure 100MBit/10MBit mode */
  403. if (miiphy_speed(dev->name, CONFIG_PHY_ADDR) == _100BASET)
  404. writel(SUPP_SPEED, &regs->supp);
  405. else
  406. writel(0, &regs->supp);
  407. /* Save station address */
  408. writel((unsigned long) (dev->enetaddr[0] |
  409. (dev->enetaddr[1] << 8)), &regs->sa2);
  410. writel((unsigned long) (dev->enetaddr[2] |
  411. (dev->enetaddr[3] << 8)), &regs->sa1);
  412. writel((unsigned long) (dev->enetaddr[4] |
  413. (dev->enetaddr[5] << 8)), &regs->sa0);
  414. /* set up transmit buffers */
  415. for (index = 0; index < TX_BUF_COUNT; index++) {
  416. bufs->tx_desc[index].control = 0;
  417. bufs->tx_stat[index].statusinfo = 0;
  418. }
  419. writel((u32)(&bufs->tx_desc), (u32 *)&regs->txdescriptor);
  420. writel((u32)(&bufs->tx_stat), &regs->txstatus);
  421. writel(TX_BUF_COUNT-1, &regs->txdescriptornumber);
  422. /* set up receive buffers */
  423. for (index = 0; index < RX_BUF_COUNT; index++) {
  424. bufs->rx_desc[index].packet =
  425. (u32) (bufs->rx_buf+index*PKTSIZE_ALIGN);
  426. bufs->rx_desc[index].control = PKTSIZE_ALIGN - 1;
  427. bufs->rx_stat[index].statusinfo = 0;
  428. bufs->rx_stat[index].statushashcrc = 0;
  429. }
  430. writel((u32)(&bufs->rx_desc), &regs->rxdescriptor);
  431. writel((u32)(&bufs->rx_stat), &regs->rxstatus);
  432. writel(RX_BUF_COUNT-1, &regs->rxdescriptornumber);
  433. /* set up transmit buffers */
  434. for (index = 0; index < TX_BUF_COUNT; index++)
  435. bufs->tx_desc[index].packet =
  436. (u32)(bufs->tx_buf + index * PKTSIZE_ALIGN);
  437. /* Enable broadcast and matching address packets */
  438. writel(RXFILTERCTRL_ACCEPTBROADCAST |
  439. RXFILTERCTRL_ACCEPTPERFECT, &regs->rxfilterctrl);
  440. /* Clear and disable interrupts */
  441. writel(0xFFFF, &regs->intclear);
  442. writel(0, &regs->intenable);
  443. /* Enable receive and transmit mode of MAC ethernet core */
  444. setbits_le32(&regs->command, COMMAND_RXENABLE | COMMAND_TXENABLE);
  445. setbits_le32(&regs->mac1, MAC1_RECV_ENABLE);
  446. /*
  447. * Perform a 'dummy' first send to work around Ethernet.1
  448. * erratum (see ES_LPC3250 rev. 9 dated 1 June 2011).
  449. * Use zeroed "index" variable as the dummy.
  450. */
  451. index = 0;
  452. lpc32xx_eth_send(dev, &index, 4);
  453. return 0;
  454. }
  455. static int lpc32xx_eth_halt(struct eth_device *dev)
  456. {
  457. struct lpc32xx_eth_device *lpc32xx_eth_device =
  458. container_of(dev, struct lpc32xx_eth_device, dev);
  459. struct lpc32xx_eth_registers *regs = lpc32xx_eth_device->regs;
  460. /* Reset all MAC logic */
  461. writel(MAC1_RESETS, &regs->mac1);
  462. writel(COMMAND_RESETS, &regs->command);
  463. /* Let reset condition settle */
  464. udelay(2000);
  465. return 0;
  466. }
  467. #if defined(CONFIG_PHYLIB)
  468. int lpc32xx_eth_phylib_init(struct eth_device *dev, int phyid)
  469. {
  470. struct lpc32xx_eth_device *lpc32xx_eth_device =
  471. container_of(dev, struct lpc32xx_eth_device, dev);
  472. struct mii_dev *bus;
  473. struct phy_device *phydev;
  474. int ret;
  475. bus = mdio_alloc();
  476. if (!bus) {
  477. printf("mdio_alloc failed\n");
  478. return -ENOMEM;
  479. }
  480. bus->read = mii_reg_read;
  481. bus->write = mii_reg_write;
  482. strcpy(bus->name, dev->name);
  483. ret = mdio_register(bus);
  484. if (ret) {
  485. printf("mdio_register failed\n");
  486. free(bus);
  487. return -ENOMEM;
  488. }
  489. if (lpc32xx_eth_device->phy_rmii)
  490. phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_RMII);
  491. else
  492. phydev = phy_connect(bus, phyid, dev, PHY_INTERFACE_MODE_MII);
  493. if (!phydev) {
  494. printf("phy_connect failed\n");
  495. return -ENODEV;
  496. }
  497. phy_config(phydev);
  498. phy_startup(phydev);
  499. return 0;
  500. }
  501. #endif
  502. int lpc32xx_eth_initialize(struct bd_info *bis)
  503. {
  504. struct eth_device *dev = &lpc32xx_eth.dev;
  505. struct lpc32xx_eth_registers *regs = lpc32xx_eth.regs;
  506. /*
  507. * Set RMII management clock rate. With HCLK at 104 MHz and
  508. * a divider of 28, this will be 3.72 MHz.
  509. */
  510. writel(MCFG_RESET_MII_MGMT, &regs->mcfg);
  511. writel(MCFG_CLOCK_SELECT_DIV28, &regs->mcfg);
  512. /* Reset all MAC logic */
  513. writel(MAC1_RESETS, &regs->mac1);
  514. writel(COMMAND_RESETS, &regs->command);
  515. /* wait 10 ms for the whole I/F to reset */
  516. udelay(10000);
  517. /* must be less than sizeof(dev->name) */
  518. strcpy(dev->name, "eth0");
  519. dev->init = (void *)lpc32xx_eth_init;
  520. dev->halt = (void *)lpc32xx_eth_halt;
  521. dev->send = (void *)lpc32xx_eth_send;
  522. dev->recv = (void *)lpc32xx_eth_recv;
  523. dev->write_hwaddr = (void *)lpc32xx_eth_write_hwaddr;
  524. /* Release SOFT reset to let MII talk to PHY */
  525. clrbits_le32(&regs->mac1, MAC1_SOFT_RESET);
  526. /* register driver before talking to phy */
  527. eth_register(dev);
  528. #if defined(CONFIG_PHYLIB)
  529. lpc32xx_eth_phylib_init(dev, CONFIG_PHY_ADDR);
  530. #elif defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  531. int retval;
  532. struct mii_dev *mdiodev = mdio_alloc();
  533. if (!mdiodev)
  534. return -ENOMEM;
  535. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  536. mdiodev->read = mii_reg_read;
  537. mdiodev->write = mii_reg_write;
  538. retval = mdio_register(mdiodev);
  539. if (retval < 0)
  540. return retval;
  541. #endif
  542. return 0;
  543. }