ftmac110.h 6.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Faraday 10/100Mbps Ethernet Controller
  4. *
  5. * (C) Copyright 2013 Faraday Technology
  6. * Dante Su <dantesu@faraday-tech.com>
  7. */
  8. #ifndef _FTMAC110_H
  9. #define _FTMAC110_H
  10. struct ftmac110_regs {
  11. uint32_t isr; /* 0x00: Interrups Status Register */
  12. uint32_t imr; /* 0x04: Interrupt Mask Register */
  13. uint32_t mac[2]; /* 0x08: MAC Address */
  14. uint32_t mht[2]; /* 0x10: Multicast Hash Table Register */
  15. uint32_t txpd; /* 0x18: Tx Poll Demand Register */
  16. uint32_t rxpd; /* 0x1c: Rx Poll Demand Register */
  17. uint32_t txba; /* 0x20: Tx Ring Base Address Register */
  18. uint32_t rxba; /* 0x24: Rx Ring Base Address Register */
  19. uint32_t itc; /* 0x28: Interrupt Timer Control Register */
  20. uint32_t aptc; /* 0x2C: Automatic Polling Timer Control Register */
  21. uint32_t dblac; /* 0x30: DMA Burst Length&Arbitration Control */
  22. uint32_t revr; /* 0x34: Revision Register */
  23. uint32_t fear; /* 0x38: Feature Register */
  24. uint32_t rsvd[19];
  25. uint32_t maccr; /* 0x88: MAC Control Register */
  26. uint32_t macsr; /* 0x8C: MAC Status Register */
  27. uint32_t phycr; /* 0x90: PHY Control Register */
  28. uint32_t phydr; /* 0x94: PHY Data Register */
  29. uint32_t fcr; /* 0x98: Flow Control Register */
  30. uint32_t bpr; /* 0x9C: Back Pressure Register */
  31. };
  32. /*
  33. * Interrupt status/mask register(ISR/IMR) bits
  34. */
  35. #define ISR_ALL 0x3ff
  36. #define ISR_PHYSTCHG (1 << 9) /* phy status change */
  37. #define ISR_AHBERR (1 << 8) /* bus error */
  38. #define ISR_RXLOST (1 << 7) /* rx lost */
  39. #define ISR_RXFIFO (1 << 6) /* rx to fifo */
  40. #define ISR_TXLOST (1 << 5) /* tx lost */
  41. #define ISR_TXOK (1 << 4) /* tx to ethernet */
  42. #define ISR_NOTXBUF (1 << 3) /* out of tx buffer */
  43. #define ISR_TXFIFO (1 << 2) /* tx to fifo */
  44. #define ISR_NORXBUF (1 << 1) /* out of rx buffer */
  45. #define ISR_RXOK (1 << 0) /* rx to buffer */
  46. /*
  47. * MACCR control bits
  48. */
  49. #define MACCR_100M (1 << 18) /* 100Mbps mode */
  50. #define MACCR_RXBCST (1 << 17) /* rx broadcast packet */
  51. #define MACCR_RXMCST (1 << 16) /* rx multicast packet */
  52. #define MACCR_FD (1 << 15) /* full duplex */
  53. #define MACCR_CRCAPD (1 << 14) /* tx crc append */
  54. #define MACCR_RXALL (1 << 12) /* rx all packets */
  55. #define MACCR_RXFTL (1 << 11) /* rx packet even it's > 1518 byte */
  56. #define MACCR_RXRUNT (1 << 10) /* rx packet even it's < 64 byte */
  57. #define MACCR_RXMCSTHT (1 << 9) /* rx multicast hash table */
  58. #define MACCR_RXEN (1 << 8) /* rx enable */
  59. #define MACCR_RXINHDTX (1 << 6) /* rx in half duplex tx */
  60. #define MACCR_TXEN (1 << 5) /* tx enable */
  61. #define MACCR_CRCDIS (1 << 4) /* tx packet even it's crc error */
  62. #define MACCR_LOOPBACK (1 << 3) /* loop-back */
  63. #define MACCR_RESET (1 << 2) /* reset */
  64. #define MACCR_RXDMAEN (1 << 1) /* rx dma enable */
  65. #define MACCR_TXDMAEN (1 << 0) /* tx dma enable */
  66. /*
  67. * PHYCR control bits
  68. */
  69. #define PHYCR_READ (1 << 26)
  70. #define PHYCR_WRITE (1 << 27)
  71. #define PHYCR_REG_SHIFT 21
  72. #define PHYCR_ADDR_SHIFT 16
  73. /*
  74. * ITC control bits
  75. */
  76. /* Tx Cycle Length */
  77. #define ITC_TX_CYCLONG (1 << 15) /* 100Mbps=81.92us; 10Mbps=819.2us */
  78. #define ITC_TX_CYCNORM (0 << 15) /* 100Mbps=5.12us; 10Mbps=51.2us */
  79. /* Tx Threshold: Aggregate n interrupts as 1 interrupt */
  80. #define ITC_TX_THR(n) (((n) & 0x7) << 12)
  81. /* Tx Interrupt Timeout = n * Tx Cycle */
  82. #define ITC_TX_ITMO(n) (((n) & 0xf) << 8)
  83. /* Rx Cycle Length */
  84. #define ITC_RX_CYCLONG (1 << 7) /* 100Mbps=81.92us; 10Mbps=819.2us */
  85. #define ITC_RX_CYCNORM (0 << 7) /* 100Mbps=5.12us; 10Mbps=51.2us */
  86. /* Rx Threshold: Aggregate n interrupts as 1 interrupt */
  87. #define ITC_RX_THR(n) (((n) & 0x7) << 4)
  88. /* Rx Interrupt Timeout = n * Rx Cycle */
  89. #define ITC_RX_ITMO(n) (((n) & 0xf) << 0)
  90. #define ITC_DEFAULT \
  91. (ITC_TX_THR(1) | ITC_TX_ITMO(0) | ITC_RX_THR(1) | ITC_RX_ITMO(0))
  92. /*
  93. * APTC contrl bits
  94. */
  95. /* Tx Cycle Length */
  96. #define APTC_TX_CYCLONG (1 << 12) /* 100Mbps=81.92us; 10Mbps=819.2us */
  97. #define APTC_TX_CYCNORM (0 << 12) /* 100Mbps=5.12us; 10Mbps=51.2us */
  98. /* Tx Poll Timeout = n * Tx Cycle, 0=No auto polling */
  99. #define APTC_TX_PTMO(n) (((n) & 0xf) << 8)
  100. /* Rx Cycle Length */
  101. #define APTC_RX_CYCLONG (1 << 4) /* 100Mbps=81.92us; 10Mbps=819.2us */
  102. #define APTC_RX_CYCNORM (0 << 4) /* 100Mbps=5.12us; 10Mbps=51.2us */
  103. /* Rx Poll Timeout = n * Rx Cycle, 0=No auto polling */
  104. #define APTC_RX_PTMO(n) (((n) & 0xf) << 0)
  105. #define APTC_DEFAULT (APTC_TX_PTMO(0) | APTC_RX_PTMO(1))
  106. /*
  107. * DBLAC contrl bits
  108. */
  109. #define DBLAC_BURST_MAX_ANY (0 << 14) /* un-limited */
  110. #define DBLAC_BURST_MAX_32X4 (2 << 14) /* max = 32 x 4 bytes */
  111. #define DBLAC_BURST_MAX_64X4 (3 << 14) /* max = 64 x 4 bytes */
  112. #define DBLAC_RXTHR_EN (1 << 9) /* enable rx threshold arbitration */
  113. #define DBLAC_RXTHR_HIGH(n) (((n) & 0x7) << 6) /* upper bound = n/8 fifo */
  114. #define DBLAC_RXTHR_LOW(n) (((n) & 0x7) << 3) /* lower bound = n/8 fifo */
  115. #define DBLAC_BURST_CAP16 (1 << 2) /* support burst 16 */
  116. #define DBLAC_BURST_CAP8 (1 << 1) /* support burst 8 */
  117. #define DBLAC_BURST_CAP4 (1 << 0) /* support burst 4 */
  118. #define DBLAC_DEFAULT \
  119. (DBLAC_RXTHR_EN | DBLAC_RXTHR_HIGH(6) | DBLAC_RXTHR_LOW(2))
  120. /*
  121. * descriptor structure
  122. */
  123. struct ftmac110_desc {
  124. uint64_t ctrl;
  125. uint32_t pbuf;
  126. void *vbuf;
  127. };
  128. #define FTMAC110_RXD_END ((uint64_t)1 << 63)
  129. #define FTMAC110_RXD_BUFSZ(x) (((uint64_t)(x) & 0x7ff) << 32)
  130. #define FTMAC110_RXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */
  131. #define FTMAC110_RXD_FRS ((uint64_t)1 << 29) /* first pkt desc */
  132. #define FTMAC110_RXD_LRS ((uint64_t)1 << 28) /* last pkt desc */
  133. #define FTMAC110_RXD_ODDNB ((uint64_t)1 << 22) /* odd nibble */
  134. #define FTMAC110_RXD_RUNT ((uint64_t)1 << 21) /* runt pkt */
  135. #define FTMAC110_RXD_FTL ((uint64_t)1 << 20) /* frame too long */
  136. #define FTMAC110_RXD_CRC ((uint64_t)1 << 19) /* pkt crc error */
  137. #define FTMAC110_RXD_ERR ((uint64_t)1 << 18) /* bus error */
  138. #define FTMAC110_RXD_ERRMASK ((uint64_t)0x1f << 18)
  139. #define FTMAC110_RXD_BCST ((uint64_t)1 << 17) /* Bcst pkt */
  140. #define FTMAC110_RXD_MCST ((uint64_t)1 << 16) /* Mcst pkt */
  141. #define FTMAC110_RXD_LEN(x) ((uint64_t)((x) & 0x7ff))
  142. #define FTMAC110_RXD_CLRMASK \
  143. (FTMAC110_RXD_END | FTMAC110_RXD_BUFSZ(0x7ff))
  144. #define FTMAC110_TXD_END ((uint64_t)1 << 63) /* end of ring */
  145. #define FTMAC110_TXD_TXIC ((uint64_t)1 << 62) /* tx done interrupt */
  146. #define FTMAC110_TXD_TX2FIC ((uint64_t)1 << 61) /* tx fifo interrupt */
  147. #define FTMAC110_TXD_FTS ((uint64_t)1 << 60) /* first pkt desc */
  148. #define FTMAC110_TXD_LTS ((uint64_t)1 << 59) /* last pkt desc */
  149. #define FTMAC110_TXD_LEN(x) ((uint64_t)((x) & 0x7ff) << 32)
  150. #define FTMAC110_TXD_OWNER ((uint64_t)1 << 31) /* owner: 1=HW, 0=SW */
  151. #define FTMAC110_TXD_COL ((uint64_t)3) /* collision */
  152. #define FTMAC110_TXD_CLRMASK \
  153. (FTMAC110_TXD_END)
  154. #endif /* FTMAC110_H */