ftmac110.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Faraday 10/100Mbps Ethernet Controller
  4. *
  5. * (C) Copyright 2013 Faraday Technology
  6. * Dante Su <dantesu@faraday-tech.com>
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <log.h>
  11. #include <malloc.h>
  12. #include <net.h>
  13. #include <asm/cache.h>
  14. #include <linux/errno.h>
  15. #include <asm/io.h>
  16. #include <linux/dma-mapping.h>
  17. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  18. #include <miiphy.h>
  19. #endif
  20. #include "ftmac110.h"
  21. #define CFG_RXDES_NUM 8
  22. #define CFG_TXDES_NUM 2
  23. #define CFG_XBUF_SIZE 1536
  24. #define CFG_MDIORD_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
  25. #define CFG_MDIOWR_TIMEOUT (CONFIG_SYS_HZ >> 1) /* 500 ms */
  26. #define CFG_LINKUP_TIMEOUT (CONFIG_SYS_HZ << 2) /* 4 sec */
  27. /*
  28. * FTMAC110 DMA design issue
  29. *
  30. * Its DMA engine has a weird restriction that its Rx DMA engine
  31. * accepts only 16-bits aligned address, 32-bits aligned is not
  32. * acceptable. However this restriction does not apply to Tx DMA.
  33. *
  34. * Conclusion:
  35. * (1) Tx DMA Buffer Address:
  36. * 1 bytes aligned: Invalid
  37. * 2 bytes aligned: O.K
  38. * 4 bytes aligned: O.K (-> u-boot ZeroCopy is possible)
  39. * (2) Rx DMA Buffer Address:
  40. * 1 bytes aligned: Invalid
  41. * 2 bytes aligned: O.K
  42. * 4 bytes aligned: Invalid
  43. */
  44. struct ftmac110_chip {
  45. void __iomem *regs;
  46. uint32_t imr;
  47. uint32_t maccr;
  48. uint32_t lnkup;
  49. uint32_t phy_addr;
  50. struct ftmac110_desc *rxd;
  51. ulong rxd_dma;
  52. uint32_t rxd_idx;
  53. struct ftmac110_desc *txd;
  54. ulong txd_dma;
  55. uint32_t txd_idx;
  56. };
  57. static int ftmac110_reset(struct eth_device *dev);
  58. static uint16_t mdio_read(struct eth_device *dev,
  59. uint8_t phyaddr, uint8_t phyreg)
  60. {
  61. struct ftmac110_chip *chip = dev->priv;
  62. struct ftmac110_regs *regs = chip->regs;
  63. uint32_t tmp, ts;
  64. uint16_t ret = 0xffff;
  65. tmp = PHYCR_READ
  66. | (phyaddr << PHYCR_ADDR_SHIFT)
  67. | (phyreg << PHYCR_REG_SHIFT);
  68. writel(tmp, &regs->phycr);
  69. for (ts = get_timer(0); get_timer(ts) < CFG_MDIORD_TIMEOUT; ) {
  70. tmp = readl(&regs->phycr);
  71. if (tmp & PHYCR_READ)
  72. continue;
  73. break;
  74. }
  75. if (tmp & PHYCR_READ)
  76. printf("ftmac110: mdio read timeout\n");
  77. else
  78. ret = (uint16_t)(tmp & 0xffff);
  79. return ret;
  80. }
  81. static void mdio_write(struct eth_device *dev,
  82. uint8_t phyaddr, uint8_t phyreg, uint16_t phydata)
  83. {
  84. struct ftmac110_chip *chip = dev->priv;
  85. struct ftmac110_regs *regs = chip->regs;
  86. uint32_t tmp, ts;
  87. tmp = PHYCR_WRITE
  88. | (phyaddr << PHYCR_ADDR_SHIFT)
  89. | (phyreg << PHYCR_REG_SHIFT);
  90. writel(phydata, &regs->phydr);
  91. writel(tmp, &regs->phycr);
  92. for (ts = get_timer(0); get_timer(ts) < CFG_MDIOWR_TIMEOUT; ) {
  93. if (readl(&regs->phycr) & PHYCR_WRITE)
  94. continue;
  95. break;
  96. }
  97. if (readl(&regs->phycr) & PHYCR_WRITE)
  98. printf("ftmac110: mdio write timeout\n");
  99. }
  100. static uint32_t ftmac110_phyqry(struct eth_device *dev)
  101. {
  102. ulong ts;
  103. uint32_t maccr;
  104. uint16_t pa, tmp, bmsr, bmcr;
  105. struct ftmac110_chip *chip = dev->priv;
  106. /* Default = 100Mbps Full */
  107. maccr = MACCR_100M | MACCR_FD;
  108. /* 1. find the phy device */
  109. for (pa = 0; pa < 32; ++pa) {
  110. tmp = mdio_read(dev, pa, MII_PHYSID1);
  111. if (tmp == 0xFFFF || tmp == 0x0000)
  112. continue;
  113. chip->phy_addr = pa;
  114. break;
  115. }
  116. if (pa >= 32) {
  117. puts("ftmac110: phy device not found!\n");
  118. goto exit;
  119. }
  120. /* 2. wait until link-up & auto-negotiation complete */
  121. chip->lnkup = 0;
  122. bmcr = mdio_read(dev, chip->phy_addr, MII_BMCR);
  123. ts = get_timer(0);
  124. do {
  125. bmsr = mdio_read(dev, chip->phy_addr, MII_BMSR);
  126. chip->lnkup = (bmsr & BMSR_LSTATUS) ? 1 : 0;
  127. if (!chip->lnkup)
  128. continue;
  129. if (!(bmcr & BMCR_ANENABLE) || (bmsr & BMSR_ANEGCOMPLETE))
  130. break;
  131. } while (get_timer(ts) < CFG_LINKUP_TIMEOUT);
  132. if (!chip->lnkup) {
  133. puts("ftmac110: link down\n");
  134. goto exit;
  135. }
  136. if (!(bmcr & BMCR_ANENABLE))
  137. puts("ftmac110: auto negotiation disabled\n");
  138. else if (!(bmsr & BMSR_ANEGCOMPLETE))
  139. puts("ftmac110: auto negotiation timeout\n");
  140. /* 3. derive MACCR */
  141. if ((bmcr & BMCR_ANENABLE) && (bmsr & BMSR_ANEGCOMPLETE)) {
  142. tmp = mdio_read(dev, chip->phy_addr, MII_ADVERTISE);
  143. tmp &= mdio_read(dev, chip->phy_addr, MII_LPA);
  144. if (tmp & LPA_100FULL) /* 100Mbps full-duplex */
  145. maccr = MACCR_100M | MACCR_FD;
  146. else if (tmp & LPA_100HALF) /* 100Mbps half-duplex */
  147. maccr = MACCR_100M;
  148. else if (tmp & LPA_10FULL) /* 10Mbps full-duplex */
  149. maccr = MACCR_FD;
  150. else if (tmp & LPA_10HALF) /* 10Mbps half-duplex */
  151. maccr = 0;
  152. } else {
  153. if (bmcr & BMCR_SPEED100)
  154. maccr = MACCR_100M;
  155. else
  156. maccr = 0;
  157. if (bmcr & BMCR_FULLDPLX)
  158. maccr |= MACCR_FD;
  159. }
  160. exit:
  161. printf("ftmac110: %d Mbps, %s\n",
  162. (maccr & MACCR_100M) ? 100 : 10,
  163. (maccr & MACCR_FD) ? "Full" : "half");
  164. return maccr;
  165. }
  166. static int ftmac110_reset(struct eth_device *dev)
  167. {
  168. uint8_t *a;
  169. uint32_t i, maccr;
  170. struct ftmac110_chip *chip = dev->priv;
  171. struct ftmac110_regs *regs = chip->regs;
  172. /* 1. MAC reset */
  173. writel(MACCR_RESET, &regs->maccr);
  174. for (i = get_timer(0); get_timer(i) < 1000; ) {
  175. if (readl(&regs->maccr) & MACCR_RESET)
  176. continue;
  177. break;
  178. }
  179. if (readl(&regs->maccr) & MACCR_RESET) {
  180. printf("ftmac110: reset failed\n");
  181. return -ENXIO;
  182. }
  183. /* 1-1. Init tx ring */
  184. for (i = 0; i < CFG_TXDES_NUM; ++i) {
  185. /* owned by SW */
  186. chip->txd[i].ctrl &= cpu_to_le64(FTMAC110_TXD_CLRMASK);
  187. }
  188. chip->txd_idx = 0;
  189. /* 1-2. Init rx ring */
  190. for (i = 0; i < CFG_RXDES_NUM; ++i) {
  191. /* owned by HW */
  192. chip->rxd[i].ctrl &= cpu_to_le64(FTMAC110_RXD_CLRMASK);
  193. chip->rxd[i].ctrl |= cpu_to_le64(FTMAC110_RXD_OWNER);
  194. }
  195. chip->rxd_idx = 0;
  196. /* 2. PHY status query */
  197. maccr = ftmac110_phyqry(dev);
  198. /* 3. Fix up the MACCR value */
  199. chip->maccr = maccr | MACCR_CRCAPD | MACCR_RXALL | MACCR_RXRUNT
  200. | MACCR_RXEN | MACCR_TXEN | MACCR_RXDMAEN | MACCR_TXDMAEN;
  201. /* 4. MAC address setup */
  202. a = dev->enetaddr;
  203. writel(a[1] | (a[0] << 8), &regs->mac[0]);
  204. writel(a[5] | (a[4] << 8) | (a[3] << 16)
  205. | (a[2] << 24), &regs->mac[1]);
  206. /* 5. MAC registers setup */
  207. writel(chip->rxd_dma, &regs->rxba);
  208. writel(chip->txd_dma, &regs->txba);
  209. /* interrupt at each tx/rx */
  210. writel(ITC_DEFAULT, &regs->itc);
  211. /* no tx pool, rx poll = 1 normal cycle */
  212. writel(APTC_DEFAULT, &regs->aptc);
  213. /* rx threshold = [6/8 fifo, 2/8 fifo] */
  214. writel(DBLAC_DEFAULT, &regs->dblac);
  215. /* disable & clear all interrupt status */
  216. chip->imr = 0;
  217. writel(ISR_ALL, &regs->isr);
  218. writel(chip->imr, &regs->imr);
  219. /* enable mac */
  220. writel(chip->maccr, &regs->maccr);
  221. return 0;
  222. }
  223. static int ftmac110_probe(struct eth_device *dev, struct bd_info *bis)
  224. {
  225. debug("ftmac110: probe\n");
  226. if (ftmac110_reset(dev))
  227. return -1;
  228. return 0;
  229. }
  230. static void ftmac110_halt(struct eth_device *dev)
  231. {
  232. struct ftmac110_chip *chip = dev->priv;
  233. struct ftmac110_regs *regs = chip->regs;
  234. writel(0, &regs->imr);
  235. writel(0, &regs->maccr);
  236. debug("ftmac110: halt\n");
  237. }
  238. static int ftmac110_send(struct eth_device *dev, void *pkt, int len)
  239. {
  240. struct ftmac110_chip *chip = dev->priv;
  241. struct ftmac110_regs *regs = chip->regs;
  242. struct ftmac110_desc *txd;
  243. uint64_t ctrl;
  244. if (!chip->lnkup)
  245. return 0;
  246. if (len <= 0 || len > CFG_XBUF_SIZE) {
  247. printf("ftmac110: bad tx pkt len(%d)\n", len);
  248. return 0;
  249. }
  250. len = max(60, len);
  251. txd = &chip->txd[chip->txd_idx];
  252. ctrl = le64_to_cpu(txd->ctrl);
  253. if (ctrl & FTMAC110_TXD_OWNER) {
  254. /* kick-off Tx DMA */
  255. writel(0xffffffff, &regs->txpd);
  256. printf("ftmac110: out of txd\n");
  257. return 0;
  258. }
  259. memcpy(txd->vbuf, (void *)pkt, len);
  260. dma_map_single(txd->vbuf, len, DMA_TO_DEVICE);
  261. /* clear control bits */
  262. ctrl &= FTMAC110_TXD_CLRMASK;
  263. /* set len, fts and lts */
  264. ctrl |= FTMAC110_TXD_LEN(len) | FTMAC110_TXD_FTS | FTMAC110_TXD_LTS;
  265. /* set owner bit */
  266. ctrl |= FTMAC110_TXD_OWNER;
  267. /* write back to descriptor */
  268. txd->ctrl = cpu_to_le64(ctrl);
  269. /* kick-off Tx DMA */
  270. writel(0xffffffff, &regs->txpd);
  271. chip->txd_idx = (chip->txd_idx + 1) % CFG_TXDES_NUM;
  272. return len;
  273. }
  274. static int ftmac110_recv(struct eth_device *dev)
  275. {
  276. struct ftmac110_chip *chip = dev->priv;
  277. struct ftmac110_desc *rxd;
  278. uint32_t len, rlen = 0;
  279. uint64_t ctrl;
  280. uint8_t *buf;
  281. if (!chip->lnkup)
  282. return 0;
  283. do {
  284. rxd = &chip->rxd[chip->rxd_idx];
  285. ctrl = le64_to_cpu(rxd->ctrl);
  286. if (ctrl & FTMAC110_RXD_OWNER)
  287. break;
  288. len = (uint32_t)FTMAC110_RXD_LEN(ctrl);
  289. buf = rxd->vbuf;
  290. if (ctrl & FTMAC110_RXD_ERRMASK) {
  291. printf("ftmac110: rx error\n");
  292. } else {
  293. dma_map_single(buf, len, DMA_FROM_DEVICE);
  294. net_process_received_packet(buf, len);
  295. rlen += len;
  296. }
  297. /* owned by hardware */
  298. ctrl &= FTMAC110_RXD_CLRMASK;
  299. ctrl |= FTMAC110_RXD_OWNER;
  300. rxd->ctrl |= cpu_to_le64(ctrl);
  301. chip->rxd_idx = (chip->rxd_idx + 1) % CFG_RXDES_NUM;
  302. } while (0);
  303. return rlen;
  304. }
  305. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  306. static int ftmac110_mdio_read(struct mii_dev *bus, int addr, int devad,
  307. int reg)
  308. {
  309. uint16_t value = 0;
  310. int ret = 0;
  311. struct eth_device *dev;
  312. dev = eth_get_dev_by_name(bus->name);
  313. if (dev == NULL) {
  314. printf("%s: no such device\n", bus->name);
  315. ret = -1;
  316. } else {
  317. value = mdio_read(dev, addr, reg);
  318. }
  319. if (ret < 0)
  320. return ret;
  321. return value;
  322. }
  323. static int ftmac110_mdio_write(struct mii_dev *bus, int addr, int devad,
  324. int reg, u16 value)
  325. {
  326. int ret = 0;
  327. struct eth_device *dev;
  328. dev = eth_get_dev_by_name(bus->name);
  329. if (dev == NULL) {
  330. printf("%s: no such device\n", bus->name);
  331. ret = -1;
  332. } else {
  333. mdio_write(dev, addr, reg, value);
  334. }
  335. return ret;
  336. }
  337. #endif /* #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) */
  338. int ftmac110_initialize(struct bd_info *bis)
  339. {
  340. int i, card_nr = 0;
  341. struct eth_device *dev;
  342. struct ftmac110_chip *chip;
  343. dev = malloc(sizeof(*dev) + sizeof(*chip));
  344. if (dev == NULL) {
  345. panic("ftmac110: out of memory 1\n");
  346. return -1;
  347. }
  348. chip = (struct ftmac110_chip *)(dev + 1);
  349. memset(dev, 0, sizeof(*dev) + sizeof(*chip));
  350. sprintf(dev->name, "FTMAC110#%d", card_nr);
  351. dev->iobase = CONFIG_FTMAC110_BASE;
  352. chip->regs = (void __iomem *)dev->iobase;
  353. dev->priv = chip;
  354. dev->init = ftmac110_probe;
  355. dev->halt = ftmac110_halt;
  356. dev->send = ftmac110_send;
  357. dev->recv = ftmac110_recv;
  358. /* allocate tx descriptors (it must be 16 bytes aligned) */
  359. chip->txd = dma_alloc_coherent(
  360. sizeof(struct ftmac110_desc) * CFG_TXDES_NUM, &chip->txd_dma);
  361. if (!chip->txd)
  362. panic("ftmac110: out of memory 3\n");
  363. memset(chip->txd, 0,
  364. sizeof(struct ftmac110_desc) * CFG_TXDES_NUM);
  365. for (i = 0; i < CFG_TXDES_NUM; ++i) {
  366. void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE);
  367. if (!va)
  368. panic("ftmac110: out of memory 4\n");
  369. chip->txd[i].vbuf = va;
  370. chip->txd[i].pbuf = cpu_to_le32(virt_to_phys(va));
  371. chip->txd[i].ctrl = 0; /* owned by SW */
  372. }
  373. chip->txd[i - 1].ctrl |= cpu_to_le64(FTMAC110_TXD_END);
  374. chip->txd_idx = 0;
  375. /* allocate rx descriptors (it must be 16 bytes aligned) */
  376. chip->rxd = dma_alloc_coherent(
  377. sizeof(struct ftmac110_desc) * CFG_RXDES_NUM, &chip->rxd_dma);
  378. if (!chip->rxd)
  379. panic("ftmac110: out of memory 4\n");
  380. memset((void *)chip->rxd, 0,
  381. sizeof(struct ftmac110_desc) * CFG_RXDES_NUM);
  382. for (i = 0; i < CFG_RXDES_NUM; ++i) {
  383. void *va = memalign(ARCH_DMA_MINALIGN, CFG_XBUF_SIZE + 2);
  384. if (!va)
  385. panic("ftmac110: out of memory 5\n");
  386. /* it needs to be exactly 2 bytes aligned */
  387. va = ((uint8_t *)va + 2);
  388. chip->rxd[i].vbuf = va;
  389. chip->rxd[i].pbuf = cpu_to_le32(virt_to_phys(va));
  390. chip->rxd[i].ctrl = cpu_to_le64(FTMAC110_RXD_OWNER
  391. | FTMAC110_RXD_BUFSZ(CFG_XBUF_SIZE));
  392. }
  393. chip->rxd[i - 1].ctrl |= cpu_to_le64(FTMAC110_RXD_END);
  394. chip->rxd_idx = 0;
  395. eth_register(dev);
  396. #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
  397. int retval;
  398. struct mii_dev *mdiodev = mdio_alloc();
  399. if (!mdiodev)
  400. return -ENOMEM;
  401. strncpy(mdiodev->name, dev->name, MDIO_NAME_LEN);
  402. mdiodev->read = ftmac110_mdio_read;
  403. mdiodev->write = ftmac110_mdio_write;
  404. retval = mdio_register(mdiodev);
  405. if (retval < 0)
  406. return retval;
  407. #endif
  408. card_nr++;
  409. return card_nr;
  410. }