designware.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2010
  4. * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
  5. */
  6. /*
  7. * Designware ethernet IP driver for U-Boot
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <cpu_func.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <log.h>
  15. #include <miiphy.h>
  16. #include <malloc.h>
  17. #include <net.h>
  18. #include <pci.h>
  19. #include <reset.h>
  20. #include <asm/cache.h>
  21. #include <dm/device_compat.h>
  22. #include <dm/devres.h>
  23. #include <linux/compiler.h>
  24. #include <linux/delay.h>
  25. #include <linux/err.h>
  26. #include <linux/kernel.h>
  27. #include <asm/io.h>
  28. #include <power/regulator.h>
  29. #include "designware.h"
  30. static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  31. {
  32. #ifdef CONFIG_DM_ETH
  33. struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
  34. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  35. #else
  36. struct eth_mac_regs *mac_p = bus->priv;
  37. #endif
  38. ulong start;
  39. u16 miiaddr;
  40. int timeout = CONFIG_MDIO_TIMEOUT;
  41. miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
  42. ((reg << MIIREGSHIFT) & MII_REGMSK);
  43. writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
  44. start = get_timer(0);
  45. while (get_timer(start) < timeout) {
  46. if (!(readl(&mac_p->miiaddr) & MII_BUSY))
  47. return readl(&mac_p->miidata);
  48. udelay(10);
  49. };
  50. return -ETIMEDOUT;
  51. }
  52. static int dw_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
  53. u16 val)
  54. {
  55. #ifdef CONFIG_DM_ETH
  56. struct dw_eth_dev *priv = dev_get_priv((struct udevice *)bus->priv);
  57. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  58. #else
  59. struct eth_mac_regs *mac_p = bus->priv;
  60. #endif
  61. ulong start;
  62. u16 miiaddr;
  63. int ret = -ETIMEDOUT, timeout = CONFIG_MDIO_TIMEOUT;
  64. writel(val, &mac_p->miidata);
  65. miiaddr = ((addr << MIIADDRSHIFT) & MII_ADDRMSK) |
  66. ((reg << MIIREGSHIFT) & MII_REGMSK) | MII_WRITE;
  67. writel(miiaddr | MII_CLKRANGE_150_250M | MII_BUSY, &mac_p->miiaddr);
  68. start = get_timer(0);
  69. while (get_timer(start) < timeout) {
  70. if (!(readl(&mac_p->miiaddr) & MII_BUSY)) {
  71. ret = 0;
  72. break;
  73. }
  74. udelay(10);
  75. };
  76. return ret;
  77. }
  78. #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
  79. static int dw_mdio_reset(struct mii_dev *bus)
  80. {
  81. struct udevice *dev = bus->priv;
  82. struct dw_eth_dev *priv = dev_get_priv(dev);
  83. struct dw_eth_pdata *pdata = dev_get_platdata(dev);
  84. int ret;
  85. if (!dm_gpio_is_valid(&priv->reset_gpio))
  86. return 0;
  87. /* reset the phy */
  88. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  89. if (ret)
  90. return ret;
  91. udelay(pdata->reset_delays[0]);
  92. ret = dm_gpio_set_value(&priv->reset_gpio, 1);
  93. if (ret)
  94. return ret;
  95. udelay(pdata->reset_delays[1]);
  96. ret = dm_gpio_set_value(&priv->reset_gpio, 0);
  97. if (ret)
  98. return ret;
  99. udelay(pdata->reset_delays[2]);
  100. return 0;
  101. }
  102. #endif
  103. static int dw_mdio_init(const char *name, void *priv)
  104. {
  105. struct mii_dev *bus = mdio_alloc();
  106. if (!bus) {
  107. printf("Failed to allocate MDIO bus\n");
  108. return -ENOMEM;
  109. }
  110. bus->read = dw_mdio_read;
  111. bus->write = dw_mdio_write;
  112. snprintf(bus->name, sizeof(bus->name), "%s", name);
  113. #if defined(CONFIG_DM_ETH) && CONFIG_IS_ENABLED(DM_GPIO)
  114. bus->reset = dw_mdio_reset;
  115. #endif
  116. bus->priv = priv;
  117. return mdio_register(bus);
  118. }
  119. static void tx_descs_init(struct dw_eth_dev *priv)
  120. {
  121. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  122. struct dmamacdescr *desc_table_p = &priv->tx_mac_descrtable[0];
  123. char *txbuffs = &priv->txbuffs[0];
  124. struct dmamacdescr *desc_p;
  125. u32 idx;
  126. for (idx = 0; idx < CONFIG_TX_DESCR_NUM; idx++) {
  127. desc_p = &desc_table_p[idx];
  128. desc_p->dmamac_addr = (ulong)&txbuffs[idx * CONFIG_ETH_BUFSIZE];
  129. desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
  130. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  131. desc_p->txrx_status &= ~(DESC_TXSTS_TXINT | DESC_TXSTS_TXLAST |
  132. DESC_TXSTS_TXFIRST | DESC_TXSTS_TXCRCDIS |
  133. DESC_TXSTS_TXCHECKINSCTRL |
  134. DESC_TXSTS_TXRINGEND | DESC_TXSTS_TXPADDIS);
  135. desc_p->txrx_status |= DESC_TXSTS_TXCHAIN;
  136. desc_p->dmamac_cntl = 0;
  137. desc_p->txrx_status &= ~(DESC_TXSTS_MSK | DESC_TXSTS_OWNBYDMA);
  138. #else
  139. desc_p->dmamac_cntl = DESC_TXCTRL_TXCHAIN;
  140. desc_p->txrx_status = 0;
  141. #endif
  142. }
  143. /* Correcting the last pointer of the chain */
  144. desc_p->dmamac_next = (ulong)&desc_table_p[0];
  145. /* Flush all Tx buffer descriptors at once */
  146. flush_dcache_range((ulong)priv->tx_mac_descrtable,
  147. (ulong)priv->tx_mac_descrtable +
  148. sizeof(priv->tx_mac_descrtable));
  149. writel((ulong)&desc_table_p[0], &dma_p->txdesclistaddr);
  150. priv->tx_currdescnum = 0;
  151. }
  152. static void rx_descs_init(struct dw_eth_dev *priv)
  153. {
  154. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  155. struct dmamacdescr *desc_table_p = &priv->rx_mac_descrtable[0];
  156. char *rxbuffs = &priv->rxbuffs[0];
  157. struct dmamacdescr *desc_p;
  158. u32 idx;
  159. /* Before passing buffers to GMAC we need to make sure zeros
  160. * written there right after "priv" structure allocation were
  161. * flushed into RAM.
  162. * Otherwise there's a chance to get some of them flushed in RAM when
  163. * GMAC is already pushing data to RAM via DMA. This way incoming from
  164. * GMAC data will be corrupted. */
  165. flush_dcache_range((ulong)rxbuffs, (ulong)rxbuffs + RX_TOTAL_BUFSIZE);
  166. for (idx = 0; idx < CONFIG_RX_DESCR_NUM; idx++) {
  167. desc_p = &desc_table_p[idx];
  168. desc_p->dmamac_addr = (ulong)&rxbuffs[idx * CONFIG_ETH_BUFSIZE];
  169. desc_p->dmamac_next = (ulong)&desc_table_p[idx + 1];
  170. desc_p->dmamac_cntl =
  171. (MAC_MAX_FRAME_SZ & DESC_RXCTRL_SIZE1MASK) |
  172. DESC_RXCTRL_RXCHAIN;
  173. desc_p->txrx_status = DESC_RXSTS_OWNBYDMA;
  174. }
  175. /* Correcting the last pointer of the chain */
  176. desc_p->dmamac_next = (ulong)&desc_table_p[0];
  177. /* Flush all Rx buffer descriptors at once */
  178. flush_dcache_range((ulong)priv->rx_mac_descrtable,
  179. (ulong)priv->rx_mac_descrtable +
  180. sizeof(priv->rx_mac_descrtable));
  181. writel((ulong)&desc_table_p[0], &dma_p->rxdesclistaddr);
  182. priv->rx_currdescnum = 0;
  183. }
  184. static int _dw_write_hwaddr(struct dw_eth_dev *priv, u8 *mac_id)
  185. {
  186. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  187. u32 macid_lo, macid_hi;
  188. macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
  189. (mac_id[3] << 24);
  190. macid_hi = mac_id[4] + (mac_id[5] << 8);
  191. writel(macid_hi, &mac_p->macaddr0hi);
  192. writel(macid_lo, &mac_p->macaddr0lo);
  193. return 0;
  194. }
  195. static int dw_adjust_link(struct dw_eth_dev *priv, struct eth_mac_regs *mac_p,
  196. struct phy_device *phydev)
  197. {
  198. u32 conf = readl(&mac_p->conf) | FRAMEBURSTENABLE | DISABLERXOWN;
  199. if (!phydev->link) {
  200. printf("%s: No link.\n", phydev->dev->name);
  201. return 0;
  202. }
  203. if (phydev->speed != 1000)
  204. conf |= MII_PORTSELECT;
  205. else
  206. conf &= ~MII_PORTSELECT;
  207. if (phydev->speed == 100)
  208. conf |= FES_100;
  209. if (phydev->duplex)
  210. conf |= FULLDPLXMODE;
  211. writel(conf, &mac_p->conf);
  212. printf("Speed: %d, %s duplex%s\n", phydev->speed,
  213. (phydev->duplex) ? "full" : "half",
  214. (phydev->port == PORT_FIBRE) ? ", fiber mode" : "");
  215. return 0;
  216. }
  217. static void _dw_eth_halt(struct dw_eth_dev *priv)
  218. {
  219. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  220. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  221. writel(readl(&mac_p->conf) & ~(RXENABLE | TXENABLE), &mac_p->conf);
  222. writel(readl(&dma_p->opmode) & ~(RXSTART | TXSTART), &dma_p->opmode);
  223. phy_shutdown(priv->phydev);
  224. }
  225. int designware_eth_init(struct dw_eth_dev *priv, u8 *enetaddr)
  226. {
  227. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  228. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  229. unsigned int start;
  230. int ret;
  231. writel(readl(&dma_p->busmode) | DMAMAC_SRST, &dma_p->busmode);
  232. /*
  233. * When a MII PHY is used, we must set the PS bit for the DMA
  234. * reset to succeed.
  235. */
  236. if (priv->phydev->interface == PHY_INTERFACE_MODE_MII)
  237. writel(readl(&mac_p->conf) | MII_PORTSELECT, &mac_p->conf);
  238. else
  239. writel(readl(&mac_p->conf) & ~MII_PORTSELECT, &mac_p->conf);
  240. start = get_timer(0);
  241. while (readl(&dma_p->busmode) & DMAMAC_SRST) {
  242. if (get_timer(start) >= CONFIG_MACRESET_TIMEOUT) {
  243. printf("DMA reset timeout\n");
  244. return -ETIMEDOUT;
  245. }
  246. mdelay(100);
  247. };
  248. /*
  249. * Soft reset above clears HW address registers.
  250. * So we have to set it here once again.
  251. */
  252. _dw_write_hwaddr(priv, enetaddr);
  253. rx_descs_init(priv);
  254. tx_descs_init(priv);
  255. writel(FIXEDBURST | PRIORXTX_41 | DMA_PBL, &dma_p->busmode);
  256. #ifndef CONFIG_DW_MAC_FORCE_THRESHOLD_MODE
  257. writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD,
  258. &dma_p->opmode);
  259. #else
  260. writel(readl(&dma_p->opmode) | FLUSHTXFIFO,
  261. &dma_p->opmode);
  262. #endif
  263. writel(readl(&dma_p->opmode) | RXSTART | TXSTART, &dma_p->opmode);
  264. #ifdef CONFIG_DW_AXI_BURST_LEN
  265. writel((CONFIG_DW_AXI_BURST_LEN & 0x1FF >> 1), &dma_p->axibus);
  266. #endif
  267. /* Start up the PHY */
  268. ret = phy_startup(priv->phydev);
  269. if (ret) {
  270. printf("Could not initialize PHY %s\n",
  271. priv->phydev->dev->name);
  272. return ret;
  273. }
  274. ret = dw_adjust_link(priv, mac_p, priv->phydev);
  275. if (ret)
  276. return ret;
  277. return 0;
  278. }
  279. int designware_eth_enable(struct dw_eth_dev *priv)
  280. {
  281. struct eth_mac_regs *mac_p = priv->mac_regs_p;
  282. if (!priv->phydev->link)
  283. return -EIO;
  284. writel(readl(&mac_p->conf) | RXENABLE | TXENABLE, &mac_p->conf);
  285. return 0;
  286. }
  287. #define ETH_ZLEN 60
  288. static int _dw_eth_send(struct dw_eth_dev *priv, void *packet, int length)
  289. {
  290. struct eth_dma_regs *dma_p = priv->dma_regs_p;
  291. u32 desc_num = priv->tx_currdescnum;
  292. struct dmamacdescr *desc_p = &priv->tx_mac_descrtable[desc_num];
  293. ulong desc_start = (ulong)desc_p;
  294. ulong desc_end = desc_start +
  295. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  296. ulong data_start = desc_p->dmamac_addr;
  297. ulong data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
  298. /*
  299. * Strictly we only need to invalidate the "txrx_status" field
  300. * for the following check, but on some platforms we cannot
  301. * invalidate only 4 bytes, so we flush the entire descriptor,
  302. * which is 16 bytes in total. This is safe because the
  303. * individual descriptors in the array are each aligned to
  304. * ARCH_DMA_MINALIGN and padded appropriately.
  305. */
  306. invalidate_dcache_range(desc_start, desc_end);
  307. /* Check if the descriptor is owned by CPU */
  308. if (desc_p->txrx_status & DESC_TXSTS_OWNBYDMA) {
  309. printf("CPU not owner of tx frame\n");
  310. return -EPERM;
  311. }
  312. memcpy((void *)data_start, packet, length);
  313. if (length < ETH_ZLEN) {
  314. memset(&((char *)data_start)[length], 0, ETH_ZLEN - length);
  315. length = ETH_ZLEN;
  316. }
  317. /* Flush data to be sent */
  318. flush_dcache_range(data_start, data_end);
  319. #if defined(CONFIG_DW_ALTDESCRIPTOR)
  320. desc_p->txrx_status |= DESC_TXSTS_TXFIRST | DESC_TXSTS_TXLAST;
  321. desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
  322. ((length << DESC_TXCTRL_SIZE1SHFT) &
  323. DESC_TXCTRL_SIZE1MASK);
  324. desc_p->txrx_status &= ~(DESC_TXSTS_MSK);
  325. desc_p->txrx_status |= DESC_TXSTS_OWNBYDMA;
  326. #else
  327. desc_p->dmamac_cntl = (desc_p->dmamac_cntl & ~DESC_TXCTRL_SIZE1MASK) |
  328. ((length << DESC_TXCTRL_SIZE1SHFT) &
  329. DESC_TXCTRL_SIZE1MASK) | DESC_TXCTRL_TXLAST |
  330. DESC_TXCTRL_TXFIRST;
  331. desc_p->txrx_status = DESC_TXSTS_OWNBYDMA;
  332. #endif
  333. /* Flush modified buffer descriptor */
  334. flush_dcache_range(desc_start, desc_end);
  335. /* Test the wrap-around condition. */
  336. if (++desc_num >= CONFIG_TX_DESCR_NUM)
  337. desc_num = 0;
  338. priv->tx_currdescnum = desc_num;
  339. /* Start the transmission */
  340. writel(POLL_DATA, &dma_p->txpolldemand);
  341. return 0;
  342. }
  343. static int _dw_eth_recv(struct dw_eth_dev *priv, uchar **packetp)
  344. {
  345. u32 status, desc_num = priv->rx_currdescnum;
  346. struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
  347. int length = -EAGAIN;
  348. ulong desc_start = (ulong)desc_p;
  349. ulong desc_end = desc_start +
  350. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  351. ulong data_start = desc_p->dmamac_addr;
  352. ulong data_end;
  353. /* Invalidate entire buffer descriptor */
  354. invalidate_dcache_range(desc_start, desc_end);
  355. status = desc_p->txrx_status;
  356. /* Check if the owner is the CPU */
  357. if (!(status & DESC_RXSTS_OWNBYDMA)) {
  358. length = (status & DESC_RXSTS_FRMLENMSK) >>
  359. DESC_RXSTS_FRMLENSHFT;
  360. /* Invalidate received data */
  361. data_end = data_start + roundup(length, ARCH_DMA_MINALIGN);
  362. invalidate_dcache_range(data_start, data_end);
  363. *packetp = (uchar *)(ulong)desc_p->dmamac_addr;
  364. }
  365. return length;
  366. }
  367. static int _dw_free_pkt(struct dw_eth_dev *priv)
  368. {
  369. u32 desc_num = priv->rx_currdescnum;
  370. struct dmamacdescr *desc_p = &priv->rx_mac_descrtable[desc_num];
  371. ulong desc_start = (ulong)desc_p;
  372. ulong desc_end = desc_start +
  373. roundup(sizeof(*desc_p), ARCH_DMA_MINALIGN);
  374. /*
  375. * Make the current descriptor valid again and go to
  376. * the next one
  377. */
  378. desc_p->txrx_status |= DESC_RXSTS_OWNBYDMA;
  379. /* Flush only status field - others weren't changed */
  380. flush_dcache_range(desc_start, desc_end);
  381. /* Test the wrap-around condition. */
  382. if (++desc_num >= CONFIG_RX_DESCR_NUM)
  383. desc_num = 0;
  384. priv->rx_currdescnum = desc_num;
  385. return 0;
  386. }
  387. static int dw_phy_init(struct dw_eth_dev *priv, void *dev)
  388. {
  389. struct phy_device *phydev;
  390. int phy_addr = -1, ret;
  391. #ifdef CONFIG_PHY_ADDR
  392. phy_addr = CONFIG_PHY_ADDR;
  393. #endif
  394. phydev = phy_connect(priv->bus, phy_addr, dev, priv->interface);
  395. if (!phydev)
  396. return -ENODEV;
  397. phydev->supported &= PHY_GBIT_FEATURES;
  398. if (priv->max_speed) {
  399. ret = phy_set_supported(phydev, priv->max_speed);
  400. if (ret)
  401. return ret;
  402. }
  403. phydev->advertising = phydev->supported;
  404. priv->phydev = phydev;
  405. phy_config(phydev);
  406. return 0;
  407. }
  408. #ifndef CONFIG_DM_ETH
  409. static int dw_eth_init(struct eth_device *dev, struct bd_info *bis)
  410. {
  411. int ret;
  412. ret = designware_eth_init(dev->priv, dev->enetaddr);
  413. if (!ret)
  414. ret = designware_eth_enable(dev->priv);
  415. return ret;
  416. }
  417. static int dw_eth_send(struct eth_device *dev, void *packet, int length)
  418. {
  419. return _dw_eth_send(dev->priv, packet, length);
  420. }
  421. static int dw_eth_recv(struct eth_device *dev)
  422. {
  423. uchar *packet;
  424. int length;
  425. length = _dw_eth_recv(dev->priv, &packet);
  426. if (length == -EAGAIN)
  427. return 0;
  428. net_process_received_packet(packet, length);
  429. _dw_free_pkt(dev->priv);
  430. return 0;
  431. }
  432. static void dw_eth_halt(struct eth_device *dev)
  433. {
  434. return _dw_eth_halt(dev->priv);
  435. }
  436. static int dw_write_hwaddr(struct eth_device *dev)
  437. {
  438. return _dw_write_hwaddr(dev->priv, dev->enetaddr);
  439. }
  440. int designware_initialize(ulong base_addr, u32 interface)
  441. {
  442. struct eth_device *dev;
  443. struct dw_eth_dev *priv;
  444. dev = (struct eth_device *) malloc(sizeof(struct eth_device));
  445. if (!dev)
  446. return -ENOMEM;
  447. /*
  448. * Since the priv structure contains the descriptors which need a strict
  449. * buswidth alignment, memalign is used to allocate memory
  450. */
  451. priv = (struct dw_eth_dev *) memalign(ARCH_DMA_MINALIGN,
  452. sizeof(struct dw_eth_dev));
  453. if (!priv) {
  454. free(dev);
  455. return -ENOMEM;
  456. }
  457. if ((phys_addr_t)priv + sizeof(*priv) > (1ULL << 32)) {
  458. printf("designware: buffers are outside DMA memory\n");
  459. return -EINVAL;
  460. }
  461. memset(dev, 0, sizeof(struct eth_device));
  462. memset(priv, 0, sizeof(struct dw_eth_dev));
  463. sprintf(dev->name, "dwmac.%lx", base_addr);
  464. dev->iobase = (int)base_addr;
  465. dev->priv = priv;
  466. priv->dev = dev;
  467. priv->mac_regs_p = (struct eth_mac_regs *)base_addr;
  468. priv->dma_regs_p = (struct eth_dma_regs *)(base_addr +
  469. DW_DMA_BASE_OFFSET);
  470. dev->init = dw_eth_init;
  471. dev->send = dw_eth_send;
  472. dev->recv = dw_eth_recv;
  473. dev->halt = dw_eth_halt;
  474. dev->write_hwaddr = dw_write_hwaddr;
  475. eth_register(dev);
  476. priv->interface = interface;
  477. dw_mdio_init(dev->name, priv->mac_regs_p);
  478. priv->bus = miiphy_get_dev_by_name(dev->name);
  479. return dw_phy_init(priv, dev);
  480. }
  481. #endif
  482. #ifdef CONFIG_DM_ETH
  483. static int designware_eth_start(struct udevice *dev)
  484. {
  485. struct eth_pdata *pdata = dev_get_platdata(dev);
  486. struct dw_eth_dev *priv = dev_get_priv(dev);
  487. int ret;
  488. ret = designware_eth_init(priv, pdata->enetaddr);
  489. if (ret)
  490. return ret;
  491. ret = designware_eth_enable(priv);
  492. if (ret)
  493. return ret;
  494. return 0;
  495. }
  496. int designware_eth_send(struct udevice *dev, void *packet, int length)
  497. {
  498. struct dw_eth_dev *priv = dev_get_priv(dev);
  499. return _dw_eth_send(priv, packet, length);
  500. }
  501. int designware_eth_recv(struct udevice *dev, int flags, uchar **packetp)
  502. {
  503. struct dw_eth_dev *priv = dev_get_priv(dev);
  504. return _dw_eth_recv(priv, packetp);
  505. }
  506. int designware_eth_free_pkt(struct udevice *dev, uchar *packet, int length)
  507. {
  508. struct dw_eth_dev *priv = dev_get_priv(dev);
  509. return _dw_free_pkt(priv);
  510. }
  511. void designware_eth_stop(struct udevice *dev)
  512. {
  513. struct dw_eth_dev *priv = dev_get_priv(dev);
  514. return _dw_eth_halt(priv);
  515. }
  516. int designware_eth_write_hwaddr(struct udevice *dev)
  517. {
  518. struct eth_pdata *pdata = dev_get_platdata(dev);
  519. struct dw_eth_dev *priv = dev_get_priv(dev);
  520. return _dw_write_hwaddr(priv, pdata->enetaddr);
  521. }
  522. static int designware_eth_bind(struct udevice *dev)
  523. {
  524. #ifdef CONFIG_DM_PCI
  525. static int num_cards;
  526. char name[20];
  527. /* Create a unique device name for PCI type devices */
  528. if (device_is_on_pci_bus(dev)) {
  529. sprintf(name, "eth_designware#%u", num_cards++);
  530. device_set_name(dev, name);
  531. }
  532. #endif
  533. return 0;
  534. }
  535. int designware_eth_probe(struct udevice *dev)
  536. {
  537. struct eth_pdata *pdata = dev_get_platdata(dev);
  538. struct dw_eth_dev *priv = dev_get_priv(dev);
  539. u32 iobase = pdata->iobase;
  540. ulong ioaddr;
  541. int ret, err;
  542. struct reset_ctl_bulk reset_bulk;
  543. #ifdef CONFIG_CLK
  544. int i, clock_nb;
  545. priv->clock_count = 0;
  546. clock_nb = dev_count_phandle_with_args(dev, "clocks", "#clock-cells");
  547. if (clock_nb > 0) {
  548. priv->clocks = devm_kcalloc(dev, clock_nb, sizeof(struct clk),
  549. GFP_KERNEL);
  550. if (!priv->clocks)
  551. return -ENOMEM;
  552. for (i = 0; i < clock_nb; i++) {
  553. err = clk_get_by_index(dev, i, &priv->clocks[i]);
  554. if (err < 0)
  555. break;
  556. err = clk_enable(&priv->clocks[i]);
  557. if (err && err != -ENOSYS && err != -ENOTSUPP) {
  558. pr_err("failed to enable clock %d\n", i);
  559. clk_free(&priv->clocks[i]);
  560. goto clk_err;
  561. }
  562. priv->clock_count++;
  563. }
  564. } else if (clock_nb != -ENOENT) {
  565. pr_err("failed to get clock phandle(%d)\n", clock_nb);
  566. return clock_nb;
  567. }
  568. #endif
  569. #if defined(CONFIG_DM_REGULATOR)
  570. struct udevice *phy_supply;
  571. ret = device_get_supply_regulator(dev, "phy-supply",
  572. &phy_supply);
  573. if (ret) {
  574. debug("%s: No phy supply\n", dev->name);
  575. } else {
  576. ret = regulator_set_enable(phy_supply, true);
  577. if (ret) {
  578. puts("Error enabling phy supply\n");
  579. return ret;
  580. }
  581. }
  582. #endif
  583. ret = reset_get_bulk(dev, &reset_bulk);
  584. if (ret)
  585. dev_warn(dev, "Can't get reset: %d\n", ret);
  586. else
  587. reset_deassert_bulk(&reset_bulk);
  588. #ifdef CONFIG_DM_PCI
  589. /*
  590. * If we are on PCI bus, either directly attached to a PCI root port,
  591. * or via a PCI bridge, fill in platdata before we probe the hardware.
  592. */
  593. if (device_is_on_pci_bus(dev)) {
  594. dm_pci_read_config32(dev, PCI_BASE_ADDRESS_0, &iobase);
  595. iobase &= PCI_BASE_ADDRESS_MEM_MASK;
  596. iobase = dm_pci_mem_to_phys(dev, iobase);
  597. pdata->iobase = iobase;
  598. pdata->phy_interface = PHY_INTERFACE_MODE_RMII;
  599. }
  600. #endif
  601. debug("%s, iobase=%x, priv=%p\n", __func__, iobase, priv);
  602. ioaddr = iobase;
  603. priv->mac_regs_p = (struct eth_mac_regs *)ioaddr;
  604. priv->dma_regs_p = (struct eth_dma_regs *)(ioaddr + DW_DMA_BASE_OFFSET);
  605. priv->interface = pdata->phy_interface;
  606. priv->max_speed = pdata->max_speed;
  607. ret = dw_mdio_init(dev->name, dev);
  608. if (ret) {
  609. err = ret;
  610. goto mdio_err;
  611. }
  612. priv->bus = miiphy_get_dev_by_name(dev->name);
  613. ret = dw_phy_init(priv, dev);
  614. debug("%s, ret=%d\n", __func__, ret);
  615. if (!ret)
  616. return 0;
  617. /* continue here for cleanup if no PHY found */
  618. err = ret;
  619. mdio_unregister(priv->bus);
  620. mdio_free(priv->bus);
  621. mdio_err:
  622. #ifdef CONFIG_CLK
  623. clk_err:
  624. ret = clk_release_all(priv->clocks, priv->clock_count);
  625. if (ret)
  626. pr_err("failed to disable all clocks\n");
  627. #endif
  628. return err;
  629. }
  630. static int designware_eth_remove(struct udevice *dev)
  631. {
  632. struct dw_eth_dev *priv = dev_get_priv(dev);
  633. free(priv->phydev);
  634. mdio_unregister(priv->bus);
  635. mdio_free(priv->bus);
  636. #ifdef CONFIG_CLK
  637. return clk_release_all(priv->clocks, priv->clock_count);
  638. #else
  639. return 0;
  640. #endif
  641. }
  642. const struct eth_ops designware_eth_ops = {
  643. .start = designware_eth_start,
  644. .send = designware_eth_send,
  645. .recv = designware_eth_recv,
  646. .free_pkt = designware_eth_free_pkt,
  647. .stop = designware_eth_stop,
  648. .write_hwaddr = designware_eth_write_hwaddr,
  649. };
  650. int designware_eth_ofdata_to_platdata(struct udevice *dev)
  651. {
  652. struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
  653. #if CONFIG_IS_ENABLED(DM_GPIO)
  654. struct dw_eth_dev *priv = dev_get_priv(dev);
  655. #endif
  656. struct eth_pdata *pdata = &dw_pdata->eth_pdata;
  657. const char *phy_mode;
  658. #if CONFIG_IS_ENABLED(DM_GPIO)
  659. int reset_flags = GPIOD_IS_OUT;
  660. #endif
  661. int ret = 0;
  662. pdata->iobase = dev_read_addr(dev);
  663. pdata->phy_interface = -1;
  664. phy_mode = dev_read_string(dev, "phy-mode");
  665. if (phy_mode)
  666. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  667. if (pdata->phy_interface == -1) {
  668. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  669. return -EINVAL;
  670. }
  671. pdata->max_speed = dev_read_u32_default(dev, "max-speed", 0);
  672. #if CONFIG_IS_ENABLED(DM_GPIO)
  673. if (dev_read_bool(dev, "snps,reset-active-low"))
  674. reset_flags |= GPIOD_ACTIVE_LOW;
  675. ret = gpio_request_by_name(dev, "snps,reset-gpio", 0,
  676. &priv->reset_gpio, reset_flags);
  677. if (ret == 0) {
  678. ret = dev_read_u32_array(dev, "snps,reset-delays-us",
  679. dw_pdata->reset_delays, 3);
  680. } else if (ret == -ENOENT) {
  681. ret = 0;
  682. }
  683. #endif
  684. return ret;
  685. }
  686. static const struct udevice_id designware_eth_ids[] = {
  687. { .compatible = "allwinner,sun7i-a20-gmac" },
  688. { .compatible = "amlogic,meson6-dwmac" },
  689. { .compatible = "amlogic,meson-gx-dwmac" },
  690. { .compatible = "amlogic,meson-gxbb-dwmac" },
  691. { .compatible = "amlogic,meson-axg-dwmac" },
  692. { .compatible = "st,stm32-dwmac" },
  693. { .compatible = "snps,arc-dwmac-3.70a" },
  694. { }
  695. };
  696. U_BOOT_DRIVER(eth_designware) = {
  697. .name = "eth_designware",
  698. .id = UCLASS_ETH,
  699. .of_match = designware_eth_ids,
  700. .ofdata_to_platdata = designware_eth_ofdata_to_platdata,
  701. .bind = designware_eth_bind,
  702. .probe = designware_eth_probe,
  703. .remove = designware_eth_remove,
  704. .ops = &designware_eth_ops,
  705. .priv_auto_alloc_size = sizeof(struct dw_eth_dev),
  706. .platdata_auto_alloc_size = sizeof(struct dw_eth_pdata),
  707. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  708. };
  709. static struct pci_device_id supported[] = {
  710. { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
  711. { }
  712. };
  713. U_BOOT_PCI_DEVICE(eth_designware, supported);
  714. #endif