bcmgenet.c 21 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2019 Amit Singh Tomar <amittomer25@gmail.com>
  4. *
  5. * Driver for Broadcom GENETv5 Ethernet controller (as found on the RPi4)
  6. * This driver is based on the Linux driver:
  7. * drivers/net/ethernet/broadcom/genet/bcmgenet.c
  8. * which is: Copyright (c) 2014-2017 Broadcom
  9. *
  10. * The hardware supports multiple queues (16 priority queues and one
  11. * default queue), both for RX and TX. There are 256 DMA descriptors (both
  12. * for TX and RX), and they live in MMIO registers. The hardware allows
  13. * assigning descriptor ranges to queues, but we choose the most simple setup:
  14. * All 256 descriptors are assigned to the default queue (#16).
  15. * Also the Linux driver supports multiple generations of the MAC, whereas
  16. * we only support v5, as used in the Raspberry Pi 4.
  17. */
  18. #include <log.h>
  19. #include <asm/cache.h>
  20. #include <asm/io.h>
  21. #include <clk.h>
  22. #include <cpu_func.h>
  23. #include <dm.h>
  24. #include <fdt_support.h>
  25. #include <linux/bitops.h>
  26. #include <linux/delay.h>
  27. #include <linux/err.h>
  28. #include <malloc.h>
  29. #include <miiphy.h>
  30. #include <net.h>
  31. #include <dm/of_access.h>
  32. #include <dm/ofnode.h>
  33. #include <linux/iopoll.h>
  34. #include <linux/sizes.h>
  35. #include <asm/dma-mapping.h>
  36. #include <wait_bit.h>
  37. /* Register definitions derived from Linux source */
  38. #define SYS_REV_CTRL 0x00
  39. #define SYS_PORT_CTRL 0x04
  40. #define PORT_MODE_EXT_GPHY 3
  41. #define GENET_SYS_OFF 0x0000
  42. #define SYS_RBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x08)
  43. #define SYS_TBUF_FLUSH_CTRL (GENET_SYS_OFF + 0x0c)
  44. #define GENET_EXT_OFF 0x0080
  45. #define EXT_RGMII_OOB_CTRL (GENET_EXT_OFF + 0x0c)
  46. #define RGMII_LINK BIT(4)
  47. #define OOB_DISABLE BIT(5)
  48. #define RGMII_MODE_EN BIT(6)
  49. #define ID_MODE_DIS BIT(16)
  50. #define GENET_RBUF_OFF 0x0300
  51. #define RBUF_TBUF_SIZE_CTRL (GENET_RBUF_OFF + 0xb4)
  52. #define RBUF_CTRL (GENET_RBUF_OFF + 0x00)
  53. #define RBUF_ALIGN_2B BIT(1)
  54. #define GENET_UMAC_OFF 0x0800
  55. #define UMAC_MIB_CTRL (GENET_UMAC_OFF + 0x580)
  56. #define UMAC_MAX_FRAME_LEN (GENET_UMAC_OFF + 0x014)
  57. #define UMAC_MAC0 (GENET_UMAC_OFF + 0x00c)
  58. #define UMAC_MAC1 (GENET_UMAC_OFF + 0x010)
  59. #define UMAC_CMD (GENET_UMAC_OFF + 0x008)
  60. #define MDIO_CMD (GENET_UMAC_OFF + 0x614)
  61. #define UMAC_TX_FLUSH (GENET_UMAC_OFF + 0x334)
  62. #define MDIO_START_BUSY BIT(29)
  63. #define MDIO_READ_FAIL BIT(28)
  64. #define MDIO_RD (2 << 26)
  65. #define MDIO_WR BIT(26)
  66. #define MDIO_PMD_SHIFT 21
  67. #define MDIO_PMD_MASK 0x1f
  68. #define MDIO_REG_SHIFT 16
  69. #define MDIO_REG_MASK 0x1f
  70. #define CMD_TX_EN BIT(0)
  71. #define CMD_RX_EN BIT(1)
  72. #define UMAC_SPEED_10 0
  73. #define UMAC_SPEED_100 1
  74. #define UMAC_SPEED_1000 2
  75. #define UMAC_SPEED_2500 3
  76. #define CMD_SPEED_SHIFT 2
  77. #define CMD_SPEED_MASK 3
  78. #define CMD_SW_RESET BIT(13)
  79. #define CMD_LCL_LOOP_EN BIT(15)
  80. #define CMD_TX_EN BIT(0)
  81. #define CMD_RX_EN BIT(1)
  82. #define MIB_RESET_RX BIT(0)
  83. #define MIB_RESET_RUNT BIT(1)
  84. #define MIB_RESET_TX BIT(2)
  85. /* total number of Buffer Descriptors, same for Rx/Tx */
  86. #define TOTAL_DESCS 256
  87. #define RX_DESCS TOTAL_DESCS
  88. #define TX_DESCS TOTAL_DESCS
  89. #define DEFAULT_Q 0x10
  90. /* Body(1500) + EH_SIZE(14) + VLANTAG(4) + BRCMTAG(6) + FCS(4) = 1528.
  91. * 1536 is multiple of 256 bytes
  92. */
  93. #define ENET_BRCM_TAG_LEN 6
  94. #define ENET_PAD 8
  95. #define ENET_MAX_MTU_SIZE (ETH_DATA_LEN + ETH_HLEN + \
  96. VLAN_HLEN + ENET_BRCM_TAG_LEN + \
  97. ETH_FCS_LEN + ENET_PAD)
  98. /* Tx/Rx Dma Descriptor common bits */
  99. #define DMA_EN BIT(0)
  100. #define DMA_RING_BUF_EN_SHIFT 0x01
  101. #define DMA_RING_BUF_EN_MASK 0xffff
  102. #define DMA_BUFLENGTH_MASK 0x0fff
  103. #define DMA_BUFLENGTH_SHIFT 16
  104. #define DMA_RING_SIZE_SHIFT 16
  105. #define DMA_OWN 0x8000
  106. #define DMA_EOP 0x4000
  107. #define DMA_SOP 0x2000
  108. #define DMA_WRAP 0x1000
  109. #define DMA_MAX_BURST_LENGTH 0x8
  110. /* Tx specific DMA descriptor bits */
  111. #define DMA_TX_UNDERRUN 0x0200
  112. #define DMA_TX_APPEND_CRC 0x0040
  113. #define DMA_TX_OW_CRC 0x0020
  114. #define DMA_TX_DO_CSUM 0x0010
  115. #define DMA_TX_QTAG_SHIFT 7
  116. /* DMA rings size */
  117. #define DMA_RING_SIZE 0x40
  118. #define DMA_RINGS_SIZE (DMA_RING_SIZE * (DEFAULT_Q + 1))
  119. /* DMA descriptor */
  120. #define DMA_DESC_LENGTH_STATUS 0x00
  121. #define DMA_DESC_ADDRESS_LO 0x04
  122. #define DMA_DESC_ADDRESS_HI 0x08
  123. #define DMA_DESC_SIZE 12
  124. #define GENET_RX_OFF 0x2000
  125. #define GENET_RDMA_REG_OFF \
  126. (GENET_RX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
  127. #define GENET_TX_OFF 0x4000
  128. #define GENET_TDMA_REG_OFF \
  129. (GENET_TX_OFF + TOTAL_DESCS * DMA_DESC_SIZE)
  130. #define DMA_FC_THRESH_HI (RX_DESCS >> 4)
  131. #define DMA_FC_THRESH_LO 5
  132. #define DMA_FC_THRESH_VALUE ((DMA_FC_THRESH_LO << 16) | \
  133. DMA_FC_THRESH_HI)
  134. #define DMA_XOFF_THRESHOLD_SHIFT 16
  135. #define TDMA_RING_REG_BASE \
  136. (GENET_TDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
  137. #define TDMA_READ_PTR (TDMA_RING_REG_BASE + 0x00)
  138. #define TDMA_CONS_INDEX (TDMA_RING_REG_BASE + 0x08)
  139. #define TDMA_PROD_INDEX (TDMA_RING_REG_BASE + 0x0c)
  140. #define DMA_RING_BUF_SIZE 0x10
  141. #define DMA_START_ADDR 0x14
  142. #define DMA_END_ADDR 0x1c
  143. #define DMA_MBUF_DONE_THRESH 0x24
  144. #define TDMA_FLOW_PERIOD (TDMA_RING_REG_BASE + 0x28)
  145. #define TDMA_WRITE_PTR (TDMA_RING_REG_BASE + 0x2c)
  146. #define RDMA_RING_REG_BASE \
  147. (GENET_RDMA_REG_OFF + DEFAULT_Q * DMA_RING_SIZE)
  148. #define RDMA_WRITE_PTR (RDMA_RING_REG_BASE + 0x00)
  149. #define RDMA_PROD_INDEX (RDMA_RING_REG_BASE + 0x08)
  150. #define RDMA_CONS_INDEX (RDMA_RING_REG_BASE + 0x0c)
  151. #define RDMA_XON_XOFF_THRESH (RDMA_RING_REG_BASE + 0x28)
  152. #define RDMA_READ_PTR (RDMA_RING_REG_BASE + 0x2c)
  153. #define TDMA_REG_BASE (GENET_TDMA_REG_OFF + DMA_RINGS_SIZE)
  154. #define RDMA_REG_BASE (GENET_RDMA_REG_OFF + DMA_RINGS_SIZE)
  155. #define DMA_RING_CFG 0x00
  156. #define DMA_CTRL 0x04
  157. #define DMA_SCB_BURST_SIZE 0x0c
  158. #define RX_BUF_LENGTH 2048
  159. #define RX_TOTAL_BUFSIZE (RX_BUF_LENGTH * RX_DESCS)
  160. #define RX_BUF_OFFSET 2
  161. struct bcmgenet_eth_priv {
  162. char rxbuffer[RX_TOTAL_BUFSIZE] __aligned(ARCH_DMA_MINALIGN);
  163. void *mac_reg;
  164. void *tx_desc_base;
  165. void *rx_desc_base;
  166. int tx_index;
  167. int rx_index;
  168. int c_index;
  169. int phyaddr;
  170. u32 interface;
  171. u32 speed;
  172. struct phy_device *phydev;
  173. struct mii_dev *bus;
  174. };
  175. static void bcmgenet_umac_reset(struct bcmgenet_eth_priv *priv)
  176. {
  177. u32 reg;
  178. reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL);
  179. reg |= BIT(1);
  180. writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
  181. udelay(10);
  182. reg &= ~BIT(1);
  183. writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
  184. udelay(10);
  185. writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL));
  186. udelay(10);
  187. writel(0, priv->mac_reg + UMAC_CMD);
  188. writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD);
  189. udelay(2);
  190. writel(0, priv->mac_reg + UMAC_CMD);
  191. /* clear tx/rx counter */
  192. writel(MIB_RESET_RX | MIB_RESET_TX | MIB_RESET_RUNT,
  193. priv->mac_reg + UMAC_MIB_CTRL);
  194. writel(0, priv->mac_reg + UMAC_MIB_CTRL);
  195. writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN);
  196. /* init rx registers, enable ip header optimization */
  197. reg = readl(priv->mac_reg + RBUF_CTRL);
  198. reg |= RBUF_ALIGN_2B;
  199. writel(reg, (priv->mac_reg + RBUF_CTRL));
  200. writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL));
  201. }
  202. static int bcmgenet_gmac_write_hwaddr(struct udevice *dev)
  203. {
  204. struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
  205. struct eth_pdata *pdata = dev_get_platdata(dev);
  206. uchar *addr = pdata->enetaddr;
  207. u32 reg;
  208. reg = addr[0] << 24 | addr[1] << 16 | addr[2] << 8 | addr[3];
  209. writel_relaxed(reg, priv->mac_reg + UMAC_MAC0);
  210. reg = addr[4] << 8 | addr[5];
  211. writel_relaxed(reg, priv->mac_reg + UMAC_MAC1);
  212. return 0;
  213. }
  214. static void bcmgenet_disable_dma(struct bcmgenet_eth_priv *priv)
  215. {
  216. clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN);
  217. clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN);
  218. writel(1, priv->mac_reg + UMAC_TX_FLUSH);
  219. udelay(10);
  220. writel(0, priv->mac_reg + UMAC_TX_FLUSH);
  221. }
  222. static void bcmgenet_enable_dma(struct bcmgenet_eth_priv *priv)
  223. {
  224. u32 dma_ctrl = (1 << (DEFAULT_Q + DMA_RING_BUF_EN_SHIFT)) | DMA_EN;
  225. writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL);
  226. setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl);
  227. }
  228. static int bcmgenet_gmac_eth_send(struct udevice *dev, void *packet, int length)
  229. {
  230. struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
  231. void *desc_base = priv->tx_desc_base + priv->tx_index * DMA_DESC_SIZE;
  232. u32 len_stat = length << DMA_BUFLENGTH_SHIFT;
  233. ulong packet_aligned = rounddown((ulong)packet, ARCH_DMA_MINALIGN);
  234. u32 prod_index, cons;
  235. u32 tries = 100;
  236. prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX);
  237. /* There is actually no reason for the rounding here, but the ARMv7
  238. * implementation of flush_dcache_range() checks for aligned
  239. * boundaries of the flushed range.
  240. * Adjust them here to pass that check and avoid misleading messages.
  241. */
  242. flush_dcache_range(packet_aligned,
  243. packet_aligned + roundup(length, ARCH_DMA_MINALIGN));
  244. len_stat |= 0x3F << DMA_TX_QTAG_SHIFT;
  245. len_stat |= DMA_TX_APPEND_CRC | DMA_SOP | DMA_EOP;
  246. /* Set-up packet for transmission */
  247. writel(lower_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_LO));
  248. writel(upper_32_bits((ulong)packet), (desc_base + DMA_DESC_ADDRESS_HI));
  249. writel(len_stat, (desc_base + DMA_DESC_LENGTH_STATUS));
  250. /* Increment index and start transmission */
  251. if (++priv->tx_index >= TX_DESCS)
  252. priv->tx_index = 0;
  253. prod_index++;
  254. /* Start Transmisson */
  255. writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX);
  256. do {
  257. cons = readl(priv->mac_reg + TDMA_CONS_INDEX);
  258. } while ((cons & 0xffff) < prod_index && --tries);
  259. if (!tries)
  260. return -ETIMEDOUT;
  261. return 0;
  262. }
  263. /* Check whether all cache lines affected by an invalidate are within
  264. * the buffer, to make sure we don't accidentally lose unrelated dirty
  265. * data stored nearby.
  266. * Alignment of the buffer start address will be checked in the implementation
  267. * of invalidate_dcache_range().
  268. */
  269. static void invalidate_dcache_check(unsigned long addr, size_t size,
  270. size_t buffer_size)
  271. {
  272. size_t inval_size = roundup(size, ARCH_DMA_MINALIGN);
  273. if (unlikely(inval_size > buffer_size))
  274. printf("WARNING: Cache invalidate area exceeds buffer size\n");
  275. invalidate_dcache_range(addr, addr + inval_size);
  276. }
  277. static int bcmgenet_gmac_eth_recv(struct udevice *dev,
  278. int flags, uchar **packetp)
  279. {
  280. struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
  281. void *desc_base = priv->rx_desc_base + priv->rx_index * DMA_DESC_SIZE;
  282. u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX);
  283. u32 length, addr;
  284. if (prod_index == priv->c_index)
  285. return -EAGAIN;
  286. length = readl(desc_base + DMA_DESC_LENGTH_STATUS);
  287. length = (length >> DMA_BUFLENGTH_SHIFT) & DMA_BUFLENGTH_MASK;
  288. addr = readl(desc_base + DMA_DESC_ADDRESS_LO);
  289. invalidate_dcache_check(addr, length, RX_BUF_LENGTH);
  290. /* To cater for the IP header alignment the hardware does.
  291. * This would actually not be needed if we don't program
  292. * RBUF_ALIGN_2B
  293. */
  294. *packetp = (uchar *)(ulong)addr + RX_BUF_OFFSET;
  295. return length - RX_BUF_OFFSET;
  296. }
  297. static int bcmgenet_gmac_free_pkt(struct udevice *dev, uchar *packet,
  298. int length)
  299. {
  300. struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
  301. /* Tell the MAC we have consumed that last receive buffer. */
  302. priv->c_index = (priv->c_index + 1) & 0xFFFF;
  303. writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX);
  304. /* Forward our descriptor pointer, wrapping around if needed. */
  305. if (++priv->rx_index >= RX_DESCS)
  306. priv->rx_index = 0;
  307. return 0;
  308. }
  309. static void rx_descs_init(struct bcmgenet_eth_priv *priv)
  310. {
  311. char *rxbuffs = &priv->rxbuffer[0];
  312. u32 len_stat, i;
  313. void *desc_base = priv->rx_desc_base;
  314. len_stat = (RX_BUF_LENGTH << DMA_BUFLENGTH_SHIFT) | DMA_OWN;
  315. for (i = 0; i < RX_DESCS; i++) {
  316. writel(lower_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]),
  317. desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_LO);
  318. writel(upper_32_bits((uintptr_t)&rxbuffs[i * RX_BUF_LENGTH]),
  319. desc_base + i * DMA_DESC_SIZE + DMA_DESC_ADDRESS_HI);
  320. writel(len_stat,
  321. desc_base + i * DMA_DESC_SIZE + DMA_DESC_LENGTH_STATUS);
  322. }
  323. }
  324. static void rx_ring_init(struct bcmgenet_eth_priv *priv)
  325. {
  326. writel(DMA_MAX_BURST_LENGTH,
  327. priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE);
  328. writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR);
  329. writel(0x0, priv->mac_reg + RDMA_READ_PTR);
  330. writel(0x0, priv->mac_reg + RDMA_WRITE_PTR);
  331. writel(RX_DESCS * DMA_DESC_SIZE / 4 - 1,
  332. priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR);
  333. /* cannot init RDMA_PROD_INDEX to 0, so align RDMA_CONS_INDEX on it instead */
  334. priv->c_index = readl(priv->mac_reg + RDMA_PROD_INDEX);
  335. writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX);
  336. priv->rx_index = priv->c_index;
  337. priv->rx_index &= 0xFF;
  338. writel((RX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
  339. priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE);
  340. writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH);
  341. writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG);
  342. }
  343. static void tx_ring_init(struct bcmgenet_eth_priv *priv)
  344. {
  345. writel(DMA_MAX_BURST_LENGTH,
  346. priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE);
  347. writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR);
  348. writel(0x0, priv->mac_reg + TDMA_READ_PTR);
  349. writel(0x0, priv->mac_reg + TDMA_WRITE_PTR);
  350. writel(TX_DESCS * DMA_DESC_SIZE / 4 - 1,
  351. priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR);
  352. /* cannot init TDMA_CONS_INDEX to 0, so align TDMA_PROD_INDEX on it instead */
  353. priv->tx_index = readl(priv->mac_reg + TDMA_CONS_INDEX);
  354. writel(priv->tx_index, priv->mac_reg + TDMA_PROD_INDEX);
  355. priv->tx_index &= 0xFF;
  356. writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH);
  357. writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD);
  358. writel((TX_DESCS << DMA_RING_SIZE_SHIFT) | RX_BUF_LENGTH,
  359. priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE);
  360. writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG);
  361. }
  362. static int bcmgenet_adjust_link(struct bcmgenet_eth_priv *priv)
  363. {
  364. struct phy_device *phy_dev = priv->phydev;
  365. u32 speed;
  366. switch (phy_dev->speed) {
  367. case SPEED_1000:
  368. speed = UMAC_SPEED_1000;
  369. break;
  370. case SPEED_100:
  371. speed = UMAC_SPEED_100;
  372. break;
  373. case SPEED_10:
  374. speed = UMAC_SPEED_10;
  375. break;
  376. default:
  377. printf("bcmgenet: Unsupported PHY speed: %d\n", phy_dev->speed);
  378. return -EINVAL;
  379. }
  380. clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE,
  381. RGMII_LINK | RGMII_MODE_EN);
  382. if (phy_dev->interface == PHY_INTERFACE_MODE_RGMII ||
  383. phy_dev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
  384. setbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, ID_MODE_DIS);
  385. writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD));
  386. return 0;
  387. }
  388. static int bcmgenet_gmac_eth_start(struct udevice *dev)
  389. {
  390. struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
  391. int ret;
  392. priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF;
  393. priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF;
  394. bcmgenet_umac_reset(priv);
  395. bcmgenet_gmac_write_hwaddr(dev);
  396. /* Disable RX/TX DMA and flush TX queues */
  397. bcmgenet_disable_dma(priv);
  398. rx_ring_init(priv);
  399. rx_descs_init(priv);
  400. tx_ring_init(priv);
  401. /* Enable RX/TX DMA */
  402. bcmgenet_enable_dma(priv);
  403. /* read PHY properties over the wire from generic PHY set-up */
  404. ret = phy_startup(priv->phydev);
  405. if (ret) {
  406. printf("bcmgenet: PHY startup failed: %d\n", ret);
  407. return ret;
  408. }
  409. /* Update MAC registers based on PHY property */
  410. ret = bcmgenet_adjust_link(priv);
  411. if (ret) {
  412. printf("bcmgenet: adjust PHY link failed: %d\n", ret);
  413. return ret;
  414. }
  415. /* Enable Rx/Tx */
  416. setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
  417. return 0;
  418. }
  419. static int bcmgenet_phy_init(struct bcmgenet_eth_priv *priv, void *dev)
  420. {
  421. struct phy_device *phydev;
  422. int ret;
  423. phydev = phy_connect(priv->bus, priv->phyaddr, dev, priv->interface);
  424. if (!phydev)
  425. return -ENODEV;
  426. phydev->supported &= PHY_GBIT_FEATURES;
  427. if (priv->speed) {
  428. ret = phy_set_supported(priv->phydev, priv->speed);
  429. if (ret)
  430. return ret;
  431. }
  432. phydev->advertising = phydev->supported;
  433. phy_connect_dev(phydev, dev);
  434. priv->phydev = phydev;
  435. phy_config(priv->phydev);
  436. return 0;
  437. }
  438. static void bcmgenet_mdio_start(struct bcmgenet_eth_priv *priv)
  439. {
  440. setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY);
  441. }
  442. static int bcmgenet_mdio_write(struct mii_dev *bus, int addr, int devad,
  443. int reg, u16 value)
  444. {
  445. struct udevice *dev = bus->priv;
  446. struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
  447. u32 val;
  448. /* Prepare the read operation */
  449. val = MDIO_WR | (addr << MDIO_PMD_SHIFT) |
  450. (reg << MDIO_REG_SHIFT) | (0xffff & value);
  451. writel_relaxed(val, priv->mac_reg + MDIO_CMD);
  452. /* Start MDIO transaction */
  453. bcmgenet_mdio_start(priv);
  454. return wait_for_bit_32(priv->mac_reg + MDIO_CMD,
  455. MDIO_START_BUSY, false, 20, true);
  456. }
  457. static int bcmgenet_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
  458. {
  459. struct udevice *dev = bus->priv;
  460. struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
  461. u32 val;
  462. int ret;
  463. /* Prepare the read operation */
  464. val = MDIO_RD | (addr << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
  465. writel_relaxed(val, priv->mac_reg + MDIO_CMD);
  466. /* Start MDIO transaction */
  467. bcmgenet_mdio_start(priv);
  468. ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD,
  469. MDIO_START_BUSY, false, 20, true);
  470. if (ret)
  471. return ret;
  472. val = readl_relaxed(priv->mac_reg + MDIO_CMD);
  473. return val & 0xffff;
  474. }
  475. static int bcmgenet_mdio_init(const char *name, struct udevice *priv)
  476. {
  477. struct mii_dev *bus = mdio_alloc();
  478. if (!bus) {
  479. debug("Failed to allocate MDIO bus\n");
  480. return -ENOMEM;
  481. }
  482. bus->read = bcmgenet_mdio_read;
  483. bus->write = bcmgenet_mdio_write;
  484. snprintf(bus->name, sizeof(bus->name), name);
  485. bus->priv = (void *)priv;
  486. return mdio_register(bus);
  487. }
  488. /* We only support RGMII (as used on the RPi4). */
  489. static int bcmgenet_interface_set(struct bcmgenet_eth_priv *priv)
  490. {
  491. phy_interface_t phy_mode = priv->interface;
  492. switch (phy_mode) {
  493. case PHY_INTERFACE_MODE_RGMII:
  494. case PHY_INTERFACE_MODE_RGMII_RXID:
  495. writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL);
  496. break;
  497. default:
  498. printf("unknown phy mode: %d\n", priv->interface);
  499. return -EINVAL;
  500. }
  501. return 0;
  502. }
  503. static int bcmgenet_eth_probe(struct udevice *dev)
  504. {
  505. struct eth_pdata *pdata = dev_get_platdata(dev);
  506. struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
  507. ofnode mdio_node;
  508. const char *name;
  509. u32 reg;
  510. int ret;
  511. u8 major;
  512. priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE);
  513. priv->interface = pdata->phy_interface;
  514. priv->speed = pdata->max_speed;
  515. /* Read GENET HW version */
  516. reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL);
  517. major = (reg >> 24) & 0x0f;
  518. if (major != 6) {
  519. if (major == 5)
  520. major = 4;
  521. else if (major == 0)
  522. major = 1;
  523. printf("Unsupported GENETv%d.%d\n", major, (reg >> 16) & 0x0f);
  524. return -ENODEV;
  525. }
  526. ret = bcmgenet_interface_set(priv);
  527. if (ret)
  528. return ret;
  529. writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL);
  530. udelay(10);
  531. /* disable MAC while updating its registers */
  532. writel(0, priv->mac_reg + UMAC_CMD);
  533. /* issue soft reset with (rg)mii loopback to ensure a stable rxclk */
  534. writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD);
  535. mdio_node = dev_read_first_subnode(dev);
  536. name = ofnode_get_name(mdio_node);
  537. ret = bcmgenet_mdio_init(name, dev);
  538. if (ret)
  539. return ret;
  540. priv->bus = miiphy_get_dev_by_name(name);
  541. return bcmgenet_phy_init(priv, dev);
  542. }
  543. static void bcmgenet_gmac_eth_stop(struct udevice *dev)
  544. {
  545. struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
  546. clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN);
  547. bcmgenet_disable_dma(priv);
  548. }
  549. static const struct eth_ops bcmgenet_gmac_eth_ops = {
  550. .start = bcmgenet_gmac_eth_start,
  551. .write_hwaddr = bcmgenet_gmac_write_hwaddr,
  552. .send = bcmgenet_gmac_eth_send,
  553. .recv = bcmgenet_gmac_eth_recv,
  554. .free_pkt = bcmgenet_gmac_free_pkt,
  555. .stop = bcmgenet_gmac_eth_stop,
  556. };
  557. static int bcmgenet_eth_ofdata_to_platdata(struct udevice *dev)
  558. {
  559. struct eth_pdata *pdata = dev_get_platdata(dev);
  560. struct bcmgenet_eth_priv *priv = dev_get_priv(dev);
  561. struct ofnode_phandle_args phy_node;
  562. const char *phy_mode;
  563. int ret;
  564. pdata->iobase = dev_read_addr(dev);
  565. /* Get phy mode from DT */
  566. pdata->phy_interface = -1;
  567. phy_mode = dev_read_string(dev, "phy-mode");
  568. if (phy_mode)
  569. pdata->phy_interface = phy_get_interface_by_name(phy_mode);
  570. if (pdata->phy_interface == -1) {
  571. debug("%s: Invalid PHY interface '%s'\n", __func__, phy_mode);
  572. return -EINVAL;
  573. }
  574. ret = dev_read_phandle_with_args(dev, "phy-handle", NULL, 0, 0,
  575. &phy_node);
  576. if (!ret) {
  577. ofnode_read_s32(phy_node.node, "reg", &priv->phyaddr);
  578. ofnode_read_s32(phy_node.node, "max-speed", &pdata->max_speed);
  579. }
  580. return 0;
  581. }
  582. /* The BCM2711 implementation has a limited burst length compared to a generic
  583. * GENETv5 version, but we go with that shorter value (8) in both cases, for
  584. * the sake of simplicity.
  585. */
  586. static const struct udevice_id bcmgenet_eth_ids[] = {
  587. {.compatible = "brcm,genet-v5"},
  588. {.compatible = "brcm,bcm2711-genet-v5"},
  589. {}
  590. };
  591. U_BOOT_DRIVER(eth_bcmgenet) = {
  592. .name = "eth_bcmgenet",
  593. .id = UCLASS_ETH,
  594. .of_match = bcmgenet_eth_ids,
  595. .ofdata_to_platdata = bcmgenet_eth_ofdata_to_platdata,
  596. .probe = bcmgenet_eth_probe,
  597. .ops = &bcmgenet_gmac_eth_ops,
  598. .priv_auto_alloc_size = sizeof(struct bcmgenet_eth_priv),
  599. .platdata_auto_alloc_size = sizeof(struct eth_pdata),
  600. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  601. };