bcm-sf2-eth-gmac.h 6.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2014 Broadcom Corporation.
  4. */
  5. #ifndef _BCM_SF2_ETH_GMAC_H_
  6. #define _BCM_SF2_ETH_GMAC_H_
  7. #define BCM_SF2_ETH_MAC_NAME "gmac"
  8. #ifndef ETHHW_PORT_INT
  9. #define ETHHW_PORT_INT 8
  10. #endif
  11. #define GMAC0_REG_BASE 0x18042000
  12. #define GMAC0_DEV_CTRL_ADDR GMAC0_REG_BASE
  13. #define GMAC0_INT_STATUS_ADDR (GMAC0_REG_BASE + 0x020)
  14. #define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100)
  15. #define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188)
  16. #define GMAC_DMA_PTR_OFFSET 0x04
  17. #define GMAC_DMA_ADDR_LOW_OFFSET 0x08
  18. #define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c
  19. #define GMAC_DMA_STATUS0_OFFSET 0x10
  20. #define GMAC_DMA_STATUS1_OFFSET 0x14
  21. #define GMAC0_DMA_TX_CTRL_ADDR (GMAC0_REG_BASE + 0x200)
  22. #define GMAC0_DMA_TX_PTR_ADDR \
  23. (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
  24. #define GMAC0_DMA_TX_ADDR_LOW_ADDR \
  25. (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
  26. #define GMAC0_DMA_TX_ADDR_HIGH_ADDR \
  27. (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
  28. #define GMAC0_DMA_TX_STATUS0_ADDR \
  29. (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
  30. #define GMAC0_DMA_TX_STATUS1_ADDR \
  31. (GMAC0_DMA_TX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
  32. #define GMAC0_DMA_RX_CTRL_ADDR (GMAC0_REG_BASE + 0x220)
  33. #define GMAC0_DMA_RX_PTR_ADDR \
  34. (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_PTR_OFFSET)
  35. #define GMAC0_DMA_RX_ADDR_LOW_ADDR \
  36. (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_LOW_OFFSET)
  37. #define GMAC0_DMA_RX_ADDR_HIGH_ADDR \
  38. (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_ADDR_HIGH_OFFSET)
  39. #define GMAC0_DMA_RX_STATUS0_ADDR \
  40. (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS0_OFFSET)
  41. #define GMAC0_DMA_RX_STATUS1_ADDR \
  42. (GMAC0_DMA_RX_CTRL_ADDR + GMAC_DMA_STATUS1_OFFSET)
  43. #define UNIMAC0_CMD_CFG_ADDR (GMAC0_REG_BASE + 0x808)
  44. #define UNIMAC0_MAC_MSB_ADDR (GMAC0_REG_BASE + 0x80c)
  45. #define UNIMAC0_MAC_LSB_ADDR (GMAC0_REG_BASE + 0x810)
  46. #define UNIMAC0_FRM_LENGTH_ADDR (GMAC0_REG_BASE + 0x814)
  47. #define GMAC0_IRL_FRAMECOUNT_SHIFT 24
  48. /* transmit channel control */
  49. /* transmit enable */
  50. #define D64_XC_XE 0x00000001
  51. /* transmit suspend request */
  52. #define D64_XC_SE 0x00000002
  53. /* parity check disable */
  54. #define D64_XC_PD 0x00000800
  55. /* BurstLen bits */
  56. #define D64_XC_BL_MASK 0x001C0000
  57. #define D64_XC_BL_SHIFT 18
  58. /* transmit descriptor table pointer */
  59. /* last valid descriptor */
  60. #define D64_XP_LD_MASK 0x00001fff
  61. /* transmit channel status */
  62. /* transmit state */
  63. #define D64_XS0_XS_MASK 0xf0000000
  64. #define D64_XS0_XS_SHIFT 28
  65. #define D64_XS0_XS_DISABLED 0x00000000
  66. #define D64_XS0_XS_ACTIVE 0x10000000
  67. #define D64_XS0_XS_IDLE 0x20000000
  68. #define D64_XS0_XS_STOPPED 0x30000000
  69. #define D64_XS0_XS_SUSP 0x40000000
  70. /* receive channel control */
  71. /* receive enable */
  72. #define D64_RC_RE 0x00000001
  73. /* address extension bits */
  74. #define D64_RC_AE 0x00030000
  75. /* overflow continue */
  76. #define D64_RC_OC 0x00000400
  77. /* parity check disable */
  78. #define D64_RC_PD 0x00000800
  79. /* receive frame offset */
  80. #define D64_RC_RO_MASK 0x000000fe
  81. #define D64_RC_RO_SHIFT 1
  82. /* BurstLen bits */
  83. #define D64_RC_BL_MASK 0x001C0000
  84. #define D64_RC_BL_SHIFT 18
  85. /* flags for dma controller */
  86. /* partity enable */
  87. #define DMA_CTRL_PEN (1 << 0)
  88. /* rx overflow continue */
  89. #define DMA_CTRL_ROC (1 << 1)
  90. /* receive descriptor table pointer */
  91. /* last valid descriptor */
  92. #define D64_RP_LD_MASK 0x00001fff
  93. /* receive channel status */
  94. /* current descriptor pointer */
  95. #define D64_RS0_CD_MASK 0x00001fff
  96. /* receive state */
  97. #define D64_RS0_RS_MASK 0xf0000000
  98. #define D64_RS0_RS_SHIFT 28
  99. #define D64_RS0_RS_DISABLED 0x00000000
  100. #define D64_RS0_RS_ACTIVE 0x10000000
  101. #define D64_RS0_RS_IDLE 0x20000000
  102. #define D64_RS0_RS_STOPPED 0x30000000
  103. #define D64_RS0_RS_SUSP 0x40000000
  104. /* descriptor control flags 1 */
  105. /* core specific flags */
  106. #define D64_CTRL_COREFLAGS 0x0ff00000
  107. /* end of descriptor table */
  108. #define D64_CTRL1_EOT ((uint32_t)1 << 28)
  109. /* interrupt on completion */
  110. #define D64_CTRL1_IOC ((uint32_t)1 << 29)
  111. /* end of frame */
  112. #define D64_CTRL1_EOF ((uint32_t)1 << 30)
  113. /* start of frame */
  114. #define D64_CTRL1_SOF ((uint32_t)1 << 31)
  115. /* descriptor control flags 2 */
  116. /* buffer byte count. real data len must <= 16KB */
  117. #define D64_CTRL2_BC_MASK 0x00007fff
  118. /* address extension bits */
  119. #define D64_CTRL2_AE 0x00030000
  120. #define D64_CTRL2_AE_SHIFT 16
  121. /* parity bit */
  122. #define D64_CTRL2_PARITY 0x00040000
  123. /* control flags in the range [27:20] are core-specific and not defined here */
  124. #define D64_CTRL_CORE_MASK 0x0ff00000
  125. #define DC_MROR 0x00000010
  126. #define PC_MTE 0x00800000
  127. /* command config */
  128. #define CC_TE 0x00000001
  129. #define CC_RE 0x00000002
  130. #define CC_ES_MASK 0x0000000c
  131. #define CC_ES_SHIFT 2
  132. #define CC_PROM 0x00000010
  133. #define CC_PAD_EN 0x00000020
  134. #define CC_CF 0x00000040
  135. #define CC_PF 0x00000080
  136. #define CC_RPI 0x00000100
  137. #define CC_TAI 0x00000200
  138. #define CC_HD 0x00000400
  139. #define CC_HD_SHIFT 10
  140. #define CC_SR 0x00002000
  141. #define CC_ML 0x00008000
  142. #define CC_AE 0x00400000
  143. #define CC_CFE 0x00800000
  144. #define CC_NLC 0x01000000
  145. #define CC_RL 0x02000000
  146. #define CC_RED 0x04000000
  147. #define CC_PE 0x08000000
  148. #define CC_TPI 0x10000000
  149. #define CC_AT 0x20000000
  150. #define I_PDEE 0x00000400
  151. #define I_PDE 0x00000800
  152. #define I_DE 0x00001000
  153. #define I_RDU 0x00002000
  154. #define I_RFO 0x00004000
  155. #define I_XFU 0x00008000
  156. #define I_RI 0x00010000
  157. #define I_XI0 0x01000000
  158. #define I_XI1 0x02000000
  159. #define I_XI2 0x04000000
  160. #define I_XI3 0x08000000
  161. #define I_ERRORS (I_PDEE | I_PDE | I_DE | I_RDU | I_RFO | I_XFU)
  162. #define DEF_INTMASK (I_XI0 | I_XI1 | I_XI2 | I_XI3 | I_RI | I_ERRORS)
  163. #define I_INTMASK 0x0f01fcff
  164. #define CHIP_DRU_BASE 0x0301d000
  165. #define CRMU_CHIP_IO_PAD_CONTROL_ADDR (CHIP_DRU_BASE + 0x0bc)
  166. #define SWITCH_GLOBAL_CONFIG_ADDR (CHIP_DRU_BASE + 0x194)
  167. #define CDRU_IOMUX_FORCE_PAD_IN_SHIFT 0
  168. #define CDRU_SWITCH_BYPASS_SWITCH_SHIFT 13
  169. #define AMAC0_IDM_RESET_ADDR 0x18110800
  170. #define AMAC0_IO_CTRL_DIRECT_ADDR 0x18110408
  171. #define AMAC0_IO_CTRL_CLK_250_SEL_SHIFT 6
  172. #define AMAC0_IO_CTRL_GMII_MODE_SHIFT 5
  173. #define AMAC0_IO_CTRL_DEST_SYNC_MODE_EN_SHIFT 3
  174. #define CHIPA_CHIP_ID_ADDR 0x18000000
  175. #define CHIPID (readl(CHIPA_CHIP_ID_ADDR) & 0xFFFF)
  176. #define CHIPREV (((readl(CHIPA_CHIP_ID_ADDR) >> 16) & 0xF)
  177. #define CHIPSKU (((readl(CHIPA_CHIP_ID_ADDR) >> 20) & 0xF)
  178. #define GMAC_MII_CTRL_ADDR 0x18002000
  179. #define GMAC_MII_CTRL_BYP_SHIFT 10
  180. #define GMAC_MII_CTRL_EXT_SHIFT 9
  181. #define GMAC_MII_DATA_ADDR 0x18002004
  182. #define GMAC_MII_DATA_READ_CMD 0x60020000
  183. #define GMAC_MII_DATA_WRITE_CMD 0x50020000
  184. #define GMAC_MII_BUSY_SHIFT 8
  185. #define GMAC_MII_PHY_ADDR_SHIFT 23
  186. #define GMAC_MII_PHY_REG_SHIFT 18
  187. #define GMAC_RESET_DELAY 2
  188. #define HWRXOFF 30
  189. #define MAXNAMEL 8
  190. #define NUMTXQ 4
  191. int gmac_add(struct eth_device *dev);
  192. #endif /* _BCM_SF2_ETH_GMAC_H_ */