altera_tse.h 6.0 KB

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  1. /*
  2. * Altera 10/100/1000 triple speed ethernet mac
  3. *
  4. * Copyright (C) 2008 Altera Corporation.
  5. * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #ifndef _ALTERA_TSE_H_
  12. #define _ALTERA_TSE_H_
  13. #include <linux/bitops.h>
  14. #define __packed_1_ __packed __aligned(1)
  15. /* dma type */
  16. #define ALT_SGDMA 0
  17. #define ALT_MSGDMA 1
  18. /* SGDMA Stuff */
  19. #define ALT_SGDMA_STATUS_BUSY_MSK BIT(4)
  20. #define ALT_SGDMA_CONTROL_RUN_MSK BIT(5)
  21. #define ALT_SGDMA_CONTROL_STOP_DMA_ER_MSK BIT(6)
  22. #define ALT_SGDMA_CONTROL_SOFTWARERESET_MSK BIT(16)
  23. /*
  24. * Descriptor control bit masks & offsets
  25. *
  26. * Note: The control byte physically occupies bits [31:24] in memory.
  27. * The following bit-offsets are expressed relative to the LSB of
  28. * the control register bitfield.
  29. */
  30. #define ALT_SGDMA_DESCRIPTOR_CONTROL_GENERATE_EOP_MSK BIT(0)
  31. #define ALT_SGDMA_DESCRIPTOR_CONTROL_READ_FIXED_ADDRESS_MSK BIT(1)
  32. #define ALT_SGDMA_DESCRIPTOR_CONTROL_WRITE_FIXED_ADDRESS_MSK BIT(2)
  33. #define ALT_SGDMA_DESCRIPTOR_CONTROL_OWNED_BY_HW_MSK BIT(7)
  34. /*
  35. * Descriptor status bit masks & offsets
  36. *
  37. * Note: The status byte physically occupies bits [23:16] in memory.
  38. * The following bit-offsets are expressed relative to the LSB of
  39. * the status register bitfield.
  40. */
  41. #define ALT_SGDMA_DESCRIPTOR_STATUS_TERMINATED_BY_EOP_MSK BIT(7)
  42. /*
  43. * The SGDMA controller buffer descriptor allocates
  44. * 64 bits for each address. To support ANSI C, the
  45. * struct implementing a descriptor places 32-bits
  46. * of padding directly above each address; each pad must
  47. * be cleared when initializing a descriptor.
  48. */
  49. /*
  50. * Buffer Descriptor data structure
  51. *
  52. */
  53. struct alt_sgdma_descriptor {
  54. u32 source; /* the address of data to be read. */
  55. u32 source_pad;
  56. u32 destination; /* the address to write data */
  57. u32 destination_pad;
  58. u32 next; /* the next descriptor in the list. */
  59. u32 next_pad;
  60. u16 bytes_to_transfer; /* the number of bytes to transfer */
  61. u8 read_burst;
  62. u8 write_burst;
  63. u16 actual_bytes_transferred;/* bytes transferred by DMA */
  64. u8 descriptor_status;
  65. u8 descriptor_control;
  66. } __packed_1_;
  67. /* SG-DMA Control/Status Slave registers map */
  68. struct alt_sgdma_registers {
  69. u32 status;
  70. u32 status_pad[3];
  71. u32 control;
  72. u32 control_pad[3];
  73. u32 next_descriptor_pointer;
  74. u32 descriptor_pad[3];
  75. };
  76. /* mSGDMA Stuff */
  77. /* mSGDMA extended descriptor format */
  78. struct msgdma_extended_desc {
  79. u32 read_addr_lo; /* data buffer source address low bits */
  80. u32 write_addr_lo; /* data buffer destination address low bits */
  81. u32 len;
  82. u32 burst_seq_num;
  83. u32 stride;
  84. u32 read_addr_hi; /* data buffer source address high bits */
  85. u32 write_addr_hi; /* data buffer destination address high bits */
  86. u32 control; /* characteristics of the transfer */
  87. };
  88. /* mSGDMA descriptor control field bit definitions */
  89. #define MSGDMA_DESC_CTL_GEN_SOP BIT(8)
  90. #define MSGDMA_DESC_CTL_GEN_EOP BIT(9)
  91. #define MSGDMA_DESC_CTL_END_ON_EOP BIT(12)
  92. #define MSGDMA_DESC_CTL_END_ON_LEN BIT(13)
  93. #define MSGDMA_DESC_CTL_GO BIT(31)
  94. /* Tx buffer control flags */
  95. #define MSGDMA_DESC_CTL_TX_SINGLE (MSGDMA_DESC_CTL_GEN_SOP | \
  96. MSGDMA_DESC_CTL_GEN_EOP | \
  97. MSGDMA_DESC_CTL_GO)
  98. #define MSGDMA_DESC_CTL_RX_SINGLE (MSGDMA_DESC_CTL_END_ON_EOP | \
  99. MSGDMA_DESC_CTL_END_ON_LEN | \
  100. MSGDMA_DESC_CTL_GO)
  101. /* mSGDMA extended descriptor stride definitions */
  102. #define MSGDMA_DESC_TX_STRIDE 0x00010001
  103. #define MSGDMA_DESC_RX_STRIDE 0x00010001
  104. /* mSGDMA dispatcher control and status register map */
  105. struct msgdma_csr {
  106. u32 status; /* Read/Clear */
  107. u32 control; /* Read/Write */
  108. u32 rw_fill_level;
  109. u32 resp_fill_level; /* bit 15:0 */
  110. u32 rw_seq_num;
  111. u32 pad[3]; /* reserved */
  112. };
  113. /* mSGDMA CSR status register bit definitions */
  114. #define MSGDMA_CSR_STAT_BUSY BIT(0)
  115. #define MSGDMA_CSR_STAT_RESETTING BIT(6)
  116. #define MSGDMA_CSR_STAT_MASK 0x3FF
  117. /* mSGDMA CSR control register bit definitions */
  118. #define MSGDMA_CSR_CTL_RESET BIT(1)
  119. /* mSGDMA response register map */
  120. struct msgdma_response {
  121. u32 bytes_transferred;
  122. u32 status;
  123. };
  124. /* TSE Stuff */
  125. #define ALTERA_TSE_CMD_TX_ENA_MSK BIT(0)
  126. #define ALTERA_TSE_CMD_RX_ENA_MSK BIT(1)
  127. #define ALTERA_TSE_CMD_ETH_SPEED_MSK BIT(3)
  128. #define ALTERA_TSE_CMD_HD_ENA_MSK BIT(10)
  129. #define ALTERA_TSE_CMD_SW_RESET_MSK BIT(13)
  130. #define ALTERA_TSE_CMD_ENA_10_MSK BIT(25)
  131. #define ALT_TSE_SW_RESET_TIMEOUT (3 * CONFIG_SYS_HZ)
  132. #define ALT_TSE_SGDMA_BUSY_TIMEOUT (3 * CONFIG_SYS_HZ)
  133. /* MAC register Space */
  134. struct alt_tse_mac {
  135. u32 megacore_revision;
  136. u32 scratch_pad;
  137. u32 command_config;
  138. u32 mac_addr_0;
  139. u32 mac_addr_1;
  140. u32 max_frame_length;
  141. u32 pause_quanta;
  142. u32 rx_sel_empty_threshold;
  143. u32 rx_sel_full_threshold;
  144. u32 tx_sel_empty_threshold;
  145. u32 tx_sel_full_threshold;
  146. u32 rx_almost_empty_threshold;
  147. u32 rx_almost_full_threshold;
  148. u32 tx_almost_empty_threshold;
  149. u32 tx_almost_full_threshold;
  150. u32 mdio_phy0_addr;
  151. u32 mdio_phy1_addr;
  152. u32 reserved1[0x29];
  153. /*FIFO control register. */
  154. u32 tx_cmd_stat;
  155. u32 rx_cmd_stat;
  156. u32 reserved2[0x44];
  157. /*Registers 0 to 31 within PHY device 0/1 */
  158. u32 mdio_phy0[0x20];
  159. u32 mdio_phy1[0x20];
  160. /*4 Supplemental MAC Addresses */
  161. u32 supp_mac_addr_0_0;
  162. u32 supp_mac_addr_0_1;
  163. u32 supp_mac_addr_1_0;
  164. u32 supp_mac_addr_1_1;
  165. u32 supp_mac_addr_2_0;
  166. u32 supp_mac_addr_2_1;
  167. u32 supp_mac_addr_3_0;
  168. u32 supp_mac_addr_3_1;
  169. u32 reserved3[0x38];
  170. };
  171. struct tse_ops {
  172. int (*send)(struct udevice *dev, void *packet, int length);
  173. int (*recv)(struct udevice *dev, int flags, uchar **packetp);
  174. int (*free_pkt)(struct udevice *dev, uchar *packet, int length);
  175. void (*stop)(struct udevice *dev);
  176. };
  177. struct altera_tse_priv {
  178. struct alt_tse_mac *mac_dev;
  179. void *sgdma_rx;
  180. void *sgdma_tx;
  181. unsigned int rx_fifo_depth;
  182. unsigned int tx_fifo_depth;
  183. void *rx_desc;
  184. void *tx_desc;
  185. void *rx_resp;
  186. unsigned char *rx_buf;
  187. unsigned int phyaddr;
  188. unsigned int interface;
  189. struct phy_device *phydev;
  190. struct mii_dev *bus;
  191. const struct tse_ops *ops;
  192. int dma_type;
  193. };
  194. #endif /* _ALTERA_TSE_H_ */