pxa_mmc_gen.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
  4. *
  5. * Modified to add driver model (DM) support
  6. * Copyright (C) 2019 Marcel Ziswiler <marcel@ziswiler.com>
  7. *
  8. * Loosely based on the old code and Linux's PXA MMC driver
  9. */
  10. #include <common.h>
  11. #include <asm/arch/hardware.h>
  12. #include <asm/arch/regs-mmc.h>
  13. #include <linux/delay.h>
  14. #include <linux/errno.h>
  15. #include <asm/io.h>
  16. #include <dm.h>
  17. #include <dm/platform_data/pxa_mmc_gen.h>
  18. #include <malloc.h>
  19. #include <mmc.h>
  20. /* PXAMMC Generic default config for various CPUs */
  21. #if defined(CONFIG_CPU_PXA25X)
  22. #define PXAMMC_FIFO_SIZE 1
  23. #define PXAMMC_MIN_SPEED 312500
  24. #define PXAMMC_MAX_SPEED 20000000
  25. #define PXAMMC_HOST_CAPS (0)
  26. #elif defined(CONFIG_CPU_PXA27X)
  27. #define PXAMMC_CRC_SKIP
  28. #define PXAMMC_FIFO_SIZE 32
  29. #define PXAMMC_MIN_SPEED 304000
  30. #define PXAMMC_MAX_SPEED 19500000
  31. #define PXAMMC_HOST_CAPS (MMC_MODE_4BIT)
  32. #elif defined(CONFIG_CPU_MONAHANS)
  33. #define PXAMMC_FIFO_SIZE 32
  34. #define PXAMMC_MIN_SPEED 304000
  35. #define PXAMMC_MAX_SPEED 26000000
  36. #define PXAMMC_HOST_CAPS (MMC_MODE_4BIT | MMC_MODE_HS)
  37. #else
  38. #error "This CPU isn't supported by PXA MMC!"
  39. #endif
  40. #define MMC_STAT_ERRORS \
  41. (MMC_STAT_RES_CRC_ERROR | MMC_STAT_SPI_READ_ERROR_TOKEN | \
  42. MMC_STAT_CRC_READ_ERROR | MMC_STAT_TIME_OUT_RESPONSE | \
  43. MMC_STAT_READ_TIME_OUT | MMC_STAT_CRC_WRITE_ERROR)
  44. /* 1 millisecond (in wait cycles below it's 100 x 10uS waits) */
  45. #define PXA_MMC_TIMEOUT 100
  46. struct pxa_mmc_priv {
  47. struct pxa_mmc_regs *regs;
  48. };
  49. /* Wait for bit to be set */
  50. static int pxa_mmc_wait(struct mmc *mmc, uint32_t mask)
  51. {
  52. struct pxa_mmc_priv *priv = mmc->priv;
  53. struct pxa_mmc_regs *regs = priv->regs;
  54. unsigned int timeout = PXA_MMC_TIMEOUT;
  55. /* Wait for bit to be set */
  56. while (--timeout) {
  57. if (readl(&regs->stat) & mask)
  58. break;
  59. udelay(10);
  60. }
  61. if (!timeout)
  62. return -ETIMEDOUT;
  63. return 0;
  64. }
  65. static int pxa_mmc_stop_clock(struct mmc *mmc)
  66. {
  67. struct pxa_mmc_priv *priv = mmc->priv;
  68. struct pxa_mmc_regs *regs = priv->regs;
  69. unsigned int timeout = PXA_MMC_TIMEOUT;
  70. /* If the clock aren't running, exit */
  71. if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
  72. return 0;
  73. /* Tell the controller to turn off the clock */
  74. writel(MMC_STRPCL_STOP_CLK, &regs->strpcl);
  75. /* Wait until the clock are off */
  76. while (--timeout) {
  77. if (!(readl(&regs->stat) & MMC_STAT_CLK_EN))
  78. break;
  79. udelay(10);
  80. }
  81. /* The clock refused to stop, scream and die a painful death */
  82. if (!timeout)
  83. return -ETIMEDOUT;
  84. /* The clock stopped correctly */
  85. return 0;
  86. }
  87. static int pxa_mmc_start_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  88. uint32_t cmdat)
  89. {
  90. struct pxa_mmc_priv *priv = mmc->priv;
  91. struct pxa_mmc_regs *regs = priv->regs;
  92. int ret;
  93. /* The card can send a "busy" response */
  94. if (cmd->resp_type & MMC_RSP_BUSY)
  95. cmdat |= MMC_CMDAT_BUSY;
  96. /* Inform the controller about response type */
  97. switch (cmd->resp_type) {
  98. case MMC_RSP_R1:
  99. case MMC_RSP_R1b:
  100. cmdat |= MMC_CMDAT_R1;
  101. break;
  102. case MMC_RSP_R2:
  103. cmdat |= MMC_CMDAT_R2;
  104. break;
  105. case MMC_RSP_R3:
  106. cmdat |= MMC_CMDAT_R3;
  107. break;
  108. default:
  109. break;
  110. }
  111. /* Load command and it's arguments into the controller */
  112. writel(cmd->cmdidx, &regs->cmd);
  113. writel(cmd->cmdarg >> 16, &regs->argh);
  114. writel(cmd->cmdarg & 0xffff, &regs->argl);
  115. writel(cmdat, &regs->cmdat);
  116. /* Start the controller clock and wait until they are started */
  117. writel(MMC_STRPCL_START_CLK, &regs->strpcl);
  118. ret = pxa_mmc_wait(mmc, MMC_STAT_CLK_EN);
  119. if (ret)
  120. return ret;
  121. /* Correct and happy end */
  122. return 0;
  123. }
  124. static int pxa_mmc_cmd_done(struct mmc *mmc, struct mmc_cmd *cmd)
  125. {
  126. struct pxa_mmc_priv *priv = mmc->priv;
  127. struct pxa_mmc_regs *regs = priv->regs;
  128. u32 a, b, c;
  129. int i;
  130. int stat;
  131. /* Read the controller status */
  132. stat = readl(&regs->stat);
  133. /*
  134. * Linux says:
  135. * Did I mention this is Sick. We always need to
  136. * discard the upper 8 bits of the first 16-bit word.
  137. */
  138. a = readl(&regs->res) & 0xffff;
  139. for (i = 0; i < 4; i++) {
  140. b = readl(&regs->res) & 0xffff;
  141. c = readl(&regs->res) & 0xffff;
  142. cmd->response[i] = (a << 24) | (b << 8) | (c >> 8);
  143. a = c;
  144. }
  145. /* The command response didn't arrive */
  146. if (stat & MMC_STAT_TIME_OUT_RESPONSE) {
  147. return -ETIMEDOUT;
  148. } else if (stat & MMC_STAT_RES_CRC_ERROR &&
  149. cmd->resp_type & MMC_RSP_CRC) {
  150. #ifdef PXAMMC_CRC_SKIP
  151. if (cmd->resp_type & MMC_RSP_136 &&
  152. cmd->response[0] & (1 << 31))
  153. printf("Ignoring CRC, this may be dangerous!\n");
  154. else
  155. #endif
  156. return -EILSEQ;
  157. }
  158. /* The command response was successfully read */
  159. return 0;
  160. }
  161. static int pxa_mmc_do_read_xfer(struct mmc *mmc, struct mmc_data *data)
  162. {
  163. struct pxa_mmc_priv *priv = mmc->priv;
  164. struct pxa_mmc_regs *regs = priv->regs;
  165. u32 len;
  166. u32 *buf = (uint32_t *)data->dest;
  167. int size;
  168. int ret;
  169. len = data->blocks * data->blocksize;
  170. while (len) {
  171. /* The controller has data ready */
  172. if (readl(&regs->i_reg) & MMC_I_REG_RXFIFO_RD_REQ) {
  173. size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
  174. len -= size;
  175. size /= 4;
  176. /* Read data into the buffer */
  177. while (size--)
  178. *buf++ = readl(&regs->rxfifo);
  179. }
  180. if (readl(&regs->stat) & MMC_STAT_ERRORS)
  181. return -EIO;
  182. }
  183. /* Wait for the transmission-done interrupt */
  184. ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
  185. if (ret)
  186. return ret;
  187. return 0;
  188. }
  189. static int pxa_mmc_do_write_xfer(struct mmc *mmc, struct mmc_data *data)
  190. {
  191. struct pxa_mmc_priv *priv = mmc->priv;
  192. struct pxa_mmc_regs *regs = priv->regs;
  193. u32 len;
  194. u32 *buf = (uint32_t *)data->src;
  195. int size;
  196. int ret;
  197. len = data->blocks * data->blocksize;
  198. while (len) {
  199. /* The controller is ready to receive data */
  200. if (readl(&regs->i_reg) & MMC_I_REG_TXFIFO_WR_REQ) {
  201. size = min(len, (uint32_t)PXAMMC_FIFO_SIZE);
  202. len -= size;
  203. size /= 4;
  204. while (size--)
  205. writel(*buf++, &regs->txfifo);
  206. if (min(len, (uint32_t)PXAMMC_FIFO_SIZE) < 32)
  207. writel(MMC_PRTBUF_BUF_PART_FULL, &regs->prtbuf);
  208. }
  209. if (readl(&regs->stat) & MMC_STAT_ERRORS)
  210. return -EIO;
  211. }
  212. /* Wait for the transmission-done interrupt */
  213. ret = pxa_mmc_wait(mmc, MMC_STAT_DATA_TRAN_DONE);
  214. if (ret)
  215. return ret;
  216. /* Wait until the data are really written to the card */
  217. ret = pxa_mmc_wait(mmc, MMC_STAT_PRG_DONE);
  218. if (ret)
  219. return ret;
  220. return 0;
  221. }
  222. static int pxa_mmc_send_cmd_common(struct pxa_mmc_priv *priv, struct mmc *mmc,
  223. struct mmc_cmd *cmd, struct mmc_data *data)
  224. {
  225. struct pxa_mmc_regs *regs = priv->regs;
  226. u32 cmdat = 0;
  227. int ret;
  228. /* Stop the controller */
  229. ret = pxa_mmc_stop_clock(mmc);
  230. if (ret)
  231. return ret;
  232. /* If we're doing data transfer, configure the controller accordingly */
  233. if (data) {
  234. writel(data->blocks, &regs->nob);
  235. writel(data->blocksize, &regs->blklen);
  236. /* This delay can be optimized, but stick with max value */
  237. writel(0xffff, &regs->rdto);
  238. cmdat |= MMC_CMDAT_DATA_EN;
  239. if (data->flags & MMC_DATA_WRITE)
  240. cmdat |= MMC_CMDAT_WRITE;
  241. }
  242. /* Run in 4bit mode if the card can do it */
  243. if (mmc->bus_width == 4)
  244. cmdat |= MMC_CMDAT_SD_4DAT;
  245. /* Execute the command */
  246. ret = pxa_mmc_start_cmd(mmc, cmd, cmdat);
  247. if (ret)
  248. return ret;
  249. /* Wait until the command completes */
  250. ret = pxa_mmc_wait(mmc, MMC_STAT_END_CMD_RES);
  251. if (ret)
  252. return ret;
  253. /* Read back the result */
  254. ret = pxa_mmc_cmd_done(mmc, cmd);
  255. if (ret)
  256. return ret;
  257. /* In case there was a data transfer scheduled, do it */
  258. if (data) {
  259. if (data->flags & MMC_DATA_WRITE)
  260. pxa_mmc_do_write_xfer(mmc, data);
  261. else
  262. pxa_mmc_do_read_xfer(mmc, data);
  263. }
  264. return 0;
  265. }
  266. static int pxa_mmc_set_ios_common(struct pxa_mmc_priv *priv, struct mmc *mmc)
  267. {
  268. struct pxa_mmc_regs *regs = priv->regs;
  269. u32 tmp;
  270. u32 pxa_mmc_clock;
  271. if (!mmc->clock) {
  272. pxa_mmc_stop_clock(mmc);
  273. return 0;
  274. }
  275. /* PXA3xx can do 26MHz with special settings. */
  276. if (mmc->clock == 26000000) {
  277. writel(0x7, &regs->clkrt);
  278. return 0;
  279. }
  280. /* Set clock to the card the usual way. */
  281. pxa_mmc_clock = 0;
  282. tmp = mmc->cfg->f_max / mmc->clock;
  283. tmp += tmp % 2;
  284. while (tmp > 1) {
  285. pxa_mmc_clock++;
  286. tmp >>= 1;
  287. }
  288. writel(pxa_mmc_clock, &regs->clkrt);
  289. return 0;
  290. }
  291. static int pxa_mmc_init_common(struct pxa_mmc_priv *priv, struct mmc *mmc)
  292. {
  293. struct pxa_mmc_regs *regs = priv->regs;
  294. /* Make sure the clock are stopped */
  295. pxa_mmc_stop_clock(mmc);
  296. /* Turn off SPI mode */
  297. writel(0, &regs->spi);
  298. /* Set up maximum timeout to wait for command response */
  299. writel(MMC_RES_TO_MAX_MASK, &regs->resto);
  300. /* Mask all interrupts */
  301. writel(~(MMC_I_MASK_TXFIFO_WR_REQ | MMC_I_MASK_RXFIFO_RD_REQ),
  302. &regs->i_mask);
  303. return 0;
  304. }
  305. #if !CONFIG_IS_ENABLED(DM_MMC)
  306. static int pxa_mmc_init(struct mmc *mmc)
  307. {
  308. struct pxa_mmc_priv *priv = mmc->priv;
  309. return pxa_mmc_init_common(priv, mmc);
  310. }
  311. static int pxa_mmc_request(struct mmc *mmc, struct mmc_cmd *cmd,
  312. struct mmc_data *data)
  313. {
  314. struct pxa_mmc_priv *priv = mmc->priv;
  315. return pxa_mmc_send_cmd_common(priv, mmc, cmd, data);
  316. }
  317. static int pxa_mmc_set_ios(struct mmc *mmc)
  318. {
  319. struct pxa_mmc_priv *priv = mmc->priv;
  320. return pxa_mmc_set_ios_common(priv, mmc);
  321. }
  322. static const struct mmc_ops pxa_mmc_ops = {
  323. .send_cmd = pxa_mmc_request,
  324. .set_ios = pxa_mmc_set_ios,
  325. .init = pxa_mmc_init,
  326. };
  327. static struct mmc_config pxa_mmc_cfg = {
  328. .name = "PXA MMC",
  329. .ops = &pxa_mmc_ops,
  330. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  331. .f_max = PXAMMC_MAX_SPEED,
  332. .f_min = PXAMMC_MIN_SPEED,
  333. .host_caps = PXAMMC_HOST_CAPS,
  334. .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  335. };
  336. int pxa_mmc_register(int card_index)
  337. {
  338. struct mmc *mmc;
  339. struct pxa_mmc_priv *priv;
  340. u32 reg;
  341. int ret = -ENOMEM;
  342. priv = malloc(sizeof(struct pxa_mmc_priv));
  343. if (!priv)
  344. goto err0;
  345. memset(priv, 0, sizeof(*priv));
  346. switch (card_index) {
  347. case 0:
  348. priv->regs = (struct pxa_mmc_regs *)MMC0_BASE;
  349. break;
  350. case 1:
  351. priv->regs = (struct pxa_mmc_regs *)MMC1_BASE;
  352. break;
  353. default:
  354. ret = -EINVAL;
  355. printf("PXA MMC: Invalid MMC controller ID (card_index = %d)\n",
  356. card_index);
  357. goto err1;
  358. }
  359. #ifndef CONFIG_CPU_MONAHANS /* PXA2xx */
  360. reg = readl(CKEN);
  361. reg |= CKEN12_MMC;
  362. writel(reg, CKEN);
  363. #else /* PXA3xx */
  364. reg = readl(CKENA);
  365. reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
  366. writel(reg, CKENA);
  367. #endif
  368. mmc = mmc_create(&pxa_mmc_cfg, priv);
  369. if (!mmc)
  370. goto err1;
  371. return 0;
  372. err1:
  373. free(priv);
  374. err0:
  375. return ret;
  376. }
  377. #else /* !CONFIG_IS_ENABLED(DM_MMC) */
  378. static int pxa_mmc_probe(struct udevice *dev)
  379. {
  380. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  381. struct pxa_mmc_plat *plat = dev_get_platdata(dev);
  382. struct mmc_config *cfg = &plat->cfg;
  383. struct mmc *mmc = &plat->mmc;
  384. struct pxa_mmc_priv *priv = dev_get_priv(dev);
  385. u32 reg;
  386. upriv->mmc = mmc;
  387. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  388. cfg->f_max = PXAMMC_MAX_SPEED;
  389. cfg->f_min = PXAMMC_MIN_SPEED;
  390. cfg->host_caps = PXAMMC_HOST_CAPS;
  391. cfg->name = dev->name;
  392. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  393. mmc->priv = priv;
  394. priv->regs = plat->base;
  395. #ifndef CONFIG_CPU_MONAHANS /* PXA2xx */
  396. reg = readl(CKEN);
  397. reg |= CKEN12_MMC;
  398. writel(reg, CKEN);
  399. #else /* PXA3xx */
  400. reg = readl(CKENA);
  401. reg |= CKENA_12_MMC0 | CKENA_13_MMC1;
  402. writel(reg, CKENA);
  403. #endif
  404. return pxa_mmc_init_common(priv, mmc);
  405. }
  406. static int pxa_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  407. struct mmc_data *data)
  408. {
  409. struct pxa_mmc_plat *plat = dev_get_platdata(dev);
  410. struct pxa_mmc_priv *priv = dev_get_priv(dev);
  411. return pxa_mmc_send_cmd_common(priv, &plat->mmc, cmd, data);
  412. }
  413. static int pxa_mmc_set_ios(struct udevice *dev)
  414. {
  415. struct pxa_mmc_plat *plat = dev_get_platdata(dev);
  416. struct pxa_mmc_priv *priv = dev_get_priv(dev);
  417. return pxa_mmc_set_ios_common(priv, &plat->mmc);
  418. }
  419. static const struct dm_mmc_ops pxa_mmc_ops = {
  420. .get_cd = NULL,
  421. .send_cmd = pxa_mmc_send_cmd,
  422. .set_ios = pxa_mmc_set_ios,
  423. };
  424. #if CONFIG_IS_ENABLED(BLK)
  425. static int pxa_mmc_bind(struct udevice *dev)
  426. {
  427. struct pxa_mmc_plat *plat = dev_get_platdata(dev);
  428. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  429. }
  430. #endif
  431. U_BOOT_DRIVER(pxa_mmc) = {
  432. #if CONFIG_IS_ENABLED(BLK)
  433. .bind = pxa_mmc_bind,
  434. #endif
  435. .id = UCLASS_MMC,
  436. .name = "pxa_mmc",
  437. .ops = &pxa_mmc_ops,
  438. .priv_auto_alloc_size = sizeof(struct pxa_mmc_priv),
  439. .probe = pxa_mmc_probe,
  440. };
  441. #endif /* !CONFIG_IS_ENABLED(DM_MMC) */