octeontx_hsmmc.c 116 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Marvell International Ltd.
  4. *
  5. * https://spdx.org/licenses
  6. */
  7. //#define DEBUG
  8. #include <cpu_func.h>
  9. #include <dm.h>
  10. #include <dm/lists.h>
  11. #include <env.h>
  12. #include <errno.h>
  13. #include <fdtdec.h>
  14. #include <log.h>
  15. #include <malloc.h>
  16. #include <memalign.h>
  17. #include <mmc.h>
  18. #include <part.h>
  19. #include <pci.h>
  20. #include <pci_ids.h>
  21. #include <time.h>
  22. #include <watchdog.h>
  23. #include <linux/delay.h>
  24. #include <linux/kernel.h>
  25. #include <linux/libfdt.h>
  26. #include <asm/arch/board.h>
  27. #include <asm/arch/clock.h>
  28. #include <asm/arch/csrs/csrs-mio_emm.h>
  29. #include <asm/io.h>
  30. #include <power/regulator.h>
  31. #include "octeontx_hsmmc.h"
  32. #define MMC_TIMEOUT_SHORT 20 /* in ms */
  33. #define MMC_TIMEOUT_LONG 1000
  34. #define MMC_TIMEOUT_ERASE 10000
  35. #define MMC_DEFAULT_DATA_IN_TAP 10
  36. #define MMC_DEFAULT_CMD_IN_TAP 10
  37. #define MMC_DEFAULT_CMD_OUT_TAP 39
  38. #define MMC_DEFAULT_DATA_OUT_TAP 39
  39. #define MMC_DEFAULT_HS200_CMD_IN_TAP 24
  40. #define MMC_DEFAULT_HS200_DATA_IN_TAP 24
  41. #define MMC_DEFAULT_HS200_CMD_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5)
  42. #define MMC_DEFAULT_HS200_DATA_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5)
  43. #define MMC_DEFAULT_HS400_CMD_OUT_TAP (otx_is_soc(CN95XX) ? 10 : 5)
  44. #define MMC_DEFAULT_HS400_DATA_OUT_TAP (otx_is_soc(CN95XX) ? 5 : 3)
  45. #define MMC_DEFAULT_HS200_CMD_OUT_DLY 800 /* Delay in ps */
  46. #define MMC_DEFAULT_HS200_DATA_OUT_DLY 800 /* Delay in ps */
  47. #define MMC_DEFAULT_HS400_CMD_OUT_DLY 800 /* Delay in ps */
  48. #define MMC_DEFAULT_HS400_DATA_OUT_DLY 400 /* Delay in ps */
  49. #define MMC_DEFAULT_SD_UHS_SDR104_CMD_OUT_TAP MMC_DEFAULT_HS200_CMD_OUT_TAP
  50. #define MMC_DEFAULT_SD_UHS_SDR104_DATA_OUT_TAP MMC_DEFAULT_HS200_DATA_OUT_TAP
  51. #define MMC_LEGACY_DEFAULT_CMD_OUT_TAP 39
  52. #define MMC_LEGACY_DEFAULT_DATA_OUT_TAP 39
  53. #define MMC_SD_LEGACY_DEFAULT_CMD_OUT_TAP 63
  54. #define MMC_SD_LEGACY_DEFAULT_DATA_OUT_TAP 63
  55. #define MMC_HS_CMD_OUT_TAP 32
  56. #define MMC_HS_DATA_OUT_TAP 32
  57. #define MMC_SD_HS_CMD_OUT_TAP 26
  58. #define MMC_SD_HS_DATA_OUT_TAP 26
  59. #define MMC_SD_UHS_SDR25_CMD_OUT_TAP 26
  60. #define MMC_SD_UHS_SDR25_DATA_OUT_TAP 26
  61. #define MMC_SD_UHS_SDR50_CMD_OUT_TAP 26
  62. #define MMC_SD_UHS_SDR50_DATA_OUT_TAP 26
  63. #define MMC_DEFAULT_TAP_DELAY 4
  64. #define TOTAL_NO_OF_TAPS 512
  65. static void octeontx_mmc_switch_to(struct mmc *mmc);
  66. static int octeontx_mmc_configure_delay(struct mmc *mmc);
  67. static void octeontx_mmc_set_timing(struct mmc *mmc);
  68. static void set_wdog(struct mmc *mmc, u64 us);
  69. static void do_switch(struct mmc *mmc, union mio_emm_switch emm_switch);
  70. static int octeontx_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  71. struct mmc_data *data);
  72. static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay);
  73. static int octeontx_mmc_calibrate_delay(struct mmc *mmc);
  74. static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc);
  75. static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc);
  76. static bool host_probed;
  77. /**
  78. * Get the slot data structure from a MMC data structure
  79. */
  80. static inline struct octeontx_mmc_slot *mmc_to_slot(struct mmc *mmc)
  81. {
  82. return container_of(mmc, struct octeontx_mmc_slot, mmc);
  83. }
  84. static inline struct octeontx_mmc_host *mmc_to_host(struct mmc *mmc)
  85. {
  86. return mmc_to_slot(mmc)->host;
  87. }
  88. static inline struct octeontx_mmc_slot *dev_to_mmc_slot(struct udevice *dev)
  89. {
  90. return dev_get_priv(dev);
  91. }
  92. static inline struct mmc *dev_to_mmc(struct udevice *dev)
  93. {
  94. return &((struct octeontx_mmc_slot *)dev_get_priv(dev))->mmc;
  95. }
  96. #ifdef DEBUG
  97. const char *mmc_reg_str(u64 reg)
  98. {
  99. if (reg == MIO_EMM_DMA_CFG())
  100. return "MIO_EMM_DMA_CFG";
  101. if (reg == MIO_EMM_DMA_ADR())
  102. return "MIO_EMM_DMA_ADR";
  103. if (reg == MIO_EMM_DMA_INT())
  104. return "MIO_EMM_DMA_INT";
  105. if (reg == MIO_EMM_CFG())
  106. return "MIO_EMM_CFG";
  107. if (reg == MIO_EMM_MODEX(0))
  108. return "MIO_EMM_MODE0";
  109. if (reg == MIO_EMM_MODEX(1))
  110. return "MIO_EMM_MODE1";
  111. if (reg == MIO_EMM_MODEX(2))
  112. return "MIO_EMM_MODE2";
  113. if (reg == MIO_EMM_MODEX(3))
  114. return "MIO_EMM_MODE3";
  115. if (reg == MIO_EMM_IO_CTL())
  116. return "MIO_EMM_IO_CTL";
  117. if (reg == MIO_EMM_SWITCH())
  118. return "MIO_EMM_SWITCH";
  119. if (reg == MIO_EMM_DMA())
  120. return "MIO_EMM_DMA";
  121. if (reg == MIO_EMM_CMD())
  122. return "MIO_EMM_CMD";
  123. if (reg == MIO_EMM_RSP_STS())
  124. return "MIO_EMM_RSP_STS";
  125. if (reg == MIO_EMM_RSP_LO())
  126. return "MIO_EMM_RSP_LO";
  127. if (reg == MIO_EMM_RSP_HI())
  128. return "MIO_EMM_RSP_HI";
  129. if (reg == MIO_EMM_INT())
  130. return "MIO_EMM_INT";
  131. if (reg == MIO_EMM_WDOG())
  132. return "MIO_EMM_WDOG";
  133. if (reg == MIO_EMM_DMA_ARG())
  134. return "MIO_EMM_DMA_ARG";
  135. if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
  136. if (reg == MIO_EMM_SAMPLE())
  137. return "MIO_EMM_SAMPLE";
  138. }
  139. if (reg == MIO_EMM_STS_MASK())
  140. return "MIO_EMM_STS_MASK";
  141. if (reg == MIO_EMM_RCA())
  142. return "MIO_EMM_RCA";
  143. if (reg == MIO_EMM_BUF_IDX())
  144. return "MIO_EMM_BUF_IDX";
  145. if (reg == MIO_EMM_BUF_DAT())
  146. return "MIO_EMM_BUF_DAT";
  147. if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
  148. if (reg == MIO_EMM_CALB())
  149. return "MIO_EMM_CALB";
  150. if (reg == MIO_EMM_TAP())
  151. return "MIO_EMM_TAP";
  152. if (reg == MIO_EMM_TIMING())
  153. return "MIO_EMM_TIMING";
  154. if (reg == MIO_EMM_DEBUG())
  155. return "MIO_EMM_DEBUG";
  156. }
  157. return "UNKNOWN";
  158. }
  159. #endif
  160. static void octeontx_print_rsp_sts(struct mmc *mmc)
  161. {
  162. #ifdef DEBUG
  163. union mio_emm_rsp_sts emm_rsp_sts;
  164. const struct octeontx_mmc_host *host = mmc_to_host(mmc);
  165. static const char * const ctype_xor_str[] = {
  166. "No data",
  167. "Read data into Dbuf",
  168. "Write data from Dbuf",
  169. "Reserved"
  170. };
  171. static const char * const rtype_xor_str[] = {
  172. "No response",
  173. "R1, 48 bits",
  174. "R2, 136 bits",
  175. "R3, 48 bits",
  176. "R4, 48 bits",
  177. "R5, 48 bits",
  178. "Reserved 6",
  179. "Reserved 7"
  180. };
  181. emm_rsp_sts.u = readq(host->base_addr + MIO_EMM_RSP_STS());
  182. printf("\nMIO_EMM_RSP_STS: 0x%016llx\n", emm_rsp_sts.u);
  183. printf(" 60-61: bus_id: %u\n", emm_rsp_sts.s.bus_id);
  184. printf(" 59: cmd_val: %s\n",
  185. emm_rsp_sts.s.cmd_val ? "yes" : "no");
  186. printf(" 58: switch_val: %s\n",
  187. emm_rsp_sts.s.switch_val ? "yes" : "no");
  188. printf(" 57: dma_val: %s\n",
  189. emm_rsp_sts.s.dma_val ? "yes" : "no");
  190. printf(" 56: dma_pend: %s\n",
  191. emm_rsp_sts.s.dma_pend ? "yes" : "no");
  192. printf(" 28: dbuf_err: %s\n",
  193. emm_rsp_sts.s.dbuf_err ? "yes" : "no");
  194. printf(" 23: dbuf: %u\n", emm_rsp_sts.s.dbuf);
  195. printf(" 22: blk_timeout: %s\n",
  196. emm_rsp_sts.s.blk_timeout ? "yes" : "no");
  197. printf(" 21: blk_crc_err: %s\n",
  198. emm_rsp_sts.s.blk_crc_err ? "yes" : "no");
  199. printf(" 20: rsp_busybit: %s\n",
  200. emm_rsp_sts.s.rsp_busybit ? "yes" : "no");
  201. printf(" 19: stp_timeout: %s\n",
  202. emm_rsp_sts.s.stp_timeout ? "yes" : "no");
  203. printf(" 18: stp_crc_err: %s\n",
  204. emm_rsp_sts.s.stp_crc_err ? "yes" : "no");
  205. printf(" 17: stp_bad_sts: %s\n",
  206. emm_rsp_sts.s.stp_bad_sts ? "yes" : "no");
  207. printf(" 16: stp_val: %s\n",
  208. emm_rsp_sts.s.stp_val ? "yes" : "no");
  209. printf(" 15: rsp_timeout: %s\n",
  210. emm_rsp_sts.s.rsp_timeout ? "yes" : "no");
  211. printf(" 14: rsp_crc_err: %s\n",
  212. emm_rsp_sts.s.rsp_crc_err ? "yes" : "no");
  213. printf(" 13: rsp_bad_sts: %s\n",
  214. emm_rsp_sts.s.rsp_bad_sts ? "yes" : "no");
  215. printf(" 12: rsp_val: %s\n",
  216. emm_rsp_sts.s.rsp_val ? "yes" : "no");
  217. printf(" 9-11: rsp_type: %s\n",
  218. rtype_xor_str[emm_rsp_sts.s.rsp_type]);
  219. printf(" 7-8: cmd_type: %s\n",
  220. ctype_xor_str[emm_rsp_sts.s.cmd_type]);
  221. printf(" 1-6: cmd_idx: %u\n",
  222. emm_rsp_sts.s.cmd_idx);
  223. printf(" 0: cmd_done: %s\n",
  224. emm_rsp_sts.s.cmd_done ? "yes" : "no");
  225. #endif
  226. }
  227. static inline u64 read_csr(struct mmc *mmc, u64 reg)
  228. {
  229. const struct octeontx_mmc_host *host = mmc_to_host(mmc);
  230. u64 value = readq(host->base_addr + reg);
  231. #ifdef DEBUG_CSR
  232. printf(" %s: %s(0x%p) => 0x%llx\n", __func__,
  233. mmc_reg_str(reg), host->base_addr + reg,
  234. value);
  235. #endif
  236. return value;
  237. }
  238. /**
  239. * Writes to a CSR register
  240. *
  241. * @param[in] mmc pointer to mmc data structure
  242. * @param reg register offset
  243. * @param value value to write to register
  244. */
  245. static inline void write_csr(struct mmc *mmc, u64 reg, u64 value)
  246. {
  247. const struct octeontx_mmc_host *host = mmc_to_host(mmc);
  248. void *addr = host->base_addr + reg;
  249. #ifdef DEBUG_CSR
  250. printf(" %s: %s(0x%p) <= 0x%llx\n", __func__, mmc_reg_str(reg),
  251. addr, value);
  252. #endif
  253. writeq(value, addr);
  254. }
  255. #ifdef DEBUG
  256. static void mmc_print_status(u32 status)
  257. {
  258. #ifdef DEBUG_STATUS
  259. static const char * const state[] = {
  260. "Idle", /* 0 */
  261. "Ready", /* 1 */
  262. "Ident", /* 2 */
  263. "Standby", /* 3 */
  264. "Tran", /* 4 */
  265. "Data", /* 5 */
  266. "Receive", /* 6 */
  267. "Program", /* 7 */
  268. "Dis", /* 8 */
  269. "Btst", /* 9 */
  270. "Sleep", /* 10 */
  271. "reserved", /* 11 */
  272. "reserved", /* 12 */
  273. "reserved", /* 13 */
  274. "reserved", /* 14 */
  275. "reserved" /* 15 */ };
  276. if (status & R1_APP_CMD)
  277. puts("MMC ACMD\n");
  278. if (status & R1_SWITCH_ERROR)
  279. puts("MMC switch error\n");
  280. if (status & R1_READY_FOR_DATA)
  281. puts("MMC ready for data\n");
  282. printf("MMC %s state\n", state[R1_CURRENT_STATE(status)]);
  283. if (status & R1_ERASE_RESET)
  284. puts("MMC erase reset\n");
  285. if (status & R1_WP_ERASE_SKIP)
  286. puts("MMC partial erase due to write protected blocks\n");
  287. if (status & R1_CID_CSD_OVERWRITE)
  288. puts("MMC CID/CSD overwrite error\n");
  289. if (status & R1_ERROR)
  290. puts("MMC undefined device error\n");
  291. if (status & R1_CC_ERROR)
  292. puts("MMC device error\n");
  293. if (status & R1_CARD_ECC_FAILED)
  294. puts("MMC internal ECC failed to correct data\n");
  295. if (status & R1_ILLEGAL_COMMAND)
  296. puts("MMC illegal command\n");
  297. if (status & R1_COM_CRC_ERROR)
  298. puts("MMC CRC of previous command failed\n");
  299. if (status & R1_LOCK_UNLOCK_FAILED)
  300. puts("MMC sequence or password error in lock/unlock device command\n");
  301. if (status & R1_CARD_IS_LOCKED)
  302. puts("MMC device locked by host\n");
  303. if (status & R1_WP_VIOLATION)
  304. puts("MMC attempt to program write protected block\n");
  305. if (status & R1_ERASE_PARAM)
  306. puts("MMC invalid selection of erase groups for erase\n");
  307. if (status & R1_ERASE_SEQ_ERROR)
  308. puts("MMC error in sequence of erase commands\n");
  309. if (status & R1_BLOCK_LEN_ERROR)
  310. puts("MMC block length error\n");
  311. if (status & R1_ADDRESS_ERROR)
  312. puts("MMC address misalign error\n");
  313. if (status & R1_OUT_OF_RANGE)
  314. puts("MMC address out of range\n");
  315. #endif
  316. }
  317. #endif
  318. /**
  319. * Print out all of the register values where mmc is optional
  320. *
  321. * @param mmc MMC device (can be NULL)
  322. * @param host Pointer to host data structure (can be NULL if mmc is !NULL)
  323. */
  324. static void octeontx_mmc_print_registers2(struct mmc *mmc,
  325. struct octeontx_mmc_host *host)
  326. {
  327. struct octeontx_mmc_slot *slot = mmc ? mmc->priv : NULL;
  328. union mio_emm_dma_cfg emm_dma_cfg;
  329. union mio_emm_dma_adr emm_dma_adr;
  330. union mio_emm_dma_int emm_dma_int;
  331. union mio_emm_cfg emm_cfg;
  332. union mio_emm_modex emm_mode;
  333. union mio_emm_switch emm_switch;
  334. union mio_emm_dma emm_dma;
  335. union mio_emm_cmd emm_cmd;
  336. union mio_emm_rsp_sts emm_rsp_sts;
  337. union mio_emm_rsp_lo emm_rsp_lo;
  338. union mio_emm_rsp_hi emm_rsp_hi;
  339. union mio_emm_int emm_int;
  340. union mio_emm_wdog emm_wdog;
  341. union mio_emm_sample emm_sample;
  342. union mio_emm_calb emm_calb;
  343. union mio_emm_tap emm_tap;
  344. union mio_emm_timing emm_timing;
  345. union mio_emm_io_ctl io_ctl;
  346. union mio_emm_debug emm_debug;
  347. union mio_emm_sts_mask emm_sts_mask;
  348. union mio_emm_rca emm_rca;
  349. int bus;
  350. static const char * const bus_width_str[] = {
  351. "1-bit data bus (power on)",
  352. "4-bit data bus",
  353. "8-bit data bus",
  354. "reserved (3)",
  355. "reserved (4)",
  356. "4-bit data bus (dual data rate)",
  357. "8-bit data bus (dual data rate)",
  358. "reserved (7)",
  359. "reserved (8)",
  360. "invalid (9)",
  361. "invalid (10)",
  362. "invalid (11)",
  363. "invalid (12)",
  364. "invalid (13)",
  365. "invalid (14)",
  366. "invalid (15)",
  367. };
  368. static const char * const ctype_xor_str[] = {
  369. "No data",
  370. "Read data into Dbuf",
  371. "Write data from Dbuf",
  372. "Reserved"
  373. };
  374. static const char * const rtype_xor_str[] = {
  375. "No response",
  376. "R1, 48 bits",
  377. "R2, 136 bits",
  378. "R3, 48 bits",
  379. "R4, 48 bits",
  380. "R5, 48 bits",
  381. "Reserved 6",
  382. "Reserved 7"
  383. };
  384. if (!host && mmc)
  385. host = mmc_to_host(mmc);
  386. if (mmc)
  387. printf("%s: bus id: %u\n", __func__, slot->bus_id);
  388. emm_dma_cfg.u = readq(host->base_addr + MIO_EMM_DMA_CFG());
  389. printf("MIO_EMM_DMA_CFG: 0x%016llx\n",
  390. emm_dma_cfg.u);
  391. printf(" 63: en: %s\n",
  392. emm_dma_cfg.s.en ? "enabled" : "disabled");
  393. printf(" 62: rw: %s\n",
  394. emm_dma_cfg.s.rw ? "write" : "read");
  395. printf(" 61: clr: %s\n",
  396. emm_dma_cfg.s.clr ? "clear" : "not clear");
  397. printf(" 59: swap32: %s\n",
  398. emm_dma_cfg.s.swap32 ? "yes" : "no");
  399. printf(" 58: swap16: %s\n",
  400. emm_dma_cfg.s.swap16 ? "yes" : "no");
  401. printf(" 57: swap8: %s\n",
  402. emm_dma_cfg.s.swap8 ? "yes" : "no");
  403. printf(" 56: endian: %s\n",
  404. emm_dma_cfg.s.endian ? "little" : "big");
  405. printf(" 36-55: size: %u\n",
  406. emm_dma_cfg.s.size);
  407. emm_dma_adr.u = readq(host->base_addr + MIO_EMM_DMA_ADR());
  408. printf("MIO_EMM_DMA_ADR: 0x%016llx\n", emm_dma_adr.u);
  409. printf(" 0-49: adr: 0x%llx\n",
  410. (u64)emm_dma_adr.s.adr);
  411. emm_dma_int.u = readq(host->base_addr + MIO_EMM_DMA_INT());
  412. printf("\nMIO_EMM_DMA_INT: 0x%016llx\n",
  413. emm_dma_int.u);
  414. printf(" 1: FIFO: %s\n",
  415. emm_dma_int.s.fifo ? "yes" : "no");
  416. printf(" 0: Done: %s\n",
  417. emm_dma_int.s.done ? "yes" : "no");
  418. emm_cfg.u = readq(host->base_addr + MIO_EMM_CFG());
  419. printf("\nMIO_EMM_CFG: 0x%016llx\n",
  420. emm_cfg.u);
  421. printf(" 3: bus_ena3: %s\n",
  422. emm_cfg.s.bus_ena & 0x08 ? "yes" : "no");
  423. printf(" 2: bus_ena2: %s\n",
  424. emm_cfg.s.bus_ena & 0x04 ? "yes" : "no");
  425. printf(" 1: bus_ena1: %s\n",
  426. emm_cfg.s.bus_ena & 0x02 ? "yes" : "no");
  427. printf(" 0: bus_ena0: %s\n",
  428. emm_cfg.s.bus_ena & 0x01 ? "yes" : "no");
  429. for (bus = 0; bus < 4; bus++) {
  430. emm_mode.u = readq(host->base_addr + MIO_EMM_MODEX(bus));
  431. printf("\nMIO_EMM_MODE%u: 0x%016llx\n",
  432. bus, emm_mode.u);
  433. if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
  434. printf(" 50: hs400_timing: %s\n",
  435. emm_mode.s.hs400_timing ? "yes" : "no");
  436. printf(" 49: hs200_timing: %s\n",
  437. emm_mode.s.hs200_timing ? "yes" : "no");
  438. }
  439. printf(" 48: hs_timing: %s\n",
  440. emm_mode.s.hs_timing ? "yes" : "no");
  441. printf(" 40-42: bus_width: %s\n",
  442. bus_width_str[emm_mode.s.bus_width]);
  443. printf(" 32-35: power_class %u\n",
  444. emm_mode.s.power_class);
  445. printf(" 16-31: clk_hi: %u\n",
  446. emm_mode.s.clk_hi);
  447. printf(" 0-15: clk_lo: %u\n",
  448. emm_mode.s.clk_lo);
  449. }
  450. emm_switch.u = readq(host->base_addr + MIO_EMM_SWITCH());
  451. printf("\nMIO_EMM_SWITCH: 0x%016llx\n", emm_switch.u);
  452. printf(" 60-61: bus_id: %u\n", emm_switch.s.bus_id);
  453. printf(" 59: switch_exe: %s\n",
  454. emm_switch.s.switch_exe ? "yes" : "no");
  455. printf(" 58: switch_err0: %s\n",
  456. emm_switch.s.switch_err0 ? "yes" : "no");
  457. printf(" 57: switch_err1: %s\n",
  458. emm_switch.s.switch_err1 ? "yes" : "no");
  459. printf(" 56: switch_err2: %s\n",
  460. emm_switch.s.switch_err2 ? "yes" : "no");
  461. printf(" 48: hs_timing: %s\n",
  462. emm_switch.s.hs_timing ? "yes" : "no");
  463. printf(" 42-40: bus_width: %s\n",
  464. bus_width_str[emm_switch.s.bus_width]);
  465. printf(" 32-35: power_class: %u\n",
  466. emm_switch.s.power_class);
  467. printf(" 16-31: clk_hi: %u\n",
  468. emm_switch.s.clk_hi);
  469. printf(" 0-15: clk_lo: %u\n", emm_switch.s.clk_lo);
  470. emm_dma.u = readq(host->base_addr + MIO_EMM_DMA());
  471. printf("\nMIO_EMM_DMA: 0x%016llx\n", emm_dma.u);
  472. printf(" 60-61: bus_id: %u\n", emm_dma.s.bus_id);
  473. printf(" 59: dma_val: %s\n",
  474. emm_dma.s.dma_val ? "yes" : "no");
  475. printf(" 58: sector: %s mode\n",
  476. emm_dma.s.sector ? "sector" : "byte");
  477. printf(" 57: dat_null: %s\n",
  478. emm_dma.s.dat_null ? "yes" : "no");
  479. printf(" 51-56: thres: %u\n", emm_dma.s.thres);
  480. printf(" 50: rel_wr: %s\n",
  481. emm_dma.s.rel_wr ? "yes" : "no");
  482. printf(" 49: rw: %s\n",
  483. emm_dma.s.rw ? "write" : "read");
  484. printf(" 48: multi: %s\n",
  485. emm_dma.s.multi ? "yes" : "no");
  486. printf(" 32-47: block_cnt: %u\n",
  487. emm_dma.s.block_cnt);
  488. printf(" 0-31: card_addr: 0x%x\n",
  489. emm_dma.s.card_addr);
  490. emm_cmd.u = readq(host->base_addr + MIO_EMM_CMD());
  491. printf("\nMIO_EMM_CMD: 0x%016llx\n", emm_cmd.u);
  492. printf("\n 62: skip_busy: %s\n",
  493. emm_cmd.s.skip_busy ? "yes" : "no");
  494. printf(" 60-61: bus_id: %u\n", emm_cmd.s.bus_id);
  495. printf(" 59: cmd_val: %s\n",
  496. emm_cmd.s.cmd_val ? "yes" : "no");
  497. printf(" 55: dbuf: %u\n", emm_cmd.s.dbuf);
  498. printf(" 49-54: offset: %u\n", emm_cmd.s.offset);
  499. printf(" 41-42: ctype_xor: %s\n",
  500. ctype_xor_str[emm_cmd.s.ctype_xor]);
  501. printf(" 38-40: rtype_xor: %s\n",
  502. rtype_xor_str[emm_cmd.s.rtype_xor]);
  503. printf(" 32-37: cmd_idx: %u\n", emm_cmd.s.cmd_idx);
  504. printf(" 0-31: arg: 0x%x\n", emm_cmd.s.arg);
  505. emm_rsp_sts.u = readq(host->base_addr + MIO_EMM_RSP_STS());
  506. printf("\nMIO_EMM_RSP_STS: 0x%016llx\n", emm_rsp_sts.u);
  507. printf(" 60-61: bus_id: %u\n", emm_rsp_sts.s.bus_id);
  508. printf(" 59: cmd_val: %s\n",
  509. emm_rsp_sts.s.cmd_val ? "yes" : "no");
  510. printf(" 58: switch_val: %s\n",
  511. emm_rsp_sts.s.switch_val ? "yes" : "no");
  512. printf(" 57: dma_val: %s\n",
  513. emm_rsp_sts.s.dma_val ? "yes" : "no");
  514. printf(" 56: dma_pend: %s\n",
  515. emm_rsp_sts.s.dma_pend ? "yes" : "no");
  516. printf(" 28: dbuf_err: %s\n",
  517. emm_rsp_sts.s.dbuf_err ? "yes" : "no");
  518. printf(" 23: dbuf: %u\n", emm_rsp_sts.s.dbuf);
  519. printf(" 22: blk_timeout: %s\n",
  520. emm_rsp_sts.s.blk_timeout ? "yes" : "no");
  521. printf(" 21: blk_crc_err: %s\n",
  522. emm_rsp_sts.s.blk_crc_err ? "yes" : "no");
  523. printf(" 20: rsp_busybit: %s\n",
  524. emm_rsp_sts.s.rsp_busybit ? "yes" : "no");
  525. printf(" 19: stp_timeout: %s\n",
  526. emm_rsp_sts.s.stp_timeout ? "yes" : "no");
  527. printf(" 18: stp_crc_err: %s\n",
  528. emm_rsp_sts.s.stp_crc_err ? "yes" : "no");
  529. printf(" 17: stp_bad_sts: %s\n",
  530. emm_rsp_sts.s.stp_bad_sts ? "yes" : "no");
  531. printf(" 16: stp_val: %s\n",
  532. emm_rsp_sts.s.stp_val ? "yes" : "no");
  533. printf(" 15: rsp_timeout: %s\n",
  534. emm_rsp_sts.s.rsp_timeout ? "yes" : "no");
  535. printf(" 14: rsp_crc_err: %s\n",
  536. emm_rsp_sts.s.rsp_crc_err ? "yes" : "no");
  537. printf(" 13: rsp_bad_sts: %s\n",
  538. emm_rsp_sts.s.rsp_bad_sts ? "yes" : "no");
  539. printf(" 12: rsp_val: %s\n",
  540. emm_rsp_sts.s.rsp_val ? "yes" : "no");
  541. printf(" 9-11: rsp_type: %s\n",
  542. rtype_xor_str[emm_rsp_sts.s.rsp_type]);
  543. printf(" 7-8: cmd_type: %s\n",
  544. ctype_xor_str[emm_rsp_sts.s.cmd_type]);
  545. printf(" 1-6: cmd_idx: %u\n",
  546. emm_rsp_sts.s.cmd_idx);
  547. printf(" 0: cmd_done: %s\n",
  548. emm_rsp_sts.s.cmd_done ? "yes" : "no");
  549. emm_rsp_lo.u = readq(host->base_addr + MIO_EMM_RSP_LO());
  550. printf("\nMIO_EMM_RSP_STS_LO: 0x%016llx\n", emm_rsp_lo.u);
  551. emm_rsp_hi.u = readq(host->base_addr + MIO_EMM_RSP_HI());
  552. printf("\nMIO_EMM_RSP_STS_HI: 0x%016llx\n", emm_rsp_hi.u);
  553. emm_int.u = readq(host->base_addr + MIO_EMM_INT());
  554. printf("\nMIO_EMM_INT: 0x%016llx\n", emm_int.u);
  555. printf(" 6: switch_err: %s\n",
  556. emm_int.s.switch_err ? "yes" : "no");
  557. printf(" 5: switch_done: %s\n",
  558. emm_int.s.switch_done ? "yes" : "no");
  559. printf(" 4: dma_err: %s\n",
  560. emm_int.s.dma_err ? "yes" : "no");
  561. printf(" 3: cmd_err: %s\n",
  562. emm_int.s.cmd_err ? "yes" : "no");
  563. printf(" 2: dma_done: %s\n",
  564. emm_int.s.dma_done ? "yes" : "no");
  565. printf(" 1: cmd_done: %s\n",
  566. emm_int.s.cmd_done ? "yes" : "no");
  567. printf(" 0: buf_done: %s\n",
  568. emm_int.s.buf_done ? "yes" : "no");
  569. emm_wdog.u = readq(host->base_addr + MIO_EMM_WDOG());
  570. printf("\nMIO_EMM_WDOG: 0x%016llx (%u)\n",
  571. emm_wdog.u, emm_wdog.s.clk_cnt);
  572. if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
  573. emm_sample.u = readq(host->base_addr + MIO_EMM_SAMPLE());
  574. printf("\nMIO_EMM_SAMPLE: 0x%016llx\n",
  575. emm_sample.u);
  576. printf(" 16-25: cmd_cnt: %u\n",
  577. emm_sample.s.cmd_cnt);
  578. printf(" 0-9: dat_cnt: %u\n",
  579. emm_sample.s.dat_cnt);
  580. }
  581. emm_sts_mask.u = readq(host->base_addr + MIO_EMM_STS_MASK());
  582. printf("\nMIO_EMM_STS_MASK: 0x%016llx\n", emm_sts_mask.u);
  583. emm_rca.u = readq(host->base_addr + MIO_EMM_RCA());
  584. printf("\nMIO_EMM_RCA: 0x%016llx\n", emm_rca.u);
  585. printf(" 0-15: card_rca: 0x%04x\n",
  586. emm_rca.s.card_rca);
  587. if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
  588. emm_calb.u = readq(host->base_addr + MIO_EMM_CALB());
  589. printf("\nMIO_EMM_CALB: 0x%016llx\n",
  590. emm_calb.u);
  591. printf(" 0: start: %u\n",
  592. emm_calb.s.start);
  593. emm_tap.u = readq(host->base_addr + MIO_EMM_TAP());
  594. printf("\nMIO_EMM_TAP: 0x%016llx\n",
  595. emm_tap.u);
  596. printf(" 7-0: delay: %u\n", emm_tap.s.delay);
  597. emm_timing.u = readq(host->base_addr + MIO_EMM_TIMING());
  598. printf("\nMIO_EMM_TIMING: 0x%016llx\n",
  599. emm_timing.u);
  600. printf(" 53-48: cmd_in_tap: %u\n",
  601. emm_timing.s.cmd_in_tap);
  602. printf(" 37-32: cmd_out_tap: %u\n",
  603. emm_timing.s.cmd_out_tap);
  604. printf(" 21-16: data_in_tap: %u\n",
  605. emm_timing.s.data_in_tap);
  606. printf(" 5-0: data_out_tap: %u\n",
  607. emm_timing.s.data_out_tap);
  608. io_ctl.u = readq(host->base_addr + MIO_EMM_IO_CTL());
  609. printf("\nMIO_IO_CTL: 0x%016llx\n", io_ctl.u);
  610. printf(" 3-2: drive: %u (%u mA)\n",
  611. io_ctl.s.drive, 2 << io_ctl.s.drive);
  612. printf(" 0: slew: %u %s\n", io_ctl.s.slew,
  613. io_ctl.s.slew ? "high" : "low");
  614. emm_debug.u = readq(host->base_addr + MIO_EMM_DEBUG());
  615. printf("\nMIO_EMM_DEBUG: 0x%016llx\n",
  616. emm_debug.u);
  617. printf(" 21: rdsync_rst 0x%x\n",
  618. emm_debug.s.rdsync_rst);
  619. printf(" 20: emmc_clk_disable 0x%x\n",
  620. emm_debug.s.emmc_clk_disable);
  621. printf(" 19-16: dma_sm: 0x%x\n",
  622. emm_debug.s.dma_sm);
  623. printf(" 15-12: data_sm: 0x%x\n",
  624. emm_debug.s.data_sm);
  625. printf(" 11-8: cmd_sm: 0x%x\n",
  626. emm_debug.s.cmd_sm);
  627. printf(" 0: clk_on: 0x%x\n",
  628. emm_debug.s.clk_on);
  629. }
  630. puts("\n");
  631. }
  632. /**
  633. * Print out all of the register values
  634. *
  635. * @param mmc MMC device
  636. */
  637. static void octeontx_mmc_print_registers(struct mmc *mmc)
  638. {
  639. #ifdef DEBUG_REGISTERS
  640. const int print = 1;
  641. #else
  642. const int print = 0;
  643. #endif
  644. if (print)
  645. octeontx_mmc_print_registers2(mmc, mmc_to_host(mmc));
  646. }
  647. static const struct octeontx_sd_mods octeontx_cr_types[] = {
  648. { {0, 0}, {0, 0}, {0, 0} }, /* CMD0 */
  649. { {0, 3}, {0, 3}, {0, 0} }, /* CMD1 */
  650. { {0, 2}, {0, 2}, {0, 0} }, /* CMD2 */
  651. { {0, 1}, {0, 3}, {0, 0} }, /* CMD3 SD_CMD_SEND_RELATIVE_ADDR 0, 2 */
  652. { {0, 0}, {0, 0}, {0, 0} }, /* CMD4 */
  653. { {0, 1}, {0, 1}, {0, 0} }, /* CMD5 */
  654. { {0, 1}, {1, 1}, {0, 1} }, /*
  655. * CMD6 SD_CMD_SWITCH_FUNC 1,0
  656. * (ACMD) SD_APP_SET_BUS_WIDTH
  657. */
  658. { {0, 1}, {0, 1}, {0, 0} }, /* CMD7 */
  659. { {1, 1}, {0, 3}, {0, 0} }, /* CMD8 SD_CMD_SEND_IF_COND 1,2 */
  660. { {0, 2}, {0, 2}, {0, 0} }, /* CMD9 */
  661. { {0, 2}, {0, 2}, {0, 0} }, /* CMD10 */
  662. { {1, 1}, {0, 1}, {1, 1} }, /* CMD11 SD_CMD_SWITCH_UHS18V 1,0 */
  663. { {0, 1}, {0, 1}, {0, 0} }, /* CMD12 */
  664. { {0, 1}, {0, 1}, {1, 3} }, /* CMD13 (ACMD)) SD_CMD_APP_SD_STATUS 1,2 */
  665. { {1, 1}, {1, 1}, {0, 0} }, /* CMD14 */
  666. { {0, 0}, {0, 0}, {0, 0} }, /* CMD15 */
  667. { {0, 1}, {0, 1}, {0, 0} }, /* CMD16 */
  668. { {1, 1}, {1, 1}, {0, 0} }, /* CMD17 */
  669. { {1, 1}, {1, 1}, {0, 0} }, /* CMD18 */
  670. { {3, 1}, {3, 1}, {0, 0} }, /* CMD19 */
  671. { {2, 1}, {0, 0}, {0, 0} }, /* CMD20 */ /* SD 2,0 */
  672. { {0, 0}, {0, 0}, {0, 0} }, /* CMD21 */
  673. { {0, 0}, {0, 0}, {1, 1} }, /* CMD22 (ACMD) SD_APP_SEND_NUM_WR_BLKS 1,0 */
  674. { {0, 1}, {0, 1}, {0, 1} }, /* CMD23 */ /* SD ACMD 1,0 */
  675. { {2, 1}, {2, 1}, {2, 1} }, /* CMD24 */
  676. { {2, 1}, {2, 1}, {2, 1} }, /* CMD25 */
  677. { {2, 1}, {2, 1}, {2, 1} }, /* CMD26 */
  678. { {2, 1}, {2, 1}, {2, 1} }, /* CMD27 */
  679. { {0, 1}, {0, 1}, {0, 1} }, /* CMD28 */
  680. { {0, 1}, {0, 1}, {0, 1} }, /* CMD29 */
  681. { {1, 1}, {1, 1}, {1, 1} }, /* CMD30 */
  682. { {1, 1}, {1, 1}, {1, 1} }, /* CMD31 */
  683. { {0, 0}, {0, 1}, {0, 0} }, /* CMD32 SD_CMD_ERASE_WR_BLK_START 0,1 */
  684. { {0, 0}, {0, 1}, {0, 0} }, /* CMD33 SD_CMD_ERASE_WR_BLK_END 0,1 */
  685. { {0, 0}, {0, 0}, {0, 0} }, /* CMD34 */
  686. { {0, 1}, {0, 1}, {0, 1} }, /* CMD35 */
  687. { {0, 1}, {0, 1}, {0, 1} }, /* CMD36 */
  688. { {0, 0}, {0, 0}, {0, 0} }, /* CMD37 */
  689. { {0, 1}, {0, 1}, {0, 1} }, /* CMD38 */
  690. { {0, 4}, {0, 4}, {0, 4} }, /* CMD39 */
  691. { {0, 5}, {0, 5}, {0, 5} }, /* CMD40 */
  692. { {0, 0}, {0, 0}, {0, 3} }, /* CMD41 (ACMD) SD_CMD_APP_SEND_OP_COND 0,3 */
  693. { {2, 1}, {2, 1}, {2, 1} }, /* CMD42 */
  694. { {0, 0}, {0, 0}, {0, 0} }, /* CMD43 */
  695. { {0, 0}, {0, 0}, {0, 0} }, /* CMD44 */
  696. { {0, 0}, {0, 0}, {0, 0} }, /* CMD45 */
  697. { {0, 0}, {0, 0}, {0, 0} }, /* CMD46 */
  698. { {0, 0}, {0, 0}, {0, 0} }, /* CMD47 */
  699. { {0, 0}, {1, 0}, {0, 0} }, /* CMD48 SD_CMD_READ_EXTR_SINGLE */
  700. { {0, 0}, {2, 0}, {0, 0} }, /* CMD49 SD_CMD_WRITE_EXTR_SINGLE */
  701. { {0, 0}, {0, 0}, {0, 0} }, /* CMD50 */
  702. { {0, 0}, {0, 0}, {1, 1} }, /* CMD51 (ACMD) SD_CMD_APP_SEND_SCR 1,1 */
  703. { {0, 0}, {0, 0}, {0, 0} }, /* CMD52 */
  704. { {0, 0}, {0, 0}, {0, 0} }, /* CMD53 */
  705. { {0, 0}, {0, 0}, {0, 0} }, /* CMD54 */
  706. { {0, 1}, {0, 1}, {0, 1} }, /* CMD55 */
  707. { {0xff, 0xff}, {0xff, 0xff}, {0xff, 0xff} }, /* CMD56 */
  708. { {0, 0}, {0, 0}, {0, 0} }, /* CMD57 */
  709. { {0, 0}, {0, 3}, {0, 3} }, /* CMD58 SD_CMD_SPI_READ_OCR 0,3 */
  710. { {0, 0}, {0, 1}, {0, 0} }, /* CMD59 SD_CMD_SPI_CRC_ON_OFF 0,1 */
  711. { {0, 0}, {0, 0}, {0, 0} }, /* CMD60 */
  712. { {0, 0}, {0, 0}, {0, 0} }, /* CMD61 */
  713. { {0, 0}, {0, 0}, {0, 0} }, /* CMD62 */
  714. { {0, 0}, {0, 0}, {0, 0} } /* CMD63 */
  715. };
  716. /**
  717. * Returns XOR values needed for SD commands and other quirks
  718. *
  719. * @param mmc mmc device
  720. * @param cmd command information
  721. *
  722. * @return octeontx_mmc_cr_mods data structure with various quirks and flags
  723. */
  724. static struct octeontx_mmc_cr_mods
  725. octeontx_mmc_get_cr_mods(struct mmc *mmc, const struct mmc_cmd *cmd,
  726. const struct mmc_data *data)
  727. {
  728. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  729. struct octeontx_mmc_cr_mods cr = {0, 0};
  730. const struct octeontx_sd_mods *sdm =
  731. &octeontx_cr_types[cmd->cmdidx & 0x3f];
  732. u8 c = sdm->mmc.c, r = sdm->mmc.r;
  733. u8 desired_ctype = 0;
  734. if (IS_MMC(mmc)) {
  735. #ifdef MMC_SUPPORTS_TUNING
  736. if (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
  737. if (cmd->resp_type == MMC_RSP_R1)
  738. cr.rtype_xor = 1;
  739. if (data && data->flags & MMC_DATA_READ)
  740. cr.ctype_xor = 1;
  741. }
  742. #endif
  743. return cr;
  744. }
  745. if (cmd->cmdidx == 56)
  746. c = (cmd->cmdarg & 1) ? 1 : 2;
  747. if (data) {
  748. if (data->flags & MMC_DATA_READ)
  749. desired_ctype = 1;
  750. else if (data->flags & MMC_DATA_WRITE)
  751. desired_ctype = 2;
  752. }
  753. cr.ctype_xor = c ^ desired_ctype;
  754. if (slot->is_acmd)
  755. cr.rtype_xor = r ^ sdm->sdacmd.r;
  756. else
  757. cr.rtype_xor = r ^ sdm->sd.r;
  758. debug("%s(%s): mmc c: %d, mmc r: %d, desired c: %d, xor c: %d, xor r: %d\n",
  759. __func__, mmc->dev->name, c, r, desired_ctype,
  760. cr.ctype_xor, cr.rtype_xor);
  761. return cr;
  762. }
  763. /**
  764. * Keep track of switch commands internally
  765. */
  766. static void octeontx_mmc_track_switch(struct mmc *mmc, u32 cmd_arg)
  767. {
  768. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  769. u8 how = (cmd_arg >> 24) & 3;
  770. u8 where = (u8)(cmd_arg >> 16);
  771. u8 val = (u8)(cmd_arg >> 8);
  772. slot->want_switch = slot->cached_switch;
  773. if (slot->is_acmd)
  774. return;
  775. if (how != 3)
  776. return;
  777. switch (where) {
  778. case EXT_CSD_BUS_WIDTH:
  779. slot->want_switch.s.bus_width = val;
  780. break;
  781. case EXT_CSD_POWER_CLASS:
  782. slot->want_switch.s.power_class = val;
  783. break;
  784. case EXT_CSD_HS_TIMING:
  785. slot->want_switch.s.hs_timing = 0;
  786. slot->want_switch.s.hs200_timing = 0;
  787. slot->want_switch.s.hs400_timing = 0;
  788. switch (val & 0xf) {
  789. case 0:
  790. break;
  791. case 1:
  792. slot->want_switch.s.hs_timing = 1;
  793. break;
  794. case 2:
  795. if (!slot->is_asim && !slot->is_emul)
  796. slot->want_switch.s.hs200_timing = 1;
  797. break;
  798. case 3:
  799. if (!slot->is_asim && !slot->is_emul)
  800. slot->want_switch.s.hs400_timing = 1;
  801. break;
  802. default:
  803. pr_err("%s(%s): Unsupported timing mode 0x%x\n",
  804. __func__, mmc->dev->name, val & 0xf);
  805. break;
  806. }
  807. break;
  808. default:
  809. break;
  810. }
  811. }
  812. static int octeontx_mmc_print_rsp_errors(struct mmc *mmc,
  813. union mio_emm_rsp_sts rsp_sts)
  814. {
  815. bool err = false;
  816. const char *name = mmc->dev->name;
  817. if (rsp_sts.s.acc_timeout) {
  818. pr_warn("%s(%s): acc_timeout\n", __func__, name);
  819. err = true;
  820. }
  821. if (rsp_sts.s.dbuf_err) {
  822. pr_warn("%s(%s): dbuf_err\n", __func__, name);
  823. err = true;
  824. }
  825. if (rsp_sts.s.blk_timeout) {
  826. pr_warn("%s(%s): blk_timeout\n", __func__, name);
  827. err = true;
  828. }
  829. if (rsp_sts.s.blk_crc_err) {
  830. pr_warn("%s(%s): blk_crc_err\n", __func__, name);
  831. err = true;
  832. }
  833. if (rsp_sts.s.stp_timeout) {
  834. pr_warn("%s(%s): stp_timeout\n", __func__, name);
  835. err = true;
  836. }
  837. if (rsp_sts.s.stp_crc_err) {
  838. pr_warn("%s(%s): stp_crc_err\n", __func__, name);
  839. err = true;
  840. }
  841. if (rsp_sts.s.stp_bad_sts) {
  842. pr_warn("%s(%s): stp_bad_sts\n", __func__, name);
  843. err = true;
  844. }
  845. if (err)
  846. pr_warn(" rsp_sts: 0x%llx\n", rsp_sts.u);
  847. return err ? -1 : 0;
  848. }
  849. /**
  850. * Starts a DMA operation for block read/write
  851. *
  852. * @param mmc mmc device
  853. * @param write true if write operation
  854. * @param clear true to clear DMA operation
  855. * @param adr source or destination DMA address
  856. * @param size size in blocks
  857. * @param timeout timeout in ms
  858. */
  859. static void octeontx_mmc_start_dma(struct mmc *mmc, bool write,
  860. bool clear, u32 block, dma_addr_t adr,
  861. u32 size, int timeout)
  862. {
  863. const struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  864. union mio_emm_dma_cfg emm_dma_cfg;
  865. union mio_emm_dma_adr emm_dma_adr;
  866. union mio_emm_dma emm_dma;
  867. /* Clear any interrupts */
  868. write_csr(mmc, MIO_EMM_DMA_INT(),
  869. read_csr(mmc, MIO_EMM_DMA_INT()));
  870. emm_dma_cfg.u = 0;
  871. emm_dma_cfg.s.en = 1;
  872. emm_dma_cfg.s.rw = !!write;
  873. emm_dma_cfg.s.clr = !!clear;
  874. emm_dma_cfg.s.size = ((u64)(size * mmc->read_bl_len) / 8) - 1;
  875. #if __BYTE_ORDER != __BIG_ENDIAN
  876. emm_dma_cfg.s.endian = 1;
  877. #endif
  878. emm_dma_adr.u = 0;
  879. emm_dma_adr.s.adr = adr;
  880. write_csr(mmc, MIO_EMM_DMA_ADR(), emm_dma_adr.u);
  881. write_csr(mmc, MIO_EMM_DMA_CFG(), emm_dma_cfg.u);
  882. emm_dma.u = 0;
  883. emm_dma.s.bus_id = slot->bus_id;
  884. emm_dma.s.dma_val = 1;
  885. emm_dma.s.rw = !!write;
  886. emm_dma.s.sector = mmc->high_capacity ? 1 : 0;
  887. if (size > 1 && ((IS_SD(mmc) && (mmc->scr[0] & 2)) || !IS_SD(mmc)))
  888. emm_dma.s.multi = 1;
  889. else
  890. emm_dma.s.multi = 0;
  891. emm_dma.s.block_cnt = size;
  892. if (!mmc->high_capacity)
  893. block *= mmc->read_bl_len;
  894. emm_dma.s.card_addr = block;
  895. debug("%s(%s): card address: 0x%x, size: %d, multi: %d\n",
  896. __func__, mmc->dev->name, block, size, emm_dma.s.multi);
  897. if (timeout > 0)
  898. timeout = (timeout * 1000) - 1000;
  899. set_wdog(mmc, timeout);
  900. debug(" Writing 0x%llx to mio_emm_dma\n", emm_dma.u);
  901. write_csr(mmc, MIO_EMM_DMA(), emm_dma.u);
  902. }
  903. /**
  904. * Waits for a DMA operation to complete
  905. *
  906. * @param mmc mmc device
  907. * @param timeout timeout in ms
  908. *
  909. * @return 0 for success (could be DMA errors), -ETIMEDOUT on timeout
  910. */
  911. /**
  912. * Cleanup DMA engine after a failure
  913. *
  914. * @param mmc mmc device
  915. * @param rsp_sts rsp status
  916. */
  917. static void octeontx_mmc_cleanup_dma(struct mmc *mmc,
  918. union mio_emm_rsp_sts rsp_sts)
  919. {
  920. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  921. union mio_emm_dma emm_dma;
  922. ulong start;
  923. int retries = 3;
  924. do {
  925. debug("%s(%s): rsp_sts: 0x%llx, rsp_lo: 0x%llx, dma_int: 0x%llx\n",
  926. __func__, mmc->dev->name, rsp_sts.u,
  927. read_csr(mmc, MIO_EMM_RSP_LO()),
  928. read_csr(mmc, MIO_EMM_DMA_INT()));
  929. emm_dma.u = read_csr(mmc, MIO_EMM_DMA());
  930. emm_dma.s.dma_val = 1;
  931. emm_dma.s.dat_null = 1;
  932. emm_dma.s.bus_id = slot->bus_id;
  933. write_csr(mmc, MIO_EMM_DMA(), emm_dma.u);
  934. start = get_timer(0);
  935. do {
  936. rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
  937. WATCHDOG_RESET();
  938. } while (get_timer(start) < 100 &&
  939. (rsp_sts.s.dma_val || rsp_sts.s.dma_pend));
  940. } while (retries-- >= 0 && rsp_sts.s.dma_pend);
  941. if (rsp_sts.s.dma_val)
  942. pr_err("%s(%s): Error: could not clean up DMA. RSP_STS: 0x%llx, RSP_LO: 0x%llx\n",
  943. __func__, mmc->dev->name, rsp_sts.u,
  944. read_csr(mmc, MIO_EMM_RSP_LO()));
  945. debug(" rsp_sts after clearing up DMA: 0x%llx\n",
  946. read_csr(mmc, MIO_EMM_RSP_STS()));
  947. }
  948. /**
  949. * Waits for a DMA operation to complete
  950. *
  951. * @param mmc mmc device
  952. * @param timeout timeout in ms
  953. * @param verbose true to print out error information
  954. *
  955. * @return 0 for success (could be DMA errors), -ETIMEDOUT on timeout
  956. * or -EIO if IO error.
  957. */
  958. static int octeontx_mmc_wait_dma(struct mmc *mmc, bool write, ulong timeout,
  959. bool verbose)
  960. {
  961. struct octeontx_mmc_host *host = mmc_to_host(mmc);
  962. ulong start_time = get_timer(0);
  963. union mio_emm_dma_int emm_dma_int;
  964. union mio_emm_rsp_sts rsp_sts;
  965. union mio_emm_dma emm_dma;
  966. bool timed_out = false;
  967. bool err = false;
  968. debug("%s(%s, %lu, %d), delay: %uus\n", __func__, mmc->dev->name,
  969. timeout, verbose, host->dma_wait_delay);
  970. udelay(host->dma_wait_delay);
  971. do {
  972. emm_dma_int.u = read_csr(mmc, MIO_EMM_DMA_INT());
  973. rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
  974. if (write) {
  975. if ((rsp_sts.s.dma_pend && !rsp_sts.s.dma_val) ||
  976. rsp_sts.s.blk_timeout ||
  977. rsp_sts.s.stp_timeout ||
  978. rsp_sts.s.rsp_timeout) {
  979. err = true;
  980. #ifdef DEBUG
  981. debug("%s: f1\n", __func__);
  982. octeontx_mmc_print_rsp_errors(mmc, rsp_sts);
  983. #endif
  984. break;
  985. }
  986. } else {
  987. if (rsp_sts.s.blk_crc_err ||
  988. (rsp_sts.s.dma_pend && !rsp_sts.s.dma_val)) {
  989. err = true;
  990. #if defined(DEBUG)
  991. octeontx_mmc_print_rsp_errors(mmc, rsp_sts);
  992. #endif
  993. break;
  994. }
  995. }
  996. if (rsp_sts.s.dma_pend) {
  997. /*
  998. * If this is set then an error has occurred.
  999. * Try and restart the DMA operation.
  1000. */
  1001. emm_dma.u = read_csr(mmc, MIO_EMM_DMA());
  1002. if (verbose) {
  1003. pr_err("%s(%s): DMA pending error: rsp_sts: 0x%llx, dma_int: 0x%llx, emm_dma: 0x%llx\n",
  1004. __func__, mmc->dev->name, rsp_sts.u,
  1005. emm_dma_int.u, emm_dma.u);
  1006. octeontx_print_rsp_sts(mmc);
  1007. debug(" MIO_EMM_DEBUG: 0x%llx\n",
  1008. read_csr(mmc, MIO_EMM_DEBUG()));
  1009. pr_err("%s: Trying DMA resume...\n", __func__);
  1010. }
  1011. emm_dma.s.dma_val = 1;
  1012. emm_dma.s.dat_null = 1;
  1013. write_csr(mmc, MIO_EMM_DMA(), emm_dma.u);
  1014. udelay(10);
  1015. } else if (!rsp_sts.s.dma_val && emm_dma_int.s.done) {
  1016. break;
  1017. }
  1018. WATCHDOG_RESET();
  1019. timed_out = (get_timer(start_time) > timeout);
  1020. } while (!timed_out);
  1021. if (timed_out || err) {
  1022. if (verbose) {
  1023. pr_err("%s(%s): MMC DMA %s after %lu ms, rsp_sts: 0x%llx, dma_int: 0x%llx, rsp_sts_lo: 0x%llx, emm_dma: 0x%llx\n",
  1024. __func__, mmc->dev->name,
  1025. timed_out ? "timed out" : "error",
  1026. get_timer(start_time), rsp_sts.u,
  1027. emm_dma_int.u,
  1028. read_csr(mmc, MIO_EMM_RSP_LO()),
  1029. read_csr(mmc, MIO_EMM_DMA()));
  1030. octeontx_print_rsp_sts(mmc);
  1031. }
  1032. if (rsp_sts.s.dma_pend)
  1033. octeontx_mmc_cleanup_dma(mmc, rsp_sts);
  1034. } else {
  1035. write_csr(mmc, MIO_EMM_DMA_INT(),
  1036. read_csr(mmc, MIO_EMM_DMA_INT()));
  1037. }
  1038. return timed_out ? -ETIMEDOUT : (err ? -EIO : 0);
  1039. }
  1040. /**
  1041. * Read blocks from the MMC/SD device
  1042. *
  1043. * @param mmc mmc device
  1044. * @param cmd command
  1045. * @param data data for read
  1046. * @param verbose true to print out error information
  1047. *
  1048. * @return number of blocks read or 0 if error
  1049. */
  1050. static int octeontx_mmc_read_blocks(struct mmc *mmc, struct mmc_cmd *cmd,
  1051. struct mmc_data *data, bool verbose)
  1052. {
  1053. struct octeontx_mmc_host *host = mmc_to_host(mmc);
  1054. union mio_emm_rsp_sts rsp_sts;
  1055. dma_addr_t dma_addr = (dma_addr_t)dm_pci_virt_to_mem(host->dev,
  1056. data->dest);
  1057. ulong count;
  1058. ulong blkcnt = data->blocks;
  1059. ulong start = cmd->cmdarg;
  1060. int timeout = 1000 + blkcnt * 20;
  1061. bool timed_out = false;
  1062. bool multi_xfer = cmd->cmdidx == MMC_CMD_READ_MULTIPLE_BLOCK;
  1063. debug("%s(%s): dest: %p, dma address: 0x%llx, blkcnt: %lu, start: %lu\n",
  1064. __func__, mmc->dev->name, data->dest, dma_addr, blkcnt, start);
  1065. debug("%s: rsp_sts: 0x%llx\n", __func__,
  1066. read_csr(mmc, MIO_EMM_RSP_STS()));
  1067. /* use max timeout for multi-block transfers */
  1068. /* timeout = 0; */
  1069. /*
  1070. * If we have a valid SD card in the slot, we set the response bit
  1071. * mask to check for CRC errors and timeouts only.
  1072. * Otherwise, use the default power on reset value.
  1073. */
  1074. write_csr(mmc, MIO_EMM_STS_MASK(),
  1075. IS_SD(mmc) ? 0x00b00000ull : 0xe4390080ull);
  1076. invalidate_dcache_range((u64)data->dest,
  1077. (u64)data->dest + blkcnt * data->blocksize);
  1078. if (multi_xfer) {
  1079. octeontx_mmc_start_dma(mmc, false, false, start, dma_addr,
  1080. blkcnt, timeout);
  1081. timed_out = !!octeontx_mmc_wait_dma(mmc, false, timeout,
  1082. verbose);
  1083. rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
  1084. if (timed_out || rsp_sts.s.dma_val || rsp_sts.s.dma_pend) {
  1085. if (!verbose)
  1086. return 0;
  1087. pr_err("%s(%s): Error: DMA timed out. rsp_sts: 0x%llx, emm_int: 0x%llx, dma_int: 0x%llx, rsp_lo: 0x%llx\n",
  1088. __func__, mmc->dev->name, rsp_sts.u,
  1089. read_csr(mmc, MIO_EMM_INT()),
  1090. read_csr(mmc, MIO_EMM_DMA_INT()),
  1091. read_csr(mmc, MIO_EMM_RSP_LO()));
  1092. pr_err("%s: block count: %lu, start: 0x%lx\n",
  1093. __func__, blkcnt, start);
  1094. octeontx_mmc_print_registers(mmc);
  1095. return 0;
  1096. }
  1097. } else {
  1098. count = blkcnt;
  1099. timeout = 1000;
  1100. do {
  1101. octeontx_mmc_start_dma(mmc, false, false, start,
  1102. dma_addr, 1, timeout);
  1103. dma_addr += mmc->read_bl_len;
  1104. start++;
  1105. timed_out = !!octeontx_mmc_wait_dma(mmc, false,
  1106. timeout, verbose);
  1107. rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
  1108. if (timed_out || rsp_sts.s.dma_val ||
  1109. rsp_sts.s.dma_pend) {
  1110. if (verbose) {
  1111. pr_err("%s: Error: DMA timed out. rsp_sts: 0x%llx, emm_int: 0x%llx, dma_int: 0x%llx, rsp_lo: 0x%llx\n",
  1112. __func__, rsp_sts.u,
  1113. read_csr(mmc, MIO_EMM_INT()),
  1114. read_csr(mmc, MIO_EMM_DMA_INT()),
  1115. read_csr(mmc, MIO_EMM_RSP_LO()));
  1116. pr_err("%s: block count: 1, start: 0x%lx\n",
  1117. __func__, start);
  1118. octeontx_mmc_print_registers(mmc);
  1119. }
  1120. return blkcnt - count;
  1121. }
  1122. WATCHDOG_RESET();
  1123. } while (--count);
  1124. }
  1125. #ifdef DEBUG
  1126. debug("%s(%s): Read %lu (0x%lx) blocks starting at block %u (0x%x) to address %p (dma address 0x%llx)\n",
  1127. __func__, mmc->dev->name, blkcnt, blkcnt,
  1128. cmd->cmdarg, cmd->cmdarg, data->dest,
  1129. dm_pci_virt_to_mem(host->dev, data->dest));
  1130. print_buffer(0, data->dest, 1, 0x200, 0);
  1131. #endif
  1132. return blkcnt;
  1133. }
  1134. static int octeontx_mmc_poll_ready(struct mmc *mmc, ulong timeout)
  1135. {
  1136. ulong start;
  1137. struct mmc_cmd cmd;
  1138. int err;
  1139. bool not_ready = false;
  1140. memset(&cmd, 0, sizeof(cmd));
  1141. cmd.cmdidx = MMC_CMD_SEND_STATUS;
  1142. cmd.cmdarg = mmc->rca << 16;
  1143. cmd.resp_type = MMC_RSP_R1;
  1144. start = get_timer(0);
  1145. do {
  1146. err = octeontx_mmc_send_cmd(mmc, &cmd, NULL);
  1147. if (err) {
  1148. pr_err("%s(%s): MMC command error: %d; Retry...\n",
  1149. __func__, mmc->dev->name, err);
  1150. not_ready = true;
  1151. } else if (cmd.response[0] & R1_READY_FOR_DATA) {
  1152. return 0;
  1153. }
  1154. WATCHDOG_RESET();
  1155. } while (get_timer(start) < timeout);
  1156. if (not_ready)
  1157. pr_err("%s(%s): MMC command error; Retry timeout\n",
  1158. __func__, mmc->dev->name);
  1159. return -ETIMEDOUT;
  1160. }
  1161. static ulong octeontx_mmc_write_blocks(struct mmc *mmc, struct mmc_cmd *cmd,
  1162. struct mmc_data *data)
  1163. {
  1164. struct octeontx_mmc_host *host = mmc_to_host(mmc);
  1165. ulong start = cmd->cmdarg;
  1166. ulong blkcnt = data->blocks;
  1167. dma_addr_t dma_addr;
  1168. union mio_emm_rsp_sts rsp_sts;
  1169. union mio_emm_sts_mask emm_sts_mask;
  1170. ulong timeout;
  1171. int count;
  1172. bool timed_out = false;
  1173. bool multi_xfer = (blkcnt > 1) &&
  1174. ((IS_SD(mmc) && mmc->scr[0] & 2) || !IS_SD(mmc));
  1175. octeontx_mmc_switch_to(mmc);
  1176. emm_sts_mask.u = 0;
  1177. emm_sts_mask.s.sts_msk = R1_BLOCK_WRITE_MASK;
  1178. write_csr(mmc, MIO_EMM_STS_MASK(), emm_sts_mask.u);
  1179. if (octeontx_mmc_poll_ready(mmc, 10000)) {
  1180. pr_err("%s(%s): Ready timed out\n", __func__, mmc->dev->name);
  1181. return 0;
  1182. }
  1183. flush_dcache_range((u64)data->src,
  1184. (u64)data->src + blkcnt * mmc->write_bl_len);
  1185. dma_addr = (u64)dm_pci_virt_to_mem(host->dev, (void *)data->src);
  1186. if (multi_xfer) {
  1187. timeout = 5000 + 100 * blkcnt;
  1188. octeontx_mmc_start_dma(mmc, true, false, start, dma_addr,
  1189. blkcnt, timeout);
  1190. timed_out = !!octeontx_mmc_wait_dma(mmc, true, timeout, true);
  1191. rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
  1192. if (timed_out || rsp_sts.s.dma_val || rsp_sts.s.dma_pend) {
  1193. pr_err("%s(%s): Error: multi-DMA timed out after %lums. rsp_sts: 0x%llx, emm_int: 0x%llx, emm_dma_int: 0x%llx, rsp_sts_lo: 0x%llx, emm_dma: 0x%llx\n",
  1194. __func__, mmc->dev->name, timeout,
  1195. rsp_sts.u,
  1196. read_csr(mmc, MIO_EMM_INT()),
  1197. read_csr(mmc, MIO_EMM_DMA_INT()),
  1198. read_csr(mmc, MIO_EMM_RSP_LO()),
  1199. read_csr(mmc, MIO_EMM_DMA()));
  1200. return 0;
  1201. }
  1202. } else {
  1203. timeout = 5000;
  1204. count = blkcnt;
  1205. do {
  1206. octeontx_mmc_start_dma(mmc, true, false, start,
  1207. dma_addr, 1, timeout);
  1208. dma_addr += mmc->read_bl_len;
  1209. start++;
  1210. timed_out = !!octeontx_mmc_wait_dma(mmc, true, timeout,
  1211. true);
  1212. rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
  1213. if (timed_out || rsp_sts.s.dma_val ||
  1214. rsp_sts.s.dma_pend) {
  1215. pr_err("%s(%s): Error: single-DMA timed out after %lums. rsp_sts: 0x%llx, emm_int: 0x%llx, emm_dma_int: 0x%llx, rsp_sts_lo: 0x%llx, emm_dma: 0x%llx\n",
  1216. __func__, mmc->dev->name, timeout,
  1217. rsp_sts.u,
  1218. read_csr(mmc, MIO_EMM_RSP_STS()),
  1219. read_csr(mmc, MIO_EMM_DMA_INT()),
  1220. read_csr(mmc, MIO_EMM_RSP_LO()),
  1221. read_csr(mmc, MIO_EMM_DMA()));
  1222. return blkcnt - count;
  1223. }
  1224. WATCHDOG_RESET();
  1225. } while (--count);
  1226. }
  1227. return blkcnt;
  1228. }
  1229. /**
  1230. * Send a command to the eMMC/SD device
  1231. *
  1232. * @param mmc mmc device
  1233. * @param cmd cmd to send and response
  1234. * @param data additional data
  1235. * @param flags
  1236. * @return 0 for success, otherwise error
  1237. */
  1238. static int octeontx_mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  1239. struct mmc_data *data)
  1240. {
  1241. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  1242. const char *name = slot->dev->name;
  1243. struct octeontx_mmc_cr_mods mods = {0, 0};
  1244. union mio_emm_rsp_sts rsp_sts;
  1245. union mio_emm_cmd emm_cmd;
  1246. union mio_emm_rsp_lo rsp_lo;
  1247. union mio_emm_buf_idx emm_buf_idx;
  1248. union mio_emm_buf_dat emm_buf_dat;
  1249. ulong start;
  1250. int i;
  1251. ulong blkcnt;
  1252. /**
  1253. * This constant has a 1 bit for each command which should have a short
  1254. * timeout and a 0 for each bit with a long timeout. Currently the
  1255. * following commands have a long timeout:
  1256. * CMD6, CMD17, CMD18, CMD24, CMD25, CMD32, CMD33, CMD35, CMD36 and
  1257. * CMD38.
  1258. */
  1259. static const u64 timeout_short = 0xFFFFFFA4FCF9FFDFull;
  1260. uint timeout;
  1261. if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD) {
  1262. union mio_emm_rca emm_rca;
  1263. emm_rca.u = 0;
  1264. emm_rca.s.card_rca = mmc->rca;
  1265. write_csr(mmc, MIO_EMM_RCA(), emm_rca.u);
  1266. }
  1267. if (timeout_short & (1ull << cmd->cmdidx))
  1268. timeout = MMC_TIMEOUT_SHORT;
  1269. else if (cmd->cmdidx == MMC_CMD_SWITCH && IS_SD(mmc))
  1270. timeout = 2560;
  1271. else if (cmd->cmdidx == MMC_CMD_ERASE)
  1272. timeout = MMC_TIMEOUT_ERASE;
  1273. else
  1274. timeout = MMC_TIMEOUT_LONG;
  1275. debug("%s(%s): cmd idx: %u, arg: 0x%x, resp type: 0x%x, timeout: %u\n",
  1276. __func__, name, cmd->cmdidx, cmd->cmdarg, cmd->resp_type,
  1277. timeout);
  1278. if (data)
  1279. debug(" data: addr: %p, flags: 0x%x, blocks: %u, blocksize: %u\n",
  1280. data->dest, data->flags, data->blocks, data->blocksize);
  1281. octeontx_mmc_switch_to(mmc);
  1282. /* Clear any interrupts */
  1283. write_csr(mmc, MIO_EMM_INT(), read_csr(mmc, MIO_EMM_INT()));
  1284. /*
  1285. * We need to override the default command types and response types
  1286. * when dealing with SD cards.
  1287. */
  1288. mods = octeontx_mmc_get_cr_mods(mmc, cmd, data);
  1289. /* Handle block read/write/stop operations */
  1290. switch (cmd->cmdidx) {
  1291. case MMC_CMD_GO_IDLE_STATE:
  1292. slot->tuned = false;
  1293. slot->hs200_tuned = false;
  1294. slot->hs400_tuned = false;
  1295. break;
  1296. case MMC_CMD_STOP_TRANSMISSION:
  1297. return 0;
  1298. case MMC_CMD_READ_MULTIPLE_BLOCK:
  1299. case MMC_CMD_READ_SINGLE_BLOCK:
  1300. pr_debug("%s(%s): Reading blocks\n", __func__, name);
  1301. blkcnt = octeontx_mmc_read_blocks(mmc, cmd, data, true);
  1302. return (blkcnt > 0) ? 0 : -1;
  1303. case MMC_CMD_WRITE_MULTIPLE_BLOCK:
  1304. case MMC_CMD_WRITE_SINGLE_BLOCK:
  1305. blkcnt = octeontx_mmc_write_blocks(mmc, cmd, data);
  1306. return (blkcnt > 0) ? 0 : -1;
  1307. case MMC_CMD_SELECT_CARD:
  1308. /* Set the RCA register (is it set automatically?) */
  1309. if (IS_SD(mmc)) {
  1310. union mio_emm_rca emm_rca;
  1311. emm_rca.u = 0;
  1312. emm_rca.s.card_rca = (cmd->cmdarg >> 16);
  1313. write_csr(mmc, MIO_EMM_RCA(), emm_rca.u);
  1314. debug("%s: Set SD relative address (RCA) to 0x%x\n",
  1315. __func__, emm_rca.s.card_rca);
  1316. }
  1317. break;
  1318. case MMC_CMD_SWITCH:
  1319. if (!data && !slot->is_acmd)
  1320. octeontx_mmc_track_switch(mmc, cmd->cmdarg);
  1321. break;
  1322. }
  1323. emm_cmd.u = 0;
  1324. emm_cmd.s.cmd_val = 1;
  1325. emm_cmd.s.bus_id = slot->bus_id;
  1326. emm_cmd.s.cmd_idx = cmd->cmdidx;
  1327. emm_cmd.s.arg = cmd->cmdarg;
  1328. emm_cmd.s.ctype_xor = mods.ctype_xor;
  1329. emm_cmd.s.rtype_xor = mods.rtype_xor;
  1330. if (data && data->blocks == 1 && data->blocksize != 512) {
  1331. emm_cmd.s.offset =
  1332. 64 - ((data->blocks * data->blocksize) / 8);
  1333. debug("%s: offset set to %u\n", __func__, emm_cmd.s.offset);
  1334. }
  1335. if (data && data->flags & MMC_DATA_WRITE) {
  1336. u8 *src = (u8 *)data->src;
  1337. if (!src) {
  1338. pr_err("%s(%s): Error: data source for cmd 0x%x is NULL!\n",
  1339. __func__, name, cmd->cmdidx);
  1340. return -1;
  1341. }
  1342. if (data->blocksize > 512) {
  1343. pr_err("%s(%s): Error: data for cmd 0x%x exceeds 512 bytes\n",
  1344. __func__, name, cmd->cmdidx);
  1345. return -1;
  1346. }
  1347. #ifdef DEBUG
  1348. debug("%s: Sending %d bytes data\n", __func__, data->blocksize);
  1349. print_buffer(0, src, 1, data->blocksize, 0);
  1350. #endif
  1351. emm_buf_idx.u = 0;
  1352. emm_buf_idx.s.inc = 1;
  1353. write_csr(mmc, MIO_EMM_BUF_IDX(), emm_buf_idx.u);
  1354. for (i = 0; i < (data->blocksize + 7) / 8; i++) {
  1355. memcpy(&emm_buf_dat.u, src, sizeof(emm_buf_dat.u));
  1356. write_csr(mmc, MIO_EMM_BUF_DAT(),
  1357. cpu_to_be64(emm_buf_dat.u));
  1358. src += sizeof(emm_buf_dat.u);
  1359. }
  1360. write_csr(mmc, MIO_EMM_BUF_IDX(), 0);
  1361. }
  1362. debug("%s(%s): Sending command %u (emm_cmd: 0x%llx)\n", __func__,
  1363. name, cmd->cmdidx, emm_cmd.u);
  1364. set_wdog(mmc, timeout * 1000);
  1365. write_csr(mmc, MIO_EMM_CMD(), emm_cmd.u);
  1366. /* Wait for command to finish or time out */
  1367. start = get_timer(0);
  1368. do {
  1369. rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
  1370. WATCHDOG_RESET();
  1371. } while (!rsp_sts.s.cmd_done && !rsp_sts.s.rsp_timeout &&
  1372. (get_timer(start) < timeout + 10));
  1373. octeontx_mmc_print_rsp_errors(mmc, rsp_sts);
  1374. if (rsp_sts.s.rsp_timeout || !rsp_sts.s.cmd_done) {
  1375. debug("%s(%s): Error: command %u(0x%x) timed out. rsp_sts: 0x%llx\n",
  1376. __func__, name, cmd->cmdidx, cmd->cmdarg, rsp_sts.u);
  1377. octeontx_mmc_print_registers(mmc);
  1378. return -ETIMEDOUT;
  1379. }
  1380. if (rsp_sts.s.rsp_crc_err) {
  1381. debug("%s(%s): RSP CRC error, rsp_sts: 0x%llx, cmdidx: %u, arg: 0x%08x\n",
  1382. __func__, name, rsp_sts.u, cmd->cmdidx, cmd->cmdarg);
  1383. octeontx_mmc_print_registers(mmc);
  1384. return -1;
  1385. }
  1386. if (slot->bus_id != rsp_sts.s.bus_id) {
  1387. pr_warn("%s(%s): bus id mismatch, got %d, expected %d for command 0x%x(0x%x)\n",
  1388. __func__, name,
  1389. rsp_sts.s.bus_id, slot->bus_id,
  1390. cmd->cmdidx, cmd->cmdarg);
  1391. goto error;
  1392. }
  1393. if (rsp_sts.s.rsp_bad_sts) {
  1394. rsp_lo.u = read_csr(mmc, MIO_EMM_RSP_LO());
  1395. debug("%s: Bad response for bus id %d, cmd id %d:\n"
  1396. " rsp_timeout: %d\n"
  1397. " rsp_bad_sts: %d\n"
  1398. " rsp_crc_err: %d\n",
  1399. __func__, slot->bus_id, cmd->cmdidx,
  1400. rsp_sts.s.rsp_timeout,
  1401. rsp_sts.s.rsp_bad_sts,
  1402. rsp_sts.s.rsp_crc_err);
  1403. if (rsp_sts.s.rsp_type == 1 && rsp_sts.s.rsp_bad_sts) {
  1404. debug(" Response status: 0x%llx\n",
  1405. (rsp_lo.u >> 8) & 0xffffffff);
  1406. #ifdef DEBUG
  1407. mmc_print_status((rsp_lo.u >> 8) & 0xffffffff);
  1408. #endif
  1409. }
  1410. goto error;
  1411. }
  1412. if (rsp_sts.s.cmd_idx != cmd->cmdidx) {
  1413. debug("%s(%s): Command response index %d does not match command index %d\n",
  1414. __func__, name, rsp_sts.s.cmd_idx, cmd->cmdidx);
  1415. octeontx_print_rsp_sts(mmc);
  1416. debug("%s: rsp_lo: 0x%llx\n", __func__,
  1417. read_csr(mmc, MIO_EMM_RSP_LO()));
  1418. goto error;
  1419. }
  1420. slot->is_acmd = (cmd->cmdidx == MMC_CMD_APP_CMD);
  1421. if (!cmd->resp_type & MMC_RSP_PRESENT)
  1422. debug(" Response type: 0x%x, no response expected\n",
  1423. cmd->resp_type);
  1424. /* Get the response if present */
  1425. if (rsp_sts.s.rsp_val && (cmd->resp_type & MMC_RSP_PRESENT)) {
  1426. union mio_emm_rsp_hi rsp_hi;
  1427. rsp_lo.u = read_csr(mmc, MIO_EMM_RSP_LO());
  1428. switch (rsp_sts.s.rsp_type) {
  1429. case 1:
  1430. case 3:
  1431. case 4:
  1432. case 5:
  1433. cmd->response[0] = (rsp_lo.u >> 8) & 0xffffffffull;
  1434. debug(" response: 0x%08x\n",
  1435. cmd->response[0]);
  1436. cmd->response[1] = 0;
  1437. cmd->response[2] = 0;
  1438. cmd->response[3] = 0;
  1439. break;
  1440. case 2:
  1441. cmd->response[3] = rsp_lo.u & 0xffffffff;
  1442. cmd->response[2] = (rsp_lo.u >> 32) & 0xffffffff;
  1443. rsp_hi.u = read_csr(mmc, MIO_EMM_RSP_HI());
  1444. cmd->response[1] = rsp_hi.u & 0xffffffff;
  1445. cmd->response[0] = (rsp_hi.u >> 32) & 0xffffffff;
  1446. debug(" response: 0x%08x 0x%08x 0x%08x 0x%08x\n",
  1447. cmd->response[0], cmd->response[1],
  1448. cmd->response[2], cmd->response[3]);
  1449. break;
  1450. default:
  1451. pr_err("%s(%s): Unknown response type 0x%x for command %d, arg: 0x%x, rsp_sts: 0x%llx\n",
  1452. __func__, name, rsp_sts.s.rsp_type, cmd->cmdidx,
  1453. cmd->cmdarg, rsp_sts.u);
  1454. return -1;
  1455. }
  1456. } else {
  1457. debug(" Response not expected\n");
  1458. }
  1459. if (data && data->flags & MMC_DATA_READ) {
  1460. u8 *dest = (u8 *)data->dest;
  1461. if (!dest) {
  1462. pr_err("%s(%s): Error, destination buffer NULL!\n",
  1463. __func__, mmc->dev->name);
  1464. goto error;
  1465. }
  1466. if (data->blocksize > 512) {
  1467. printf("%s(%s): Error: data size %u exceeds 512\n",
  1468. __func__, mmc->dev->name,
  1469. data->blocksize);
  1470. goto error;
  1471. }
  1472. emm_buf_idx.u = 0;
  1473. emm_buf_idx.s.inc = 1;
  1474. write_csr(mmc, MIO_EMM_BUF_IDX(), emm_buf_idx.u);
  1475. for (i = 0; i < (data->blocksize + 7) / 8; i++) {
  1476. emm_buf_dat.u = read_csr(mmc, MIO_EMM_BUF_DAT());
  1477. emm_buf_dat.u = be64_to_cpu(emm_buf_dat.u);
  1478. memcpy(dest, &emm_buf_dat.u, sizeof(emm_buf_dat.u));
  1479. dest += sizeof(emm_buf_dat.u);
  1480. }
  1481. write_csr(mmc, MIO_EMM_BUF_IDX(), 0);
  1482. #ifdef DEBUG
  1483. debug("%s: Received %d bytes data\n", __func__,
  1484. data->blocksize);
  1485. print_buffer(0, data->dest, 1, data->blocksize, 0);
  1486. #endif
  1487. }
  1488. return 0;
  1489. error:
  1490. #ifdef DEBUG
  1491. octeontx_mmc_print_registers(mmc);
  1492. #endif
  1493. return -1;
  1494. }
  1495. static int octeontx_mmc_dev_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  1496. struct mmc_data *data)
  1497. {
  1498. return octeontx_mmc_send_cmd(dev_to_mmc(dev), cmd, data);
  1499. }
  1500. #ifdef MMC_SUPPORTS_TUNING
  1501. static int octeontx_mmc_test_cmd(struct mmc *mmc, u32 opcode, int *statp)
  1502. {
  1503. struct mmc_cmd cmd;
  1504. int err;
  1505. memset(&cmd, 0, sizeof(cmd));
  1506. debug("%s(%s, %u, %p)\n", __func__, mmc->dev->name, opcode, statp);
  1507. cmd.cmdidx = opcode;
  1508. cmd.resp_type = MMC_RSP_R1;
  1509. cmd.cmdarg = mmc->rca << 16;
  1510. err = octeontx_mmc_send_cmd(mmc, &cmd, NULL);
  1511. if (err)
  1512. debug("%s(%s, %u) returned %d\n", __func__,
  1513. mmc->dev->name, opcode, err);
  1514. if (statp)
  1515. *statp = cmd.response[0];
  1516. return err;
  1517. }
  1518. static int octeontx_mmc_test_get_ext_csd(struct mmc *mmc, u32 opcode,
  1519. int *statp)
  1520. {
  1521. struct mmc_cmd cmd;
  1522. struct mmc_data data;
  1523. int err;
  1524. u8 ext_csd[MMC_MAX_BLOCK_LEN];
  1525. debug("%s(%s, %u, %p)\n", __func__, mmc->dev->name, opcode, statp);
  1526. memset(&cmd, 0, sizeof(cmd));
  1527. cmd.cmdidx = MMC_CMD_SEND_EXT_CSD;
  1528. cmd.resp_type = MMC_RSP_R1;
  1529. cmd.cmdarg = 0;
  1530. data.dest = (char *)ext_csd;
  1531. data.blocks = 1;
  1532. data.blocksize = MMC_MAX_BLOCK_LEN;
  1533. data.flags = MMC_DATA_READ;
  1534. err = octeontx_mmc_send_cmd(mmc, &cmd, &data);
  1535. if (statp)
  1536. *statp = cmd.response[0];
  1537. return err;
  1538. }
  1539. /**
  1540. * Wrapper to set the MIO_EMM_TIMING register
  1541. *
  1542. * @param mmc pointer to mmc data structure
  1543. * @param emm_timing New emm_timing register value
  1544. *
  1545. * On some devices it is possible that changing the data out value can
  1546. * cause a glitch on an internal fifo. This works around this problem
  1547. * by performing a soft-reset immediately before setting the timing register.
  1548. *
  1549. * Note: this function should not be called from any function that
  1550. * performs DMA or block operations since not all registers are
  1551. * preserved.
  1552. */
  1553. static void octeontx_mmc_set_emm_timing(struct mmc *mmc,
  1554. union mio_emm_timing emm_timing)
  1555. {
  1556. union mio_emm_cfg emm_cfg;
  1557. struct octeontx_mmc_slot *slot = mmc->priv;
  1558. union mio_emm_debug emm_debug;
  1559. debug("%s(%s, 0x%llx) din: %u\n", __func__, mmc->dev->name,
  1560. emm_timing.u, emm_timing.s.data_in_tap);
  1561. udelay(1);
  1562. if (slot->host->tap_requires_noclk) {
  1563. /* Turn off the clock */
  1564. emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
  1565. emm_debug.s.emmc_clk_disable = 1;
  1566. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  1567. udelay(1);
  1568. emm_debug.s.rdsync_rst = 1;
  1569. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  1570. }
  1571. emm_cfg.u = read_csr(mmc, MIO_EMM_CFG());
  1572. emm_cfg.s.bus_ena = 1 << 3;
  1573. write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
  1574. udelay(1);
  1575. write_csr(mmc, MIO_EMM_TIMING(), emm_timing.u);
  1576. udelay(1);
  1577. if (slot->host->tap_requires_noclk) {
  1578. /* Turn on the clock */
  1579. emm_debug.s.rdsync_rst = 0;
  1580. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  1581. udelay(1);
  1582. emm_debug.s.emmc_clk_disable = 0;
  1583. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  1584. udelay(1);
  1585. }
  1586. emm_cfg.s.bus_ena = 1 << mmc_to_slot(mmc)->bus_id;
  1587. write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
  1588. }
  1589. static const u8 octeontx_hs400_tuning_block[512] = {
  1590. 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
  1591. 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
  1592. 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
  1593. 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
  1594. 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
  1595. 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
  1596. 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
  1597. 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
  1598. 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
  1599. 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
  1600. 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
  1601. 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
  1602. 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
  1603. 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
  1604. 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
  1605. 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
  1606. 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
  1607. 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
  1608. 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
  1609. 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
  1610. 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
  1611. 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
  1612. 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
  1613. 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
  1614. 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
  1615. 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
  1616. 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
  1617. 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
  1618. 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
  1619. 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
  1620. 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
  1621. 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
  1622. 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
  1623. 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
  1624. 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
  1625. 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
  1626. 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
  1627. 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
  1628. 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
  1629. 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
  1630. 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
  1631. 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
  1632. 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
  1633. 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
  1634. 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
  1635. 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
  1636. 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
  1637. 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
  1638. 0xff, 0x00, 0x00, 0xff, 0xff, 0x00, 0xff, 0x00,
  1639. 0x00, 0xff, 0x00, 0xff, 0x55, 0xaa, 0x55, 0xaa,
  1640. 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
  1641. 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
  1642. 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
  1643. 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
  1644. 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
  1645. 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
  1646. 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00,
  1647. 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff,
  1648. 0x01, 0xfe, 0x01, 0xfe, 0xcc, 0xcc, 0xcc, 0xff,
  1649. 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
  1650. 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
  1651. 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
  1652. 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
  1653. 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
  1654. };
  1655. /**
  1656. * Perform tuning in HS400 mode
  1657. *
  1658. * @param[in] mmc mmc data structure
  1659. *
  1660. * @ret 0 for success, otherwise error
  1661. */
  1662. static int octeontx_tune_hs400(struct mmc *mmc)
  1663. {
  1664. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  1665. struct mmc_cmd cmd;
  1666. struct mmc_data data;
  1667. union mio_emm_timing emm_timing;
  1668. u8 buffer[mmc->read_bl_len];
  1669. int tap_adj;
  1670. int err = -1;
  1671. int tap;
  1672. int run = 0;
  1673. int start_run = -1;
  1674. int best_run = 0;
  1675. int best_start = -1;
  1676. bool prev_ok = false;
  1677. char env_name[64];
  1678. char how[MAX_NO_OF_TAPS + 1] = "";
  1679. if (slot->hs400_tuning_block == -1)
  1680. return 0;
  1681. /* The eMMC standard disables all tuning support when operating in
  1682. * DDR modes like HS400. The problem with this is that there are
  1683. * many cases where the HS200 tuning does not work for HS400 mode.
  1684. * In order to perform this tuning, while in HS200 a block is written
  1685. * to a block specified in the device tree (marvell,hs400-tuning-block)
  1686. * which is used for tuning in this function by repeatedly reading
  1687. * this block and comparing the data and return code. This function
  1688. * chooses the data input tap in the middle of the longest run of
  1689. * successful read operations.
  1690. */
  1691. emm_timing = slot->hs200_taps;
  1692. debug("%s(%s): Start ci: %d, co: %d, di: %d, do: %d\n",
  1693. __func__, mmc->dev->name, emm_timing.s.cmd_in_tap,
  1694. emm_timing.s.cmd_out_tap, emm_timing.s.data_in_tap,
  1695. emm_timing.s.data_out_tap);
  1696. memset(buffer, 0xdb, sizeof(buffer));
  1697. snprintf(env_name, sizeof(env_name), "emmc%d_data_in_tap_hs400",
  1698. slot->bus_id);
  1699. tap = env_get_ulong(env_name, 10, -1L);
  1700. if (tap >= 0 && tap < MAX_NO_OF_TAPS) {
  1701. printf("Overriding data input tap for HS400 mode to %d\n", tap);
  1702. emm_timing.s.data_in_tap = tap;
  1703. octeontx_mmc_set_emm_timing(mmc, emm_timing);
  1704. return 0;
  1705. }
  1706. for (tap = 0; tap <= MAX_NO_OF_TAPS; tap++, prev_ok = !err) {
  1707. if (tap < MAX_NO_OF_TAPS) {
  1708. debug("%s: Testing data in tap %d\n", __func__, tap);
  1709. emm_timing.s.data_in_tap = tap;
  1710. octeontx_mmc_set_emm_timing(mmc, emm_timing);
  1711. cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
  1712. cmd.cmdarg = slot->hs400_tuning_block;
  1713. cmd.resp_type = MMC_RSP_R1;
  1714. data.dest = (void *)buffer;
  1715. data.blocks = 1;
  1716. data.blocksize = mmc->read_bl_len;
  1717. data.flags = MMC_DATA_READ;
  1718. err = !octeontx_mmc_read_blocks(mmc, &cmd, &data,
  1719. false);
  1720. if (err || memcmp(buffer, octeontx_hs400_tuning_block,
  1721. sizeof(buffer))) {
  1722. #ifdef DEBUG
  1723. if (!err) {
  1724. debug("%s: data mismatch. Read:\n",
  1725. __func__);
  1726. print_buffer(0, buffer, 1,
  1727. sizeof(buffer), 0);
  1728. debug("\nExpected:\n");
  1729. print_buffer(0,
  1730. octeontx_hs400_tuning_block, 1,
  1731. sizeof(octeontx_hs400_tuning_block),
  1732. 0);
  1733. } else {
  1734. debug("%s: Error %d reading block\n",
  1735. __func__, err);
  1736. }
  1737. #endif
  1738. err = -EINVAL;
  1739. } else {
  1740. debug("%s: tap %d good\n", __func__, tap);
  1741. }
  1742. how[tap] = "-+"[!err];
  1743. } else {
  1744. err = -EINVAL;
  1745. }
  1746. if (!err) {
  1747. if (!prev_ok)
  1748. start_run = tap;
  1749. } else if (prev_ok) {
  1750. run = tap - 1 - start_run;
  1751. if (start_run >= 0 && run > best_run) {
  1752. best_start = start_run;
  1753. best_run = run;
  1754. }
  1755. }
  1756. }
  1757. how[tap - 1] = '\0';
  1758. if (best_start < 0) {
  1759. printf("%s(%s): %lldMHz tuning failed for HS400\n",
  1760. __func__, mmc->dev->name, slot->clock / 1000000);
  1761. return -EINVAL;
  1762. }
  1763. tap = best_start + best_run / 2;
  1764. snprintf(env_name, sizeof(env_name), "emmc%d_data_in_tap_adj_hs400",
  1765. slot->bus_id);
  1766. tap_adj = env_get_ulong(env_name, 10, slot->hs400_tap_adj);
  1767. /*
  1768. * Keep it in range and if out of range force it back in with a small
  1769. * buffer.
  1770. */
  1771. if (best_run > 3) {
  1772. tap = tap + tap_adj;
  1773. if (tap >= best_start + best_run)
  1774. tap = best_start + best_run - 2;
  1775. if (tap <= best_start)
  1776. tap = best_start + 2;
  1777. }
  1778. how[tap] = '@';
  1779. debug("Tuning: %s\n", how);
  1780. debug("%s(%s): HS400 tap: best run start: %d, length: %d, tap: %d\n",
  1781. __func__, mmc->dev->name, best_start, best_run, tap);
  1782. slot->hs400_taps = slot->hs200_taps;
  1783. slot->hs400_taps.s.data_in_tap = tap;
  1784. slot->hs400_tuned = true;
  1785. if (env_get_yesno("emmc_export_hs400_taps") > 0) {
  1786. debug("%s(%s): Exporting HS400 taps\n",
  1787. __func__, mmc->dev->name);
  1788. env_set_ulong("emmc_timing_tap", slot->host->timing_taps);
  1789. snprintf(env_name, sizeof(env_name),
  1790. "emmc%d_hs400_data_in_tap_debug",
  1791. slot->bus_id);
  1792. env_set(env_name, how);
  1793. snprintf(env_name, sizeof(env_name),
  1794. "emmc%d_hs400_data_in_tap_val",
  1795. slot->bus_id);
  1796. env_set_ulong(env_name, tap);
  1797. snprintf(env_name, sizeof(env_name),
  1798. "emmc%d_hs400_data_in_tap_start",
  1799. slot->bus_id);
  1800. env_set_ulong(env_name, best_start);
  1801. snprintf(env_name, sizeof(env_name),
  1802. "emmc%d_hs400_data_in_tap_end",
  1803. slot->bus_id);
  1804. env_set_ulong(env_name, best_start + best_run);
  1805. snprintf(env_name, sizeof(env_name),
  1806. "emmc%d_hs400_cmd_in_tap",
  1807. slot->bus_id);
  1808. env_set_ulong(env_name, slot->hs400_taps.s.cmd_in_tap);
  1809. snprintf(env_name, sizeof(env_name),
  1810. "emmc%d_hs400_cmd_out_tap",
  1811. slot->bus_id);
  1812. env_set_ulong(env_name, slot->hs400_taps.s.cmd_out_tap);
  1813. snprintf(env_name, sizeof(env_name),
  1814. "emmc%d_hs400_cmd_out_delay",
  1815. slot->bus_id);
  1816. env_set_ulong(env_name, slot->cmd_out_hs400_delay);
  1817. snprintf(env_name, sizeof(env_name),
  1818. "emmc%d_hs400_data_out_tap",
  1819. slot->bus_id);
  1820. env_set_ulong(env_name, slot->hs400_taps.s.data_out_tap);
  1821. snprintf(env_name, sizeof(env_name),
  1822. "emmc%d_hs400_data_out_delay",
  1823. slot->bus_id);
  1824. env_set_ulong(env_name, slot->data_out_hs400_delay);
  1825. } else {
  1826. debug("%s(%s): HS400 environment export disabled\n",
  1827. __func__, mmc->dev->name);
  1828. }
  1829. octeontx_mmc_set_timing(mmc);
  1830. return 0;
  1831. }
  1832. struct adj {
  1833. const char *name;
  1834. u8 mask_shift;
  1835. int (*test)(struct mmc *mmc, u32 opcode, int *error);
  1836. u32 opcode;
  1837. bool ddr_only;
  1838. bool hs200_only;
  1839. bool not_hs200_only;
  1840. u8 num_runs;
  1841. };
  1842. struct adj adj[] = {
  1843. { "CMD_IN", 48, octeontx_mmc_test_cmd, MMC_CMD_SEND_STATUS,
  1844. false, false, false, 2, },
  1845. /* { "CMD_OUT", 32, octeontx_mmc_test_cmd, MMC_CMD_SEND_STATUS, },*/
  1846. { "DATA_IN(HS200)", 16, mmc_send_tuning,
  1847. MMC_CMD_SEND_TUNING_BLOCK_HS200, false, true, false, 2, },
  1848. { "DATA_IN", 16, octeontx_mmc_test_get_ext_csd, 0, false, false,
  1849. true, 2, },
  1850. /* { "DATA_OUT", 0, octeontx_mmc_test_cmd, 0, true, false},*/
  1851. { NULL, },
  1852. };
  1853. /**
  1854. * Perform tuning tests to find optimal timing
  1855. *
  1856. * @param mmc mmc device
  1857. * @param adj parameter to tune
  1858. * @param opcode command opcode to use
  1859. *
  1860. * @return 0 for success, -1 if tuning failed
  1861. */
  1862. static int octeontx_mmc_adjust_tuning(struct mmc *mmc, struct adj *adj,
  1863. u32 opcode)
  1864. {
  1865. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  1866. union mio_emm_timing timing;
  1867. union mio_emm_debug emm_debug;
  1868. int tap;
  1869. int err = -1;
  1870. int run = 0;
  1871. int count;
  1872. int start_run = -1;
  1873. int best_run = 0;
  1874. int best_start = -1;
  1875. bool prev_ok = false;
  1876. u64 tap_status = 0;
  1877. const int tap_adj = slot->hs200_tap_adj;
  1878. char how[MAX_NO_OF_TAPS + 1] = "";
  1879. bool is_hs200 = mmc->selected_mode == MMC_HS_200;
  1880. debug("%s(%s, %s, %d), hs200: %d\n", __func__, mmc->dev->name,
  1881. adj->name, opcode, is_hs200);
  1882. octeontx_mmc_set_emm_timing(mmc,
  1883. is_hs200 ? slot->hs200_taps : slot->taps);
  1884. #ifdef DEBUG
  1885. if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
  1886. printf("%s(%s): Before tuning %s, opcode: %d\n",
  1887. __func__, mmc->dev->name, adj->name, opcode);
  1888. octeontx_mmc_print_registers2(mmc, NULL);
  1889. }
  1890. #endif
  1891. /*
  1892. * The algorithm to find the optimal timing is to start
  1893. * at the end and work backwards and select the second
  1894. * value that passes. Each test is repeated twice.
  1895. */
  1896. for (tap = 0; tap <= MAX_NO_OF_TAPS; tap++, prev_ok = !err) {
  1897. if (tap < MAX_NO_OF_TAPS) {
  1898. if (slot->host->tap_requires_noclk) {
  1899. /* Turn off the clock */
  1900. emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
  1901. emm_debug.s.emmc_clk_disable = 1;
  1902. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  1903. udelay(1);
  1904. emm_debug.s.rdsync_rst = 1;
  1905. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  1906. udelay(1);
  1907. }
  1908. timing.u = read_csr(mmc, MIO_EMM_TIMING());
  1909. timing.u &= ~(0x3full << adj->mask_shift);
  1910. timing.u |= (u64)tap << adj->mask_shift;
  1911. write_csr(mmc, MIO_EMM_TIMING(), timing.u);
  1912. debug("%s(%s): Testing ci: %d, co: %d, di: %d, do: %d\n",
  1913. __func__, mmc->dev->name, timing.s.cmd_in_tap,
  1914. timing.s.cmd_out_tap, timing.s.data_in_tap,
  1915. timing.s.data_out_tap);
  1916. if (slot->host->tap_requires_noclk) {
  1917. /* Turn off the clock */
  1918. emm_debug.s.rdsync_rst = 0;
  1919. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  1920. udelay(1);
  1921. emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
  1922. emm_debug.s.emmc_clk_disable = 0;
  1923. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  1924. udelay(1);
  1925. }
  1926. for (count = 0; count < 2; count++) {
  1927. err = adj->test(mmc, opcode, NULL);
  1928. if (err) {
  1929. debug("%s(%s, %s): tap %d failed, count: %d, rsp_sts: 0x%llx, rsp_lo: 0x%llx\n",
  1930. __func__, mmc->dev->name,
  1931. adj->name, tap, count,
  1932. read_csr(mmc,
  1933. MIO_EMM_RSP_STS()),
  1934. read_csr(mmc,
  1935. MIO_EMM_RSP_LO()));
  1936. debug("%s(%s, %s): tap: %d, do: %d, di: %d, co: %d, ci: %d\n",
  1937. __func__, mmc->dev->name,
  1938. adj->name, tap,
  1939. timing.s.data_out_tap,
  1940. timing.s.data_in_tap,
  1941. timing.s.cmd_out_tap,
  1942. timing.s.cmd_in_tap);
  1943. break;
  1944. }
  1945. debug("%s(%s, %s): tap %d passed, count: %d, rsp_sts: 0x%llx, rsp_lo: 0x%llx\n",
  1946. __func__, mmc->dev->name, adj->name, tap,
  1947. count,
  1948. read_csr(mmc, MIO_EMM_RSP_STS()),
  1949. read_csr(mmc, MIO_EMM_RSP_LO()));
  1950. }
  1951. tap_status |= (u64)(!err) << tap;
  1952. how[tap] = "-+"[!err];
  1953. } else {
  1954. /*
  1955. * Putting the end+1 case in the loop simplifies
  1956. * logic, allowing 'prev_ok' to process a sweet
  1957. * spot in tuning which extends to the wall.
  1958. */
  1959. err = -EINVAL;
  1960. }
  1961. if (!err) {
  1962. /*
  1963. * If no CRC/etc errors in the response, but previous
  1964. * failed, note the start of a new run.
  1965. */
  1966. debug(" prev_ok: %d\n", prev_ok);
  1967. if (!prev_ok)
  1968. start_run = tap;
  1969. } else if (prev_ok) {
  1970. run = tap - 1 - start_run;
  1971. /* did we just exit a wider sweet spot? */
  1972. if (start_run >= 0 && run > best_run) {
  1973. best_start = start_run;
  1974. best_run = run;
  1975. }
  1976. }
  1977. }
  1978. how[tap - 1] = '\0';
  1979. if (best_start < 0) {
  1980. printf("%s(%s, %s): %lldMHz tuning %s failed\n", __func__,
  1981. mmc->dev->name, adj->name, slot->clock / 1000000,
  1982. adj->name);
  1983. return -EINVAL;
  1984. }
  1985. tap = best_start + best_run / 2;
  1986. debug(" tap %d is center, start: %d, run: %d\n", tap,
  1987. best_start, best_run);
  1988. if (is_hs200) {
  1989. slot->hs200_taps.u &= ~(0x3full << adj->mask_shift);
  1990. slot->hs200_taps.u |= (u64)tap << adj->mask_shift;
  1991. } else {
  1992. slot->taps.u &= ~(0x3full << adj->mask_shift);
  1993. slot->taps.u |= (u64)tap << adj->mask_shift;
  1994. }
  1995. if (best_start < 0) {
  1996. printf("%s(%s, %s): %lldMHz tuning %s failed\n", __func__,
  1997. mmc->dev->name, adj->name, slot->clock / 1000000,
  1998. adj->name);
  1999. return -EINVAL;
  2000. }
  2001. tap = best_start + best_run / 2;
  2002. if (is_hs200 && (tap + tap_adj >= 0) && (tap + tap_adj < 64) &&
  2003. tap_status & (1ULL << (tap + tap_adj))) {
  2004. debug("Adjusting tap from %d by %d to %d\n",
  2005. tap, tap_adj, tap + tap_adj);
  2006. tap += tap_adj;
  2007. }
  2008. how[tap] = '@';
  2009. debug("%s/%s %d/%d/%d %s\n", mmc->dev->name,
  2010. adj->name, best_start, tap, best_start + best_run, how);
  2011. if (is_hs200) {
  2012. slot->hs200_taps.u &= ~(0x3full << adj->mask_shift);
  2013. slot->hs200_taps.u |= (u64)tap << adj->mask_shift;
  2014. } else {
  2015. slot->taps.u &= ~(0x3full << adj->mask_shift);
  2016. slot->taps.u |= (u64)tap << adj->mask_shift;
  2017. }
  2018. #ifdef DEBUG
  2019. if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
  2020. debug("%s(%s, %s): After successful tuning\n",
  2021. __func__, mmc->dev->name, adj->name);
  2022. debug("%s(%s, %s): tap: %d, new do: %d, di: %d, co: %d, ci: %d\n",
  2023. __func__, mmc->dev->name, adj->name, tap,
  2024. slot->taps.s.data_out_tap,
  2025. slot->taps.s.data_in_tap,
  2026. slot->taps.s.cmd_out_tap,
  2027. slot->taps.s.cmd_in_tap);
  2028. debug("%s(%s, %s): tap: %d, new do HS200: %d, di: %d, co: %d, ci: %d\n",
  2029. __func__, mmc->dev->name, adj->name, tap,
  2030. slot->hs200_taps.s.data_out_tap,
  2031. slot->hs200_taps.s.data_in_tap,
  2032. slot->hs200_taps.s.cmd_out_tap,
  2033. slot->hs200_taps.s.cmd_in_tap);
  2034. }
  2035. #endif
  2036. octeontx_mmc_set_timing(mmc);
  2037. if (is_hs200 && env_get_yesno("emmc_export_hs200_taps")) {
  2038. char env_name[64];
  2039. env_set_ulong("emmc_timing_tap", slot->host->timing_taps);
  2040. switch (opcode) {
  2041. case MMC_CMD_SEND_TUNING_BLOCK:
  2042. snprintf(env_name, sizeof(env_name),
  2043. "emmc%d_hs200_data_in_tap_debug",
  2044. slot->bus_id);
  2045. env_set(env_name, how);
  2046. snprintf(env_name, sizeof(env_name),
  2047. "emmc%d_hs200_data_in_tap_val", slot->bus_id);
  2048. env_set_ulong(env_name, tap);
  2049. snprintf(env_name, sizeof(env_name),
  2050. "emmc%d_hs200_data_in_tap_start",
  2051. slot->bus_id);
  2052. env_set_ulong(env_name, best_start);
  2053. snprintf(env_name, sizeof(env_name),
  2054. "emmc%d_hs200_data_in_tap_end",
  2055. slot->bus_id);
  2056. env_set_ulong(env_name, best_start + best_run);
  2057. break;
  2058. case MMC_CMD_SEND_STATUS:
  2059. snprintf(env_name, sizeof(env_name),
  2060. "emmc%d_hs200_cmd_in_tap_debug",
  2061. slot->bus_id);
  2062. env_set(env_name, how);
  2063. snprintf(env_name, sizeof(env_name),
  2064. "emmc%d_hs200_cmd_in_tap_val", slot->bus_id);
  2065. env_set_ulong(env_name, tap);
  2066. snprintf(env_name, sizeof(env_name),
  2067. "emmc%d_hs200_cmd_in_tap_start",
  2068. slot->bus_id);
  2069. env_set_ulong(env_name, best_start);
  2070. snprintf(env_name, sizeof(env_name),
  2071. "emmc%d_hs200_cmd_in_tap_end",
  2072. slot->bus_id);
  2073. env_set_ulong(env_name, best_start + best_run);
  2074. break;
  2075. default:
  2076. snprintf(env_name, sizeof(env_name),
  2077. "emmc%d_hs200_data_out_tap", slot->bus_id);
  2078. env_set_ulong(env_name, slot->data_out_hs200_delay);
  2079. snprintf(env_name, sizeof(env_name),
  2080. "emmc%d_hs200_cmd_out_tap", slot->bus_id);
  2081. env_set_ulong(env_name, slot->cmd_out_hs200_delay);
  2082. break;
  2083. }
  2084. }
  2085. return 0;
  2086. }
  2087. static int octeontx_mmc_execute_tuning(struct udevice *dev, u32 opcode)
  2088. {
  2089. struct mmc *mmc = dev_to_mmc(dev);
  2090. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  2091. union mio_emm_timing emm_timing;
  2092. int err;
  2093. struct adj *a;
  2094. bool is_hs200;
  2095. char env_name[64];
  2096. pr_info("%s re-tuning, opcode 0x%x\n", dev->name, opcode);
  2097. if (slot->is_asim || slot->is_emul)
  2098. return 0;
  2099. is_hs200 = (mmc->selected_mode == MMC_HS_200);
  2100. if (is_hs200) {
  2101. slot->hs200_tuned = false;
  2102. slot->hs400_tuned = false;
  2103. } else {
  2104. slot->tuned = false;
  2105. }
  2106. octeontx_mmc_set_output_bus_timing(mmc);
  2107. octeontx_mmc_set_input_bus_timing(mmc);
  2108. emm_timing.u = read_csr(mmc, MIO_EMM_TIMING());
  2109. if (mmc->selected_mode == MMC_HS_200) {
  2110. slot->hs200_taps.s.cmd_out_tap = emm_timing.s.cmd_out_tap;
  2111. slot->hs200_taps.s.data_out_tap = emm_timing.s.data_out_tap;
  2112. } else {
  2113. slot->taps.s.cmd_out_tap = emm_timing.s.cmd_out_tap;
  2114. slot->taps.s.data_out_tap = emm_timing.s.data_out_tap;
  2115. }
  2116. octeontx_mmc_set_input_bus_timing(mmc);
  2117. octeontx_mmc_set_output_bus_timing(mmc);
  2118. for (a = adj; a->name; a++) {
  2119. ulong in_tap;
  2120. if (!strcmp(a->name, "CMD_IN")) {
  2121. snprintf(env_name, sizeof(env_name),
  2122. "emmc%d_cmd_in_tap", slot->bus_id);
  2123. in_tap = env_get_ulong(env_name, 10, (ulong)-1);
  2124. if (in_tap != (ulong)-1) {
  2125. if (mmc->selected_mode == MMC_HS_200 ||
  2126. a->hs200_only) {
  2127. slot->hs200_taps.s.cmd_in_tap = in_tap;
  2128. slot->hs400_taps.s.cmd_in_tap = in_tap;
  2129. } else {
  2130. slot->taps.s.cmd_in_tap = in_tap;
  2131. }
  2132. continue;
  2133. }
  2134. } else if (a->hs200_only &&
  2135. !strcmp(a->name, "DATA_IN(HS200)")) {
  2136. snprintf(env_name, sizeof(env_name),
  2137. "emmc%d_data_in_tap_hs200", slot->bus_id);
  2138. in_tap = env_get_ulong(env_name, 10, (ulong)-1);
  2139. if (in_tap != (ulong)-1) {
  2140. debug("%s(%s): Overriding HS200 data in tap to %d\n",
  2141. __func__, dev->name, (int)in_tap);
  2142. slot->hs200_taps.s.data_in_tap = in_tap;
  2143. continue;
  2144. }
  2145. } else if (!a->hs200_only && !strcmp(a->name, "DATA_IN")) {
  2146. snprintf(env_name, sizeof(env_name),
  2147. "emmc%d_data_in_tap", slot->bus_id);
  2148. in_tap = env_get_ulong(env_name, 10, (ulong)-1);
  2149. if (in_tap != (ulong)-1) {
  2150. debug("%s(%s): Overriding non-HS200 data in tap to %d\n",
  2151. __func__, dev->name, (int)in_tap);
  2152. slot->taps.s.data_in_tap = in_tap;
  2153. continue;
  2154. }
  2155. }
  2156. debug("%s(%s): Testing: %s, mode: %s, opcode: %u\n", __func__,
  2157. dev->name, a->name, mmc_mode_name(mmc->selected_mode),
  2158. opcode);
  2159. /* Skip DDR only test when not in DDR mode */
  2160. if (a->ddr_only && !mmc->ddr_mode) {
  2161. debug("%s(%s): Skipping %s due to non-DDR mode\n",
  2162. __func__, dev->name, a->name);
  2163. continue;
  2164. }
  2165. /* Skip hs200 tests in non-hs200 mode and
  2166. * non-hs200 tests in hs200 mode
  2167. */
  2168. if (is_hs200) {
  2169. if (a->not_hs200_only) {
  2170. debug("%s(%s): Skipping %s\n", __func__,
  2171. dev->name, a->name);
  2172. continue;
  2173. }
  2174. } else {
  2175. if (a->hs200_only) {
  2176. debug("%s(%s): Skipping %s\n", __func__,
  2177. dev->name, a->name);
  2178. continue;
  2179. }
  2180. }
  2181. err = octeontx_mmc_adjust_tuning(mmc, a, a->opcode ?
  2182. a->opcode : opcode);
  2183. if (err) {
  2184. pr_err("%s(%s, %u): tuning %s failed\n", __func__,
  2185. dev->name, opcode, a->name);
  2186. return err;
  2187. }
  2188. }
  2189. octeontx_mmc_set_timing(mmc);
  2190. if (is_hs200)
  2191. slot->hs200_tuned = true;
  2192. else
  2193. slot->tuned = true;
  2194. if (slot->hs400_tuning_block != -1) {
  2195. struct mmc_cmd cmd;
  2196. struct mmc_data data;
  2197. u8 buffer[mmc->read_bl_len];
  2198. cmd.cmdidx = MMC_CMD_READ_SINGLE_BLOCK;
  2199. cmd.cmdarg = slot->hs400_tuning_block;
  2200. cmd.resp_type = MMC_RSP_R1;
  2201. data.dest = (void *)buffer;
  2202. data.blocks = 1;
  2203. data.blocksize = mmc->read_bl_len;
  2204. data.flags = MMC_DATA_READ;
  2205. err = octeontx_mmc_read_blocks(mmc, &cmd, &data, true) != 1;
  2206. if (err) {
  2207. printf("%s: Cannot read HS400 tuning block %u\n",
  2208. dev->name, slot->hs400_tuning_block);
  2209. return err;
  2210. }
  2211. if (memcmp(buffer, octeontx_hs400_tuning_block,
  2212. sizeof(buffer))) {
  2213. debug("%s(%s): Writing new HS400 tuning block to block %d\n",
  2214. __func__, dev->name, slot->hs400_tuning_block);
  2215. cmd.cmdidx = MMC_CMD_WRITE_SINGLE_BLOCK;
  2216. data.src = (void *)octeontx_hs400_tuning_block;
  2217. data.flags = MMC_DATA_WRITE;
  2218. err = !octeontx_mmc_write_blocks(mmc, &cmd, &data);
  2219. if (err) {
  2220. printf("%s: Cannot write HS400 tuning block %u\n",
  2221. dev->name, slot->hs400_tuning_block);
  2222. return -EINVAL;
  2223. }
  2224. }
  2225. }
  2226. return 0;
  2227. }
  2228. #else /* MMC_SUPPORTS_TUNING */
  2229. static void octeontx_mmc_set_emm_timing(struct mmc *mmc,
  2230. union mio_emm_timing emm_timing)
  2231. {
  2232. }
  2233. #endif /* MMC_SUPPORTS_TUNING */
  2234. /**
  2235. * Calculate the clock period with rounding up
  2236. *
  2237. * @param mmc mmc device
  2238. * @return clock period in system clocks for clk_lo + clk_hi
  2239. */
  2240. static u32 octeontx_mmc_calc_clk_period(struct mmc *mmc)
  2241. {
  2242. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  2243. struct octeontx_mmc_host *host = slot->host;
  2244. return DIV_ROUND_UP(host->sys_freq, mmc->clock);
  2245. }
  2246. static int octeontx_mmc_set_ios(struct udevice *dev)
  2247. {
  2248. struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev);
  2249. struct mmc *mmc = &slot->mmc;
  2250. struct octeontx_mmc_host *host = slot->host;
  2251. union mio_emm_switch emm_switch;
  2252. union mio_emm_modex mode;
  2253. uint clock;
  2254. int bus_width = 0;
  2255. int clk_period = 0;
  2256. int power_class = 10;
  2257. int err = 0;
  2258. bool is_hs200 = false;
  2259. bool is_hs400 = false;
  2260. debug("%s(%s): Entry\n", __func__, dev->name);
  2261. debug(" clock: %u, bus width: %u, mode: %u\n", mmc->clock,
  2262. mmc->bus_width, mmc->selected_mode);
  2263. debug(" host caps: 0x%x, card caps: 0x%x\n", mmc->host_caps,
  2264. mmc->card_caps);
  2265. octeontx_mmc_switch_to(mmc);
  2266. clock = mmc->clock;
  2267. if (!clock)
  2268. clock = mmc->cfg->f_min;
  2269. switch (mmc->bus_width) {
  2270. case 8:
  2271. bus_width = 2;
  2272. break;
  2273. case 4:
  2274. bus_width = 1;
  2275. break;
  2276. case 1:
  2277. bus_width = 0;
  2278. break;
  2279. default:
  2280. pr_warn("%s(%s): Invalid bus width %d, defaulting to 1\n",
  2281. __func__, dev->name, mmc->bus_width);
  2282. bus_width = 0;
  2283. }
  2284. /* DDR is available for 4/8 bit bus width */
  2285. if (mmc->ddr_mode && bus_width)
  2286. bus_width |= 4;
  2287. debug("%s: sys_freq: %llu\n", __func__, host->sys_freq);
  2288. clk_period = octeontx_mmc_calc_clk_period(mmc);
  2289. emm_switch.u = 0;
  2290. emm_switch.s.bus_width = bus_width;
  2291. emm_switch.s.power_class = power_class;
  2292. emm_switch.s.clk_hi = clk_period / 2;
  2293. emm_switch.s.clk_lo = clk_period / 2;
  2294. debug("%s: last mode: %d, mode: %d, last clock: %u, clock: %u, ddr: %d\n",
  2295. __func__, slot->last_mode, mmc->selected_mode,
  2296. slot->last_clock, mmc->clock, mmc->ddr_mode);
  2297. switch (mmc->selected_mode) {
  2298. case MMC_LEGACY:
  2299. break;
  2300. case MMC_HS:
  2301. case SD_HS:
  2302. case MMC_HS_52:
  2303. emm_switch.s.hs_timing = 1;
  2304. break;
  2305. case MMC_HS_200:
  2306. is_hs200 = true;
  2307. fallthrough;
  2308. case UHS_SDR12:
  2309. case UHS_SDR25:
  2310. case UHS_SDR50:
  2311. case UHS_SDR104:
  2312. emm_switch.s.hs200_timing = 1;
  2313. break;
  2314. case MMC_HS_400:
  2315. is_hs400 = true;
  2316. fallthrough;
  2317. case UHS_DDR50:
  2318. case MMC_DDR_52:
  2319. emm_switch.s.hs400_timing = 1;
  2320. break;
  2321. default:
  2322. pr_err("%s(%s): Unsupported mode 0x%x\n", __func__, dev->name,
  2323. mmc->selected_mode);
  2324. return -1;
  2325. }
  2326. emm_switch.s.bus_id = slot->bus_id;
  2327. if (!is_hs200 && !is_hs400 &&
  2328. (mmc->selected_mode != slot->last_mode ||
  2329. mmc->clock != slot->last_clock) &&
  2330. !mmc->ddr_mode) {
  2331. slot->tuned = false;
  2332. slot->last_mode = mmc->selected_mode;
  2333. slot->last_clock = mmc->clock;
  2334. }
  2335. if (CONFIG_IS_ENABLED(MMC_VERBOSE)) {
  2336. debug("%s(%s): Setting bus mode to %s\n", __func__, dev->name,
  2337. mmc_mode_name(mmc->selected_mode));
  2338. } else {
  2339. debug("%s(%s): Setting bus mode to 0x%x\n", __func__, dev->name,
  2340. mmc->selected_mode);
  2341. }
  2342. debug(" Trying switch 0x%llx w%d hs:%d hs200:%d hs400:%d\n",
  2343. emm_switch.u, emm_switch.s.bus_width, emm_switch.s.hs_timing,
  2344. emm_switch.s.hs200_timing, emm_switch.s.hs400_timing);
  2345. set_wdog(mmc, 1000);
  2346. do_switch(mmc, emm_switch);
  2347. mdelay(100);
  2348. mode.u = read_csr(mmc, MIO_EMM_MODEX(slot->bus_id));
  2349. debug("%s(%s): mode: 0x%llx w:%d, hs:%d, hs200:%d, hs400:%d\n",
  2350. __func__, dev->name, mode.u, mode.s.bus_width,
  2351. mode.s.hs_timing, mode.s.hs200_timing, mode.s.hs400_timing);
  2352. err = octeontx_mmc_configure_delay(mmc);
  2353. #ifdef MMC_SUPPORTS_TUNING
  2354. if (!err && mmc->selected_mode == MMC_HS_400 && !slot->hs400_tuned) {
  2355. debug("%s: Tuning HS400 mode\n", __func__);
  2356. err = octeontx_tune_hs400(mmc);
  2357. }
  2358. #endif
  2359. return err;
  2360. }
  2361. /**
  2362. * Gets the status of the card detect pin
  2363. */
  2364. static int octeontx_mmc_get_cd(struct udevice *dev)
  2365. {
  2366. struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev);
  2367. int val = 1;
  2368. if (dm_gpio_is_valid(&slot->cd_gpio)) {
  2369. val = dm_gpio_get_value(&slot->cd_gpio);
  2370. val ^= slot->cd_inverted;
  2371. }
  2372. debug("%s(%s): cd: %d\n", __func__, dev->name, val);
  2373. return val;
  2374. }
  2375. /**
  2376. * Gets the status of the write protect pin
  2377. */
  2378. static int octeontx_mmc_get_wp(struct udevice *dev)
  2379. {
  2380. struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev);
  2381. int val = 0;
  2382. if (dm_gpio_is_valid(&slot->wp_gpio)) {
  2383. val = dm_gpio_get_value(&slot->wp_gpio);
  2384. val ^= slot->wp_inverted;
  2385. }
  2386. debug("%s(%s): wp: %d\n", __func__, dev->name, val);
  2387. return val;
  2388. }
  2389. static void octeontx_mmc_set_timing(struct mmc *mmc)
  2390. {
  2391. union mio_emm_timing timing;
  2392. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  2393. switch (mmc->selected_mode) {
  2394. case MMC_HS_200:
  2395. timing = slot->hs200_taps;
  2396. break;
  2397. case MMC_HS_400:
  2398. timing = slot->hs400_tuned ?
  2399. slot->hs400_taps : slot->hs200_taps;
  2400. break;
  2401. default:
  2402. timing = slot->taps;
  2403. break;
  2404. }
  2405. debug("%s(%s):\n cmd_in_tap: %u\n cmd_out_tap: %u\n data_in_tap: %u\n data_out_tap: %u\n",
  2406. __func__, mmc->dev->name, timing.s.cmd_in_tap,
  2407. timing.s.cmd_out_tap, timing.s.data_in_tap,
  2408. timing.s.data_out_tap);
  2409. octeontx_mmc_set_emm_timing(mmc, timing);
  2410. }
  2411. static int octeontx_mmc_configure_delay(struct mmc *mmc)
  2412. {
  2413. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  2414. struct octeontx_mmc_host *host __maybe_unused = slot->host;
  2415. bool __maybe_unused is_hs200;
  2416. bool __maybe_unused is_hs400;
  2417. debug("%s(%s)\n", __func__, mmc->dev->name);
  2418. if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
  2419. union mio_emm_sample emm_sample;
  2420. emm_sample.u = 0;
  2421. emm_sample.s.cmd_cnt = slot->cmd_cnt;
  2422. emm_sample.s.dat_cnt = slot->dat_cnt;
  2423. write_csr(mmc, MIO_EMM_SAMPLE(), emm_sample.u);
  2424. } else {
  2425. is_hs200 = (mmc->selected_mode == MMC_HS_200);
  2426. is_hs400 = (mmc->selected_mode == MMC_HS_400);
  2427. if ((is_hs200 && slot->hs200_tuned) ||
  2428. (is_hs400 && slot->hs400_tuned) ||
  2429. (!is_hs200 && !is_hs400 && slot->tuned)) {
  2430. octeontx_mmc_set_output_bus_timing(mmc);
  2431. } else {
  2432. int half = MAX_NO_OF_TAPS / 2;
  2433. int dout, cout;
  2434. switch (mmc->selected_mode) {
  2435. case MMC_LEGACY:
  2436. if (IS_SD(mmc)) {
  2437. cout = MMC_SD_LEGACY_DEFAULT_CMD_OUT_TAP;
  2438. dout = MMC_SD_LEGACY_DEFAULT_DATA_OUT_TAP;
  2439. } else {
  2440. cout = MMC_LEGACY_DEFAULT_CMD_OUT_TAP;
  2441. dout = MMC_LEGACY_DEFAULT_DATA_OUT_TAP;
  2442. }
  2443. break;
  2444. case MMC_HS:
  2445. cout = MMC_HS_CMD_OUT_TAP;
  2446. dout = MMC_HS_DATA_OUT_TAP;
  2447. break;
  2448. case SD_HS:
  2449. case UHS_SDR12:
  2450. case UHS_SDR25:
  2451. case UHS_SDR50:
  2452. cout = MMC_SD_HS_CMD_OUT_TAP;
  2453. dout = MMC_SD_HS_DATA_OUT_TAP;
  2454. break;
  2455. case UHS_SDR104:
  2456. case UHS_DDR50:
  2457. case MMC_HS_52:
  2458. case MMC_DDR_52:
  2459. cout = MMC_DEFAULT_CMD_OUT_TAP;
  2460. dout = MMC_DEFAULT_DATA_OUT_TAP;
  2461. break;
  2462. case MMC_HS_200:
  2463. cout = -1;
  2464. dout = -1;
  2465. if (host->timing_calibrated) {
  2466. cout = octeontx2_mmc_calc_delay(
  2467. mmc, slot->cmd_out_hs200_delay);
  2468. dout = octeontx2_mmc_calc_delay(
  2469. mmc,
  2470. slot->data_out_hs200_delay);
  2471. debug("%s(%s): Calibrated HS200/HS400 cmd out delay: %dps tap: %d, data out delay: %d, tap: %d\n",
  2472. __func__, mmc->dev->name,
  2473. slot->cmd_out_hs200_delay, cout,
  2474. slot->data_out_hs200_delay, dout);
  2475. } else {
  2476. cout = MMC_DEFAULT_HS200_CMD_OUT_TAP;
  2477. dout = MMC_DEFAULT_HS200_DATA_OUT_TAP;
  2478. }
  2479. is_hs200 = true;
  2480. break;
  2481. case MMC_HS_400:
  2482. cout = -1;
  2483. dout = -1;
  2484. if (host->timing_calibrated) {
  2485. if (slot->cmd_out_hs400_delay)
  2486. cout = octeontx2_mmc_calc_delay(
  2487. mmc,
  2488. slot->cmd_out_hs400_delay);
  2489. if (slot->data_out_hs400_delay)
  2490. dout = octeontx2_mmc_calc_delay(
  2491. mmc,
  2492. slot->data_out_hs400_delay);
  2493. debug("%s(%s): Calibrated HS200/HS400 cmd out delay: %dps tap: %d, data out delay: %d, tap: %d\n",
  2494. __func__, mmc->dev->name,
  2495. slot->cmd_out_hs400_delay, cout,
  2496. slot->data_out_hs400_delay, dout);
  2497. } else {
  2498. cout = MMC_DEFAULT_HS400_CMD_OUT_TAP;
  2499. dout = MMC_DEFAULT_HS400_DATA_OUT_TAP;
  2500. }
  2501. is_hs400 = true;
  2502. break;
  2503. default:
  2504. pr_err("%s(%s): Invalid mode %d\n", __func__,
  2505. mmc->dev->name, mmc->selected_mode);
  2506. return -1;
  2507. }
  2508. debug("%s(%s): Not tuned, hs200: %d, hs200 tuned: %d, hs400: %d, hs400 tuned: %d, tuned: %d\n",
  2509. __func__, mmc->dev->name, is_hs200,
  2510. slot->hs200_tuned,
  2511. is_hs400, slot->hs400_tuned, slot->tuned);
  2512. /* Set some defaults */
  2513. if (is_hs200) {
  2514. slot->hs200_taps.u = 0;
  2515. slot->hs200_taps.s.cmd_out_tap = cout;
  2516. slot->hs200_taps.s.data_out_tap = dout;
  2517. slot->hs200_taps.s.cmd_in_tap = half;
  2518. slot->hs200_taps.s.data_in_tap = half;
  2519. } else if (is_hs400) {
  2520. slot->hs400_taps.u = 0;
  2521. slot->hs400_taps.s.cmd_out_tap = cout;
  2522. slot->hs400_taps.s.data_out_tap = dout;
  2523. slot->hs400_taps.s.cmd_in_tap = half;
  2524. slot->hs400_taps.s.data_in_tap = half;
  2525. } else {
  2526. slot->taps.u = 0;
  2527. slot->taps.s.cmd_out_tap = cout;
  2528. slot->taps.s.data_out_tap = dout;
  2529. slot->taps.s.cmd_in_tap = half;
  2530. slot->taps.s.data_in_tap = half;
  2531. }
  2532. }
  2533. if (is_hs200)
  2534. debug("%s(%s): hs200 taps: ci: %u, co: %u, di: %u, do: %u\n",
  2535. __func__, mmc->dev->name,
  2536. slot->hs200_taps.s.cmd_in_tap,
  2537. slot->hs200_taps.s.cmd_out_tap,
  2538. slot->hs200_taps.s.data_in_tap,
  2539. slot->hs200_taps.s.data_out_tap);
  2540. else if (is_hs400)
  2541. debug("%s(%s): hs400 taps: ci: %u, co: %u, di: %u, do: %u\n",
  2542. __func__, mmc->dev->name,
  2543. slot->hs400_taps.s.cmd_in_tap,
  2544. slot->hs400_taps.s.cmd_out_tap,
  2545. slot->hs400_taps.s.data_in_tap,
  2546. slot->hs400_taps.s.data_out_tap);
  2547. else
  2548. debug("%s(%s): taps: ci: %u, co: %u, di: %u, do: %u\n",
  2549. __func__, mmc->dev->name, slot->taps.s.cmd_in_tap,
  2550. slot->taps.s.cmd_out_tap,
  2551. slot->taps.s.data_in_tap,
  2552. slot->taps.s.data_out_tap);
  2553. octeontx_mmc_set_timing(mmc);
  2554. debug("%s: Done\n", __func__);
  2555. }
  2556. return 0;
  2557. }
  2558. /**
  2559. * Sets the MMC watchdog timer in microseconds
  2560. *
  2561. * @param mmc mmc device
  2562. * @param us timeout in microseconds, 0 for maximum timeout
  2563. */
  2564. static void set_wdog(struct mmc *mmc, u64 us)
  2565. {
  2566. union mio_emm_wdog wdog;
  2567. u64 val;
  2568. val = (us * mmc->clock) / 1000000;
  2569. if (val >= (1 << 26) || !us) {
  2570. if (us)
  2571. pr_debug("%s: warning: timeout %llu exceeds max value %llu, truncating\n",
  2572. __func__, us,
  2573. (u64)(((1ULL << 26) - 1) * 1000000ULL) /
  2574. mmc->clock);
  2575. val = (1 << 26) - 1;
  2576. }
  2577. wdog.u = 0;
  2578. wdog.s.clk_cnt = val;
  2579. write_csr(mmc, MIO_EMM_WDOG(), wdog.u);
  2580. }
  2581. /**
  2582. * Set the IO drive strength and slew
  2583. *
  2584. * @param mmc mmc device
  2585. */
  2586. static void octeontx_mmc_io_drive_setup(struct mmc *mmc)
  2587. {
  2588. if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
  2589. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  2590. union mio_emm_io_ctl io_ctl;
  2591. if (slot->drive < 0 || slot->slew < 0)
  2592. return;
  2593. io_ctl.u = 0;
  2594. io_ctl.s.drive = slot->drive;
  2595. io_ctl.s.slew = slot->slew;
  2596. write_csr(mmc, MIO_EMM_IO_CTL(), io_ctl.u);
  2597. }
  2598. }
  2599. /**
  2600. * Print switch errors
  2601. *
  2602. * @param mmc mmc device
  2603. */
  2604. static void check_switch_errors(struct mmc *mmc)
  2605. {
  2606. union mio_emm_switch emm_switch;
  2607. emm_switch.u = read_csr(mmc, MIO_EMM_SWITCH());
  2608. if (emm_switch.s.switch_err0)
  2609. pr_err("%s: Switch power class error\n", mmc->cfg->name);
  2610. if (emm_switch.s.switch_err1)
  2611. pr_err("%s: Switch HS timing error\n", mmc->cfg->name);
  2612. if (emm_switch.s.switch_err2)
  2613. pr_err("%s: Switch bus width error\n", mmc->cfg->name);
  2614. }
  2615. static void do_switch(struct mmc *mmc, union mio_emm_switch emm_switch)
  2616. {
  2617. union mio_emm_rsp_sts rsp_sts;
  2618. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  2619. int bus_id = emm_switch.s.bus_id;
  2620. ulong start;
  2621. if (emm_switch.s.bus_id != 0) {
  2622. emm_switch.s.bus_id = 0;
  2623. write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u);
  2624. udelay(100);
  2625. emm_switch.s.bus_id = bus_id;
  2626. }
  2627. debug("%s(%s, 0x%llx)\n", __func__, mmc->dev->name, emm_switch.u);
  2628. write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u);
  2629. start = get_timer(0);
  2630. do {
  2631. rsp_sts.u = read_csr(mmc, MIO_EMM_RSP_STS());
  2632. if (!rsp_sts.s.switch_val)
  2633. break;
  2634. udelay(100);
  2635. } while (get_timer(start) < 10);
  2636. if (rsp_sts.s.switch_val) {
  2637. pr_warn("%s(%s): Warning: writing 0x%llx to emm_switch timed out, status: 0x%llx\n",
  2638. __func__, mmc->dev->name, emm_switch.u, rsp_sts.u);
  2639. }
  2640. slot->cached_switch = emm_switch;
  2641. check_switch_errors(mmc);
  2642. slot->cached_switch.u = emm_switch.u;
  2643. debug("%s: emm_switch: 0x%llx, rsp_lo: 0x%llx\n",
  2644. __func__, read_csr(mmc, MIO_EMM_SWITCH()),
  2645. read_csr(mmc, MIO_EMM_RSP_LO()));
  2646. }
  2647. /**
  2648. * Given a delay in ps, return the tap delay count
  2649. *
  2650. * @param mmc mmc data structure
  2651. * @param delay delay in picoseconds
  2652. *
  2653. * @return Number of tap cycles or error if -1
  2654. */
  2655. static int octeontx2_mmc_calc_delay(struct mmc *mmc, int delay)
  2656. {
  2657. struct octeontx_mmc_host *host = mmc_to_host(mmc);
  2658. if (host->is_asim || host->is_emul)
  2659. return 63;
  2660. if (!host->timing_taps) {
  2661. pr_err("%s(%s): Error: host timing not calibrated\n",
  2662. __func__, mmc->dev->name);
  2663. return -1;
  2664. }
  2665. debug("%s(%s, %d) timing taps: %llu\n", __func__, mmc->dev->name,
  2666. delay, host->timing_taps);
  2667. return min_t(int, DIV_ROUND_UP(delay, host->timing_taps), 63);
  2668. }
  2669. /**
  2670. * Calibrates the delay based on the internal clock
  2671. *
  2672. * @param mmc Pointer to mmc data structure
  2673. *
  2674. * @return 0 for success or -ETIMEDOUT on error
  2675. *
  2676. * NOTE: On error a default value will be calculated.
  2677. */
  2678. static int octeontx_mmc_calibrate_delay(struct mmc *mmc)
  2679. {
  2680. union mio_emm_calb emm_calb;
  2681. union mio_emm_tap emm_tap;
  2682. union mio_emm_cfg emm_cfg;
  2683. union mio_emm_io_ctl emm_io_ctl;
  2684. union mio_emm_switch emm_switch;
  2685. union mio_emm_wdog emm_wdog;
  2686. union mio_emm_sts_mask emm_sts_mask;
  2687. union mio_emm_debug emm_debug;
  2688. union mio_emm_timing emm_timing;
  2689. struct octeontx_mmc_host *host = mmc_to_host(mmc);
  2690. ulong start;
  2691. u8 bus_id, bus_ena;
  2692. debug("%s: Calibrating delay\n", __func__);
  2693. if (host->is_asim || host->is_emul) {
  2694. debug(" No calibration for ASIM\n");
  2695. return 0;
  2696. }
  2697. emm_tap.u = 0;
  2698. if (host->calibrate_glitch) {
  2699. emm_tap.s.delay = MMC_DEFAULT_TAP_DELAY;
  2700. } else {
  2701. /* Save registers */
  2702. emm_cfg.u = read_csr(mmc, MIO_EMM_CFG());
  2703. emm_io_ctl.u = read_csr(mmc, MIO_EMM_IO_CTL());
  2704. emm_switch.u = read_csr(mmc, MIO_EMM_SWITCH());
  2705. emm_wdog.u = read_csr(mmc, MIO_EMM_WDOG());
  2706. emm_sts_mask.u = read_csr(mmc, MIO_EMM_STS_MASK());
  2707. emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
  2708. emm_timing.u = read_csr(mmc, MIO_EMM_TIMING());
  2709. bus_ena = emm_cfg.s.bus_ena;
  2710. bus_id = emm_switch.s.bus_id;
  2711. emm_cfg.s.bus_ena = 0;
  2712. write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
  2713. udelay(1);
  2714. emm_cfg.s.bus_ena = 1ULL << 3;
  2715. write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
  2716. mdelay(1);
  2717. emm_calb.u = 0;
  2718. write_csr(mmc, MIO_EMM_CALB(), emm_calb.u);
  2719. emm_calb.s.start = 1;
  2720. write_csr(mmc, MIO_EMM_CALB(), emm_calb.u);
  2721. start = get_timer(0);
  2722. /* This should only take 3 microseconds */
  2723. do {
  2724. udelay(5);
  2725. emm_tap.u = read_csr(mmc, MIO_EMM_TAP());
  2726. } while (!emm_tap.s.delay && get_timer(start) < 10);
  2727. emm_calb.s.start = 0;
  2728. write_csr(mmc, MIO_EMM_CALB(), emm_calb.u);
  2729. emm_cfg.s.bus_ena = 0;
  2730. write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
  2731. udelay(1);
  2732. /* Restore registers */
  2733. emm_cfg.s.bus_ena = bus_ena;
  2734. write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
  2735. if (host->tap_requires_noclk) {
  2736. /* Turn off the clock */
  2737. emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
  2738. emm_debug.s.emmc_clk_disable = 1;
  2739. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  2740. udelay(1);
  2741. emm_debug.s.rdsync_rst = 1;
  2742. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  2743. udelay(1);
  2744. }
  2745. write_csr(mmc, MIO_EMM_TIMING(), emm_timing.u);
  2746. if (host->tap_requires_noclk) {
  2747. /* Turn the clock back on */
  2748. udelay(1);
  2749. emm_debug.s.rdsync_rst = 0;
  2750. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  2751. udelay(1);
  2752. emm_debug.s.emmc_clk_disable = 0;
  2753. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  2754. }
  2755. udelay(1);
  2756. write_csr(mmc, MIO_EMM_IO_CTL(), emm_io_ctl.u);
  2757. bus_id = emm_switch.s.bus_id;
  2758. emm_switch.s.bus_id = 0;
  2759. write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u);
  2760. emm_switch.s.bus_id = bus_id;
  2761. write_csr(mmc, MIO_EMM_SWITCH(), emm_switch.u);
  2762. write_csr(mmc, MIO_EMM_WDOG(), emm_wdog.u);
  2763. write_csr(mmc, MIO_EMM_STS_MASK(), emm_sts_mask.u);
  2764. write_csr(mmc, MIO_EMM_RCA(), mmc->rca);
  2765. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  2766. if (!emm_tap.s.delay) {
  2767. pr_err("%s: Error: delay calibration failed, timed out.\n",
  2768. __func__);
  2769. /* Set to default value if timed out */
  2770. emm_tap.s.delay = MMC_DEFAULT_TAP_DELAY;
  2771. return -ETIMEDOUT;
  2772. }
  2773. }
  2774. /* Round up */
  2775. host->timing_taps = (10 * 1000 * emm_tap.s.delay) / TOTAL_NO_OF_TAPS;
  2776. debug("%s(%s): timing taps: %llu, delay: %u\n",
  2777. __func__, mmc->dev->name, host->timing_taps, emm_tap.s.delay);
  2778. host->timing_calibrated = true;
  2779. return 0;
  2780. }
  2781. static int octeontx_mmc_set_input_bus_timing(struct mmc *mmc)
  2782. {
  2783. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  2784. if (IS_ENABLED(CONFIG_ARCH_OCTEONTX)) {
  2785. union mio_emm_sample sample;
  2786. sample.u = 0;
  2787. sample.s.cmd_cnt = slot->cmd_clk_skew;
  2788. sample.s.dat_cnt = slot->dat_clk_skew;
  2789. write_csr(mmc, MIO_EMM_SAMPLE(), sample.u);
  2790. } else {
  2791. union mio_emm_timing timing;
  2792. timing.u = read_csr(mmc, MIO_EMM_TIMING());
  2793. if (mmc->selected_mode == MMC_HS_200) {
  2794. if (slot->hs200_tuned) {
  2795. timing.s.cmd_in_tap =
  2796. slot->hs200_taps.s.cmd_in_tap;
  2797. timing.s.data_in_tap =
  2798. slot->hs200_taps.s.data_in_tap;
  2799. } else {
  2800. pr_warn("%s(%s): Warning: hs200 timing not tuned\n",
  2801. __func__, mmc->dev->name);
  2802. timing.s.cmd_in_tap =
  2803. MMC_DEFAULT_HS200_CMD_IN_TAP;
  2804. timing.s.data_in_tap =
  2805. MMC_DEFAULT_HS200_DATA_IN_TAP;
  2806. }
  2807. } else if (mmc->selected_mode == MMC_HS_400) {
  2808. if (slot->hs400_tuned) {
  2809. timing.s.cmd_in_tap =
  2810. slot->hs400_taps.s.cmd_in_tap;
  2811. timing.s.data_in_tap =
  2812. slot->hs400_taps.s.data_in_tap;
  2813. } else if (slot->hs200_tuned) {
  2814. timing.s.cmd_in_tap =
  2815. slot->hs200_taps.s.cmd_in_tap;
  2816. timing.s.data_in_tap =
  2817. slot->hs200_taps.s.data_in_tap;
  2818. } else {
  2819. pr_warn("%s(%s): Warning: hs400 timing not tuned\n",
  2820. __func__, mmc->dev->name);
  2821. timing.s.cmd_in_tap =
  2822. MMC_DEFAULT_HS200_CMD_IN_TAP;
  2823. timing.s.data_in_tap =
  2824. MMC_DEFAULT_HS200_DATA_IN_TAP;
  2825. }
  2826. } else if (slot->tuned) {
  2827. timing.s.cmd_in_tap = slot->taps.s.cmd_in_tap;
  2828. timing.s.data_in_tap = slot->taps.s.data_in_tap;
  2829. } else {
  2830. timing.s.cmd_in_tap = MMC_DEFAULT_CMD_IN_TAP;
  2831. timing.s.data_in_tap = MMC_DEFAULT_DATA_IN_TAP;
  2832. }
  2833. octeontx_mmc_set_emm_timing(mmc, timing);
  2834. }
  2835. return 0;
  2836. }
  2837. /**
  2838. * Sets the default bus timing for the current mode.
  2839. *
  2840. * @param mmc mmc data structure
  2841. *
  2842. * @return 0 for success, error otherwise
  2843. */
  2844. static int octeontx_mmc_set_output_bus_timing(struct mmc *mmc)
  2845. {
  2846. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  2847. union mio_emm_timing timing;
  2848. int cout_bdelay, dout_bdelay;
  2849. unsigned int cout_delay, dout_delay;
  2850. char env_name[32];
  2851. if (IS_ENABLED(CONFIG_ARCH_OCTEONTX))
  2852. return 0;
  2853. debug("%s(%s)\n", __func__, mmc->dev->name);
  2854. if (slot->is_asim || slot->is_emul)
  2855. return 0;
  2856. octeontx_mmc_calibrate_delay(mmc);
  2857. if (mmc->clock < 26000000) {
  2858. cout_delay = 5000;
  2859. dout_delay = 5000;
  2860. } else if (mmc->clock <= 52000000) {
  2861. cout_delay = 2500;
  2862. dout_delay = 2500;
  2863. } else if (!mmc_is_mode_ddr(mmc->selected_mode)) {
  2864. cout_delay = slot->cmd_out_hs200_delay;
  2865. dout_delay = slot->data_out_hs200_delay;
  2866. } else {
  2867. cout_delay = slot->cmd_out_hs400_delay;
  2868. dout_delay = slot->data_out_hs400_delay;
  2869. }
  2870. snprintf(env_name, sizeof(env_name), "mmc%d_hs200_dout_delay_ps",
  2871. slot->bus_id);
  2872. dout_delay = env_get_ulong(env_name, 10, dout_delay);
  2873. debug("%s: dout_delay: %u\n", __func__, dout_delay);
  2874. cout_bdelay = octeontx2_mmc_calc_delay(mmc, cout_delay);
  2875. dout_bdelay = octeontx2_mmc_calc_delay(mmc, dout_delay);
  2876. debug("%s: cmd output delay: %u, data output delay: %u, cmd bdelay: %d, data bdelay: %d, clock: %d\n",
  2877. __func__, cout_delay, dout_delay, cout_bdelay, dout_bdelay,
  2878. mmc->clock);
  2879. if (cout_bdelay < 0 || dout_bdelay < 0) {
  2880. pr_err("%s: Error: could not calculate command and/or data clock skew\n",
  2881. __func__);
  2882. return -1;
  2883. }
  2884. timing.u = read_csr(mmc, MIO_EMM_TIMING());
  2885. timing.s.cmd_out_tap = cout_bdelay;
  2886. timing.s.data_out_tap = dout_bdelay;
  2887. if (mmc->selected_mode == MMC_HS_200) {
  2888. slot->hs200_taps.s.cmd_out_tap = cout_bdelay;
  2889. slot->hs200_taps.s.data_out_tap = dout_bdelay;
  2890. } else if (mmc->selected_mode == MMC_HS_400) {
  2891. slot->hs400_taps.s.cmd_out_tap = cout_bdelay;
  2892. slot->hs400_taps.s.data_out_tap = dout_bdelay;
  2893. } else {
  2894. slot->taps.s.cmd_out_tap = cout_bdelay;
  2895. slot->taps.s.data_out_tap = dout_bdelay;
  2896. }
  2897. octeontx_mmc_set_emm_timing(mmc, timing);
  2898. debug("%s(%s): bdelay: %d/%d, clock: %d, ddr: %s, timing taps: %llu, do: %d, di: %d, co: %d, ci: %d\n",
  2899. __func__, mmc->dev->name, cout_bdelay, dout_bdelay, mmc->clock,
  2900. mmc->ddr_mode ? "yes" : "no",
  2901. mmc_to_host(mmc)->timing_taps,
  2902. timing.s.data_out_tap,
  2903. timing.s.data_in_tap,
  2904. timing.s.cmd_out_tap,
  2905. timing.s.cmd_in_tap);
  2906. return 0;
  2907. }
  2908. static void octeontx_mmc_set_clock(struct mmc *mmc)
  2909. {
  2910. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  2911. uint clock;
  2912. clock = min(mmc->cfg->f_max, (uint)slot->clock);
  2913. clock = max(mmc->cfg->f_min, clock);
  2914. debug("%s(%s): f_min: %u, f_max: %u, clock: %u\n", __func__,
  2915. mmc->dev->name, mmc->cfg->f_min, mmc->cfg->f_max, clock);
  2916. slot->clock = clock;
  2917. mmc->clock = clock;
  2918. }
  2919. /**
  2920. * This switches I/O power as needed when switching between slots.
  2921. *
  2922. * @param mmc mmc data structure
  2923. */
  2924. static void octeontx_mmc_switch_io(struct mmc *mmc)
  2925. {
  2926. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  2927. struct octeontx_mmc_host *host = slot->host;
  2928. struct mmc *last_mmc = host->last_mmc;
  2929. static struct udevice *last_reg;
  2930. union mio_emm_cfg emm_cfg;
  2931. int bus;
  2932. static bool initialized;
  2933. /* First time? */
  2934. if (!initialized || mmc != host->last_mmc) {
  2935. struct mmc *ommc;
  2936. /* Switch to bus 3 which is unused */
  2937. emm_cfg.u = read_csr(mmc, MIO_EMM_CFG());
  2938. emm_cfg.s.bus_ena = 1 << 3;
  2939. write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
  2940. /* Turn off all other I/O interfaces with first initialization
  2941. * if at least one supply was found.
  2942. */
  2943. for (bus = 0; bus <= OCTEONTX_MAX_MMC_SLOT; bus++) {
  2944. ommc = &host->slots[bus].mmc;
  2945. /* Handle self case later */
  2946. if (ommc == mmc || !ommc->vqmmc_supply)
  2947. continue;
  2948. /* Skip if we're not switching regulators */
  2949. if (last_reg == mmc->vqmmc_supply)
  2950. continue;
  2951. /* Turn off other regulators */
  2952. if (ommc->vqmmc_supply != mmc->vqmmc_supply)
  2953. regulator_set_enable(ommc->vqmmc_supply, false);
  2954. }
  2955. /* Turn ourself on */
  2956. if (mmc->vqmmc_supply && last_reg != mmc->vqmmc_supply)
  2957. regulator_set_enable(mmc->vqmmc_supply, true);
  2958. mdelay(1); /* Settle time */
  2959. /* Switch to new bus */
  2960. emm_cfg.s.bus_ena = 1 << slot->bus_id;
  2961. write_csr(mmc, MIO_EMM_CFG(), emm_cfg.u);
  2962. last_reg = mmc->vqmmc_supply;
  2963. initialized = true;
  2964. return;
  2965. }
  2966. /* No change in device */
  2967. if (last_mmc == mmc)
  2968. return;
  2969. if (!last_mmc) {
  2970. pr_warn("%s(%s): No previous slot detected in IO slot switch!\n",
  2971. __func__, mmc->dev->name);
  2972. return;
  2973. }
  2974. debug("%s(%s): last: %s, supply: %p\n", __func__, mmc->dev->name,
  2975. last_mmc->dev->name, mmc->vqmmc_supply);
  2976. /* The supply is the same so we do nothing */
  2977. if (last_mmc->vqmmc_supply == mmc->vqmmc_supply)
  2978. return;
  2979. /* Turn off the old slot I/O supply */
  2980. if (last_mmc->vqmmc_supply) {
  2981. debug("%s(%s): Turning off IO to %s, supply: %s\n",
  2982. __func__, mmc->dev->name, last_mmc->dev->name,
  2983. last_mmc->vqmmc_supply->name);
  2984. regulator_set_enable(last_mmc->vqmmc_supply, false);
  2985. }
  2986. /* Turn on the new slot I/O supply */
  2987. if (mmc->vqmmc_supply) {
  2988. debug("%s(%s): Turning on IO to slot %d, supply: %s\n",
  2989. __func__, mmc->dev->name, slot->bus_id,
  2990. mmc->vqmmc_supply->name);
  2991. regulator_set_enable(mmc->vqmmc_supply, true);
  2992. }
  2993. /* Allow power to settle */
  2994. mdelay(1);
  2995. }
  2996. /**
  2997. * Called to switch between mmc devices
  2998. *
  2999. * @param mmc new mmc device
  3000. */
  3001. static void octeontx_mmc_switch_to(struct mmc *mmc)
  3002. {
  3003. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  3004. struct octeontx_mmc_slot *old_slot;
  3005. struct octeontx_mmc_host *host = slot->host;
  3006. union mio_emm_switch emm_switch;
  3007. union mio_emm_sts_mask emm_sts_mask;
  3008. union mio_emm_rca emm_rca;
  3009. if (slot->bus_id == host->last_slotid)
  3010. return;
  3011. debug("%s(%s) switching from slot %d to slot %d\n", __func__,
  3012. mmc->dev->name, host->last_slotid, slot->bus_id);
  3013. octeontx_mmc_switch_io(mmc);
  3014. if (host->last_slotid >= 0 && slot->valid) {
  3015. old_slot = &host->slots[host->last_slotid];
  3016. old_slot->cached_switch.u = read_csr(mmc, MIO_EMM_SWITCH());
  3017. old_slot->cached_rca.u = read_csr(mmc, MIO_EMM_RCA());
  3018. }
  3019. if (mmc->rca)
  3020. write_csr(mmc, MIO_EMM_RCA(), mmc->rca);
  3021. emm_switch = slot->cached_switch;
  3022. do_switch(mmc, emm_switch);
  3023. emm_rca.u = 0;
  3024. emm_rca.s.card_rca = mmc->rca;
  3025. write_csr(mmc, MIO_EMM_RCA(), emm_rca.u);
  3026. mdelay(100);
  3027. set_wdog(mmc, 100000);
  3028. if (octeontx_mmc_set_output_bus_timing(mmc) ||
  3029. octeontx_mmc_set_input_bus_timing(mmc))
  3030. pr_err("%s(%s): Error setting bus timing\n", __func__,
  3031. mmc->dev->name);
  3032. octeontx_mmc_io_drive_setup(mmc);
  3033. emm_sts_mask.u = 0;
  3034. emm_sts_mask.s.sts_msk = 1 << 7 | 1 << 22 | 1 << 23 | 1 << 19;
  3035. write_csr(mmc, MIO_EMM_STS_MASK(), emm_sts_mask.u);
  3036. host->last_slotid = slot->bus_id;
  3037. host->last_mmc = mmc;
  3038. mdelay(10);
  3039. }
  3040. /**
  3041. * Perform initial timing configuration
  3042. *
  3043. * @param mmc mmc device
  3044. *
  3045. * @return 0 for success
  3046. *
  3047. * NOTE: This will need to be updated when new silicon comes out
  3048. */
  3049. static int octeontx_mmc_init_timing(struct mmc *mmc)
  3050. {
  3051. union mio_emm_timing timing;
  3052. if (mmc_to_slot(mmc)->is_asim || mmc_to_slot(mmc)->is_emul)
  3053. return 0;
  3054. debug("%s(%s)\n", __func__, mmc->dev->name);
  3055. timing.u = 0;
  3056. timing.s.cmd_out_tap = MMC_DEFAULT_CMD_OUT_TAP;
  3057. timing.s.data_out_tap = MMC_DEFAULT_DATA_OUT_TAP;
  3058. timing.s.cmd_in_tap = MMC_DEFAULT_CMD_IN_TAP;
  3059. timing.s.data_in_tap = MMC_DEFAULT_DATA_IN_TAP;
  3060. octeontx_mmc_set_emm_timing(mmc, timing);
  3061. return 0;
  3062. }
  3063. /**
  3064. * Perform low-level initialization
  3065. *
  3066. * @param mmc mmc device
  3067. *
  3068. * @return 0 for success, error otherwise
  3069. */
  3070. static int octeontx_mmc_init_lowlevel(struct mmc *mmc)
  3071. {
  3072. struct octeontx_mmc_slot *slot = mmc_to_slot(mmc);
  3073. struct octeontx_mmc_host *host = slot->host;
  3074. union mio_emm_switch emm_switch;
  3075. u32 clk_period;
  3076. debug("%s(%s): lowlevel init for slot %d\n", __func__,
  3077. mmc->dev->name, slot->bus_id);
  3078. host->emm_cfg.s.bus_ena &= ~(1 << slot->bus_id);
  3079. write_csr(mmc, MIO_EMM_CFG(), host->emm_cfg.u);
  3080. udelay(100);
  3081. host->emm_cfg.s.bus_ena |= 1 << slot->bus_id;
  3082. write_csr(mmc, MIO_EMM_CFG(), host->emm_cfg.u);
  3083. udelay(10);
  3084. slot->clock = mmc->cfg->f_min;
  3085. octeontx_mmc_set_clock(&slot->mmc);
  3086. if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
  3087. if (host->cond_clock_glitch) {
  3088. union mio_emm_debug emm_debug;
  3089. emm_debug.u = read_csr(mmc, MIO_EMM_DEBUG());
  3090. emm_debug.s.clk_on = 1;
  3091. write_csr(mmc, MIO_EMM_DEBUG(), emm_debug.u);
  3092. }
  3093. octeontx_mmc_calibrate_delay(&slot->mmc);
  3094. }
  3095. clk_period = octeontx_mmc_calc_clk_period(mmc);
  3096. emm_switch.u = 0;
  3097. emm_switch.s.power_class = 10;
  3098. emm_switch.s.clk_lo = clk_period / 2;
  3099. emm_switch.s.clk_hi = clk_period / 2;
  3100. emm_switch.s.bus_id = slot->bus_id;
  3101. debug("%s: Performing switch\n", __func__);
  3102. do_switch(mmc, emm_switch);
  3103. slot->cached_switch.u = emm_switch.u;
  3104. if (!IS_ENABLED(CONFIG_ARCH_OCTEONTX))
  3105. octeontx_mmc_init_timing(mmc);
  3106. set_wdog(mmc, 1000000); /* Set to 1 second */
  3107. write_csr(mmc, MIO_EMM_STS_MASK(), 0xe4390080ull);
  3108. write_csr(mmc, MIO_EMM_RCA(), 1);
  3109. mdelay(10);
  3110. debug("%s: done\n", __func__);
  3111. return 0;
  3112. }
  3113. /**
  3114. * Translates a voltage number to bits in MMC register
  3115. *
  3116. * @param voltage voltage in microvolts
  3117. *
  3118. * @return MMC register value for voltage
  3119. */
  3120. static u32 xlate_voltage(u32 voltage)
  3121. {
  3122. u32 volt = 0;
  3123. /* Convert to millivolts */
  3124. voltage /= 1000;
  3125. if (voltage >= 1650 && voltage <= 1950)
  3126. volt |= MMC_VDD_165_195;
  3127. if (voltage >= 2000 && voltage <= 2100)
  3128. volt |= MMC_VDD_20_21;
  3129. if (voltage >= 2100 && voltage <= 2200)
  3130. volt |= MMC_VDD_21_22;
  3131. if (voltage >= 2200 && voltage <= 2300)
  3132. volt |= MMC_VDD_22_23;
  3133. if (voltage >= 2300 && voltage <= 2400)
  3134. volt |= MMC_VDD_23_24;
  3135. if (voltage >= 2400 && voltage <= 2500)
  3136. volt |= MMC_VDD_24_25;
  3137. if (voltage >= 2500 && voltage <= 2600)
  3138. volt |= MMC_VDD_25_26;
  3139. if (voltage >= 2600 && voltage <= 2700)
  3140. volt |= MMC_VDD_26_27;
  3141. if (voltage >= 2700 && voltage <= 2800)
  3142. volt |= MMC_VDD_27_28;
  3143. if (voltage >= 2800 && voltage <= 2900)
  3144. volt |= MMC_VDD_28_29;
  3145. if (voltage >= 2900 && voltage <= 3000)
  3146. volt |= MMC_VDD_29_30;
  3147. if (voltage >= 3000 && voltage <= 3100)
  3148. volt |= MMC_VDD_30_31;
  3149. if (voltage >= 3100 && voltage <= 3200)
  3150. volt |= MMC_VDD_31_32;
  3151. if (voltage >= 3200 && voltage <= 3300)
  3152. volt |= MMC_VDD_32_33;
  3153. if (voltage >= 3300 && voltage <= 3400)
  3154. volt |= MMC_VDD_33_34;
  3155. if (voltage >= 3400 && voltage <= 3500)
  3156. volt |= MMC_VDD_34_35;
  3157. if (voltage >= 3500 && voltage <= 3600)
  3158. volt |= MMC_VDD_35_36;
  3159. return volt;
  3160. }
  3161. /**
  3162. * Check if a slot is valid in the device tree
  3163. *
  3164. * @param dev slot device to check
  3165. *
  3166. * @return true if status reports "ok" or "okay" or if no status,
  3167. * false otherwise.
  3168. */
  3169. static bool octeontx_mmc_get_valid(struct udevice *dev)
  3170. {
  3171. const char *stat = ofnode_read_string(dev->node, "status");
  3172. if (!stat || !strncmp(stat, "ok", 2))
  3173. return true;
  3174. else
  3175. return false;
  3176. }
  3177. /**
  3178. * Reads slot configuration from the device tree
  3179. *
  3180. * @param dev slot device
  3181. *
  3182. * @return 0 on success, otherwise error
  3183. */
  3184. static int octeontx_mmc_get_config(struct udevice *dev)
  3185. {
  3186. struct octeontx_mmc_slot *slot = dev_to_mmc_slot(dev);
  3187. uint voltages[2];
  3188. uint low, high;
  3189. char env_name[32];
  3190. int err;
  3191. ofnode node = dev->node;
  3192. int bus_width = 1;
  3193. ulong new_max_freq;
  3194. debug("%s(%s)", __func__, dev->name);
  3195. slot->cfg.name = dev->name;
  3196. slot->cfg.f_max = ofnode_read_s32_default(dev->node, "max-frequency",
  3197. 26000000);
  3198. snprintf(env_name, sizeof(env_name), "mmc_max_frequency%d",
  3199. slot->bus_id);
  3200. new_max_freq = env_get_ulong(env_name, 10, slot->cfg.f_max);
  3201. debug("Reading %s, got %lu\n", env_name, new_max_freq);
  3202. if (new_max_freq != slot->cfg.f_max) {
  3203. printf("Overriding device tree MMC maximum frequency %u to %lu\n",
  3204. slot->cfg.f_max, new_max_freq);
  3205. slot->cfg.f_max = new_max_freq;
  3206. }
  3207. slot->cfg.f_min = 400000;
  3208. slot->cfg.b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  3209. if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
  3210. slot->hs400_tuning_block =
  3211. ofnode_read_s32_default(dev->node,
  3212. "marvell,hs400-tuning-block",
  3213. -1);
  3214. debug("%s(%s): mmc HS400 tuning block: %d\n", __func__,
  3215. dev->name, slot->hs400_tuning_block);
  3216. slot->hs200_tap_adj =
  3217. ofnode_read_s32_default(dev->node,
  3218. "marvell,hs200-tap-adjust", 0);
  3219. debug("%s(%s): hs200-tap-adjust: %d\n", __func__, dev->name,
  3220. slot->hs200_tap_adj);
  3221. slot->hs400_tap_adj =
  3222. ofnode_read_s32_default(dev->node,
  3223. "marvell,hs400-tap-adjust", 0);
  3224. debug("%s(%s): hs400-tap-adjust: %d\n", __func__, dev->name,
  3225. slot->hs400_tap_adj);
  3226. }
  3227. err = ofnode_read_u32_array(dev->node, "voltage-ranges", voltages, 2);
  3228. if (err) {
  3229. slot->cfg.voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  3230. } else {
  3231. low = xlate_voltage(voltages[0]);
  3232. high = xlate_voltage(voltages[1]);
  3233. debug(" low voltage: 0x%x (%u), high: 0x%x (%u)\n",
  3234. low, voltages[0], high, voltages[1]);
  3235. if (low > high || !low || !high) {
  3236. pr_err("Invalid MMC voltage range [%u-%u] specified for %s\n",
  3237. low, high, dev->name);
  3238. return -1;
  3239. }
  3240. slot->cfg.voltages = 0;
  3241. do {
  3242. slot->cfg.voltages |= low;
  3243. low <<= 1;
  3244. } while (low <= high);
  3245. }
  3246. debug("%s: config voltages: 0x%x\n", __func__, slot->cfg.voltages);
  3247. slot->slew = ofnode_read_s32_default(node, "cavium,clk-slew", -1);
  3248. slot->drive = ofnode_read_s32_default(node, "cavium,drv-strength", -1);
  3249. gpio_request_by_name(dev, "cd-gpios", 0, &slot->cd_gpio, GPIOD_IS_IN);
  3250. slot->cd_inverted = ofnode_read_bool(node, "cd-inverted");
  3251. gpio_request_by_name(dev, "wp-gpios", 0, &slot->wp_gpio, GPIOD_IS_IN);
  3252. slot->wp_inverted = ofnode_read_bool(node, "wp-inverted");
  3253. if (slot->cfg.voltages & MMC_VDD_165_195) {
  3254. slot->is_1_8v = true;
  3255. slot->is_3_3v = false;
  3256. } else if (slot->cfg.voltages & (MMC_VDD_30_31 | MMC_VDD_31_32 |
  3257. MMC_VDD_33_34 | MMC_VDD_34_35 |
  3258. MMC_VDD_35_36)) {
  3259. slot->is_1_8v = false;
  3260. slot->is_3_3v = true;
  3261. }
  3262. bus_width = ofnode_read_u32_default(node, "bus-width", 1);
  3263. /* Note fall-through */
  3264. switch (bus_width) {
  3265. case 8:
  3266. slot->cfg.host_caps |= MMC_MODE_8BIT;
  3267. case 4:
  3268. slot->cfg.host_caps |= MMC_MODE_4BIT;
  3269. case 1:
  3270. slot->cfg.host_caps |= MMC_MODE_1BIT;
  3271. break;
  3272. }
  3273. if (ofnode_read_bool(node, "no-1-8-v")) {
  3274. slot->is_3_3v = true;
  3275. slot->is_1_8v = false;
  3276. if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34)))
  3277. pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n",
  3278. __func__, dev->name);
  3279. }
  3280. if (ofnode_read_bool(node, "mmc-ddr-3-3v")) {
  3281. slot->is_3_3v = true;
  3282. slot->is_1_8v = false;
  3283. if (!(slot->cfg.voltages & (MMC_VDD_32_33 | MMC_VDD_33_34)))
  3284. pr_warn("%s(%s): voltages indicate 3.3v but 3.3v not supported\n",
  3285. __func__, dev->name);
  3286. }
  3287. if (ofnode_read_bool(node, "cap-sd-highspeed") ||
  3288. ofnode_read_bool(node, "cap-mmc-highspeed") ||
  3289. ofnode_read_bool(node, "sd-uhs-sdr25"))
  3290. slot->cfg.host_caps |= MMC_MODE_HS;
  3291. if (slot->cfg.f_max >= 50000000 &&
  3292. slot->cfg.host_caps & MMC_MODE_HS)
  3293. slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  3294. if (ofnode_read_bool(node, "sd-uhs-sdr50"))
  3295. slot->cfg.host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  3296. if (ofnode_read_bool(node, "sd-uhs-ddr50"))
  3297. slot->cfg.host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz |
  3298. MMC_MODE_DDR_52MHz;
  3299. if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
  3300. if (!slot->is_asim && !slot->is_emul) {
  3301. if (ofnode_read_bool(node, "mmc-hs200-1_8v"))
  3302. slot->cfg.host_caps |= MMC_MODE_HS200 |
  3303. MMC_MODE_HS_52MHz;
  3304. if (ofnode_read_bool(node, "mmc-hs400-1_8v"))
  3305. slot->cfg.host_caps |= MMC_MODE_HS400 |
  3306. MMC_MODE_HS_52MHz |
  3307. MMC_MODE_HS200 |
  3308. MMC_MODE_DDR_52MHz;
  3309. slot->cmd_out_hs200_delay =
  3310. ofnode_read_u32_default(node,
  3311. "marvell,cmd-out-hs200-dly",
  3312. MMC_DEFAULT_HS200_CMD_OUT_DLY);
  3313. debug("%s(%s): HS200 cmd out delay: %d\n",
  3314. __func__, dev->name, slot->cmd_out_hs200_delay);
  3315. slot->data_out_hs200_delay =
  3316. ofnode_read_u32_default(node,
  3317. "marvell,data-out-hs200-dly",
  3318. MMC_DEFAULT_HS200_DATA_OUT_DLY);
  3319. debug("%s(%s): HS200 data out delay: %d\n",
  3320. __func__, dev->name, slot->data_out_hs200_delay);
  3321. slot->cmd_out_hs400_delay =
  3322. ofnode_read_u32_default(node,
  3323. "marvell,cmd-out-hs400-dly",
  3324. MMC_DEFAULT_HS400_CMD_OUT_DLY);
  3325. debug("%s(%s): HS400 cmd out delay: %d\n",
  3326. __func__, dev->name, slot->cmd_out_hs400_delay);
  3327. slot->data_out_hs400_delay =
  3328. ofnode_read_u32_default(node,
  3329. "marvell,data-out-hs400-dly",
  3330. MMC_DEFAULT_HS400_DATA_OUT_DLY);
  3331. debug("%s(%s): HS400 data out delay: %d\n",
  3332. __func__, dev->name, slot->data_out_hs400_delay);
  3333. }
  3334. }
  3335. slot->disable_ddr = ofnode_read_bool(node, "marvell,disable-ddr");
  3336. slot->non_removable = ofnode_read_bool(node, "non-removable");
  3337. slot->cmd_clk_skew = ofnode_read_u32_default(node,
  3338. "cavium,cmd-clk-skew", 0);
  3339. slot->dat_clk_skew = ofnode_read_u32_default(node,
  3340. "cavium,dat-clk-skew", 0);
  3341. debug("%s(%s): host caps: 0x%x\n", __func__,
  3342. dev->name, slot->cfg.host_caps);
  3343. return 0;
  3344. }
  3345. /**
  3346. * Probes a MMC slot
  3347. *
  3348. * @param dev mmc device
  3349. *
  3350. * @return 0 for success, error otherwise
  3351. */
  3352. static int octeontx_mmc_slot_probe(struct udevice *dev)
  3353. {
  3354. struct octeontx_mmc_slot *slot;
  3355. struct mmc *mmc;
  3356. int err;
  3357. printk("%s (%d)\n", __func__, __LINE__); // test-only
  3358. debug("%s(%s)\n", __func__, dev->name);
  3359. if (!host_probed) {
  3360. pr_err("%s(%s): Error: host not probed yet\n",
  3361. __func__, dev->name);
  3362. }
  3363. slot = dev_to_mmc_slot(dev);
  3364. mmc = &slot->mmc;
  3365. mmc->dev = dev;
  3366. slot->valid = false;
  3367. if (!octeontx_mmc_get_valid(dev)) {
  3368. debug("%s(%s): slot is invalid\n", __func__, dev->name);
  3369. return -ENODEV;
  3370. }
  3371. debug("%s(%s): Getting config\n", __func__, dev->name);
  3372. err = octeontx_mmc_get_config(dev);
  3373. if (err) {
  3374. pr_err("probe(%s): Error getting config\n", dev->name);
  3375. return err;
  3376. }
  3377. debug("%s(%s): mmc bind, mmc: %p\n", __func__, dev->name, &slot->mmc);
  3378. err = mmc_bind(dev, &slot->mmc, &slot->cfg);
  3379. if (err) {
  3380. pr_err("%s(%s): Error binding mmc\n", __func__, dev->name);
  3381. return -1;
  3382. }
  3383. /* For some reason, mmc_bind always assigns priv to the device */
  3384. slot->mmc.priv = slot;
  3385. debug("%s(%s): lowlevel init\n", __func__, dev->name);
  3386. err = octeontx_mmc_init_lowlevel(mmc);
  3387. if (err) {
  3388. pr_err("probe(%s): Low-level init failed\n", dev->name);
  3389. return err;
  3390. }
  3391. slot->valid = true;
  3392. debug("%s(%s):\n"
  3393. " base address : %p\n"
  3394. " bus id : %d\n", __func__, dev->name,
  3395. slot->base_addr, slot->bus_id);
  3396. return err;
  3397. }
  3398. /**
  3399. * MMC slot driver operations
  3400. */
  3401. static const struct dm_mmc_ops octeontx_hsmmc_ops = {
  3402. .send_cmd = octeontx_mmc_dev_send_cmd,
  3403. .set_ios = octeontx_mmc_set_ios,
  3404. .get_cd = octeontx_mmc_get_cd,
  3405. .get_wp = octeontx_mmc_get_wp,
  3406. #ifdef MMC_SUPPORTS_TUNING
  3407. .execute_tuning = octeontx_mmc_execute_tuning,
  3408. #endif
  3409. };
  3410. static const struct udevice_id octeontx_hsmmc_ids[] = {
  3411. { .compatible = "mmc-slot" },
  3412. { }
  3413. };
  3414. U_BOOT_DRIVER(octeontx_hsmmc_slot) = {
  3415. .name = "octeontx_hsmmc_slot",
  3416. .id = UCLASS_MMC,
  3417. .of_match = of_match_ptr(octeontx_hsmmc_ids),
  3418. .probe = octeontx_mmc_slot_probe,
  3419. .ops = &octeontx_hsmmc_ops,
  3420. };
  3421. /*****************************************************************
  3422. * PCI host driver
  3423. *
  3424. * The PCI host driver contains the resources used by all of the
  3425. * slot drivers.
  3426. *
  3427. * The slot drivers are pseudo drivers.
  3428. */
  3429. /**
  3430. * Probe the MMC host controller
  3431. *
  3432. * @param dev mmc host controller device
  3433. *
  3434. * @return 0 for success, -1 on error
  3435. */
  3436. static int octeontx_mmc_host_probe(struct udevice *dev)
  3437. {
  3438. pci_dev_t bdf = dm_pci_get_bdf(dev);
  3439. struct octeontx_mmc_host *host = dev_get_priv(dev);
  3440. union mio_emm_int emm_int;
  3441. u8 rev;
  3442. debug("%s(%s): Entry host: %p\n", __func__, dev->name, host);
  3443. if (!octeontx_mmc_get_valid(dev)) {
  3444. debug("%s(%s): mmc host not valid\n", __func__, dev->name);
  3445. return -ENODEV;
  3446. }
  3447. memset(host, 0, sizeof(*host));
  3448. host->base_addr = dm_pci_map_bar(dev, PCI_BASE_ADDRESS_0,
  3449. PCI_REGION_MEM);
  3450. if (!host->base_addr) {
  3451. pr_err("%s: Error: MMC base address not found\n", __func__);
  3452. return -1;
  3453. }
  3454. host->dev = dev;
  3455. debug("%s(%s): Base address: %p\n", __func__, dev->name,
  3456. host->base_addr);
  3457. if (!dev_has_of_node(dev)) {
  3458. pr_err("%s: No device tree information found\n", __func__);
  3459. return -1;
  3460. }
  3461. host->node = dev->node;
  3462. dev->req_seq = PCI_FUNC(bdf);
  3463. host->last_slotid = -1;
  3464. if (otx_is_platform(PLATFORM_ASIM))
  3465. host->is_asim = true;
  3466. if (otx_is_platform(PLATFORM_EMULATOR))
  3467. host->is_emul = true;
  3468. host->dma_wait_delay =
  3469. ofnode_read_u32_default(dev->node, "marvell,dma-wait-delay", 1);
  3470. /* Force reset of eMMC */
  3471. writeq(0, host->base_addr + MIO_EMM_CFG());
  3472. debug("%s: Clearing MIO_EMM_CFG\n", __func__);
  3473. udelay(100);
  3474. emm_int.u = readq(host->base_addr + MIO_EMM_INT());
  3475. debug("%s: Writing 0x%llx to MIO_EMM_INT\n", __func__, emm_int.u);
  3476. writeq(emm_int.u, host->base_addr + MIO_EMM_INT());
  3477. debug("%s(%s): Getting I/O clock\n", __func__, dev->name);
  3478. host->sys_freq = octeontx_get_io_clock();
  3479. debug("%s(%s): I/O clock %llu\n", __func__, dev->name, host->sys_freq);
  3480. if (IS_ENABLED(CONFIG_ARCH_OCTEONTX2)) {
  3481. /* Flags for issues to work around */
  3482. dm_pci_read_config8(dev, PCI_REVISION_ID, &rev);
  3483. if (otx_is_soc(CN96XX)) {
  3484. debug("%s: CN96XX revision %d\n", __func__, rev);
  3485. switch (rev) {
  3486. case 0:
  3487. host->calibrate_glitch = true;
  3488. host->cond_clock_glitch = true;
  3489. break;
  3490. case 1:
  3491. break;
  3492. case 2:
  3493. break;
  3494. case 0x10: /* C0 */
  3495. host->hs400_skew_needed = true;
  3496. debug("HS400 skew support enabled\n");
  3497. fallthrough;
  3498. default:
  3499. debug("CN96XX rev C0+ detected\n");
  3500. host->tap_requires_noclk = true;
  3501. break;
  3502. }
  3503. } else if (otx_is_soc(CN95XX)) {
  3504. if (!rev)
  3505. host->cond_clock_glitch = true;
  3506. }
  3507. }
  3508. host_probed = true;
  3509. return 0;
  3510. }
  3511. /**
  3512. * This performs some initial setup before a probe occurs.
  3513. *
  3514. * @param dev: MMC slot device
  3515. *
  3516. * @return 0 for success, -1 on failure
  3517. *
  3518. * Do some pre-initialization before probing a slot.
  3519. */
  3520. static int octeontx_mmc_host_child_pre_probe(struct udevice *dev)
  3521. {
  3522. struct octeontx_mmc_host *host = dev_get_priv(dev_get_parent(dev));
  3523. struct octeontx_mmc_slot *slot;
  3524. struct mmc_uclass_priv *upriv;
  3525. ofnode node = dev->node;
  3526. u32 bus_id;
  3527. char name[16];
  3528. int err;
  3529. debug("%s(%s) Pre-Probe\n", __func__, dev->name);
  3530. if (ofnode_read_u32(node, "reg", &bus_id)) {
  3531. pr_err("%s(%s): Error: \"reg\" not found in device tree\n",
  3532. __func__, dev->name);
  3533. return -1;
  3534. }
  3535. if (bus_id > OCTEONTX_MAX_MMC_SLOT) {
  3536. pr_err("%s(%s): Error: \"reg\" out of range of 0..%d\n",
  3537. __func__, dev->name, OCTEONTX_MAX_MMC_SLOT);
  3538. return -1;
  3539. }
  3540. slot = &host->slots[bus_id];
  3541. dev->priv = slot;
  3542. slot->host = host;
  3543. slot->bus_id = bus_id;
  3544. slot->dev = dev;
  3545. slot->base_addr = host->base_addr;
  3546. slot->is_asim = host->is_asim;
  3547. slot->is_emul = host->is_emul;
  3548. snprintf(name, sizeof(name), "octeontx-mmc%d", bus_id);
  3549. err = device_set_name(dev, name);
  3550. if (!dev->uclass_priv) {
  3551. debug("%s(%s): Allocating uclass priv\n", __func__,
  3552. dev->name);
  3553. upriv = calloc(1, sizeof(struct mmc_uclass_priv));
  3554. if (!upriv)
  3555. return -ENOMEM;
  3556. dev->uclass_priv = upriv;
  3557. dev->uclass->priv = upriv;
  3558. } else {
  3559. upriv = dev->uclass_priv;
  3560. }
  3561. upriv->mmc = &slot->mmc;
  3562. debug("%s: uclass priv: %p, mmc: %p\n", dev->name, upriv, upriv->mmc);
  3563. debug("%s: ret: %d\n", __func__, err);
  3564. return err;
  3565. }
  3566. static const struct udevice_id octeontx_hsmmc_host_ids[] = {
  3567. { .compatible = "cavium,thunder-8890-mmc" },
  3568. { }
  3569. };
  3570. U_BOOT_DRIVER(octeontx_hsmmc_host) = {
  3571. .name = "octeontx_hsmmc_host",
  3572. .id = UCLASS_MISC,
  3573. .of_match = of_match_ptr(octeontx_hsmmc_host_ids),
  3574. .probe = octeontx_mmc_host_probe,
  3575. .priv_auto_alloc_size = sizeof(struct octeontx_mmc_host),
  3576. .child_pre_probe = octeontx_mmc_host_child_pre_probe,
  3577. .flags = DM_FLAG_PRE_RELOC,
  3578. };
  3579. static struct pci_device_id octeontx_mmc_supported[] = {
  3580. { PCI_VDEVICE(CAVIUM, PCI_DEVICE_ID_CAVIUM_EMMC) },
  3581. { },
  3582. };
  3583. U_BOOT_PCI_DEVICE(octeontx_hsmmc_host, octeontx_mmc_supported);