mxcmmc.c 12 KB

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  1. /*
  2. * This is a driver for the SDHC controller found in Freescale MX2/MX3
  3. * SoCs. It is basically the same hardware as found on MX1 (imxmmc.c).
  4. * Unlike the hardware found on MX1, this hardware just works and does
  5. * not need all the quirks found in imxmmc.c, hence the seperate driver.
  6. *
  7. * Copyright (C) 2009 Ilya Yanok, <yanok@emcraft.com>
  8. * Copyright (C) 2008 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
  9. * Copyright (C) 2006 Pavel Pisa, PiKRON <ppisa@pikron.com>
  10. *
  11. * derived from pxamci.c by Russell King
  12. *
  13. * This program is free software; you can redistribute it and/or modify
  14. * it under the terms of the GNU General Public License version 2 as
  15. * published by the Free Software Foundation.
  16. *
  17. */
  18. #include <config.h>
  19. #include <common.h>
  20. #include <command.h>
  21. #include <mmc.h>
  22. #include <part.h>
  23. #include <malloc.h>
  24. #include <mmc.h>
  25. #include <time.h>
  26. #include <linux/errno.h>
  27. #include <asm/io.h>
  28. #include <asm/arch/clock.h>
  29. #define DRIVER_NAME "mxc-mmc"
  30. struct mxcmci_regs {
  31. u32 str_stp_clk;
  32. u32 status;
  33. u32 clk_rate;
  34. u32 cmd_dat_cont;
  35. u32 res_to;
  36. u32 read_to;
  37. u32 blk_len;
  38. u32 nob;
  39. u32 rev_no;
  40. u32 int_cntr;
  41. u32 cmd;
  42. u32 arg;
  43. u32 pad;
  44. u32 res_fifo;
  45. u32 buffer_access;
  46. };
  47. #define STR_STP_CLK_RESET (1 << 3)
  48. #define STR_STP_CLK_START_CLK (1 << 1)
  49. #define STR_STP_CLK_STOP_CLK (1 << 0)
  50. #define STATUS_CARD_INSERTION (1 << 31)
  51. #define STATUS_CARD_REMOVAL (1 << 30)
  52. #define STATUS_YBUF_EMPTY (1 << 29)
  53. #define STATUS_XBUF_EMPTY (1 << 28)
  54. #define STATUS_YBUF_FULL (1 << 27)
  55. #define STATUS_XBUF_FULL (1 << 26)
  56. #define STATUS_BUF_UND_RUN (1 << 25)
  57. #define STATUS_BUF_OVFL (1 << 24)
  58. #define STATUS_SDIO_INT_ACTIVE (1 << 14)
  59. #define STATUS_END_CMD_RESP (1 << 13)
  60. #define STATUS_WRITE_OP_DONE (1 << 12)
  61. #define STATUS_DATA_TRANS_DONE (1 << 11)
  62. #define STATUS_READ_OP_DONE (1 << 11)
  63. #define STATUS_WR_CRC_ERROR_CODE_MASK (3 << 10)
  64. #define STATUS_CARD_BUS_CLK_RUN (1 << 8)
  65. #define STATUS_BUF_READ_RDY (1 << 7)
  66. #define STATUS_BUF_WRITE_RDY (1 << 6)
  67. #define STATUS_RESP_CRC_ERR (1 << 5)
  68. #define STATUS_CRC_READ_ERR (1 << 3)
  69. #define STATUS_CRC_WRITE_ERR (1 << 2)
  70. #define STATUS_TIME_OUT_RESP (1 << 1)
  71. #define STATUS_TIME_OUT_READ (1 << 0)
  72. #define STATUS_ERR_MASK 0x2f
  73. #define CMD_DAT_CONT_CMD_RESP_LONG_OFF (1 << 12)
  74. #define CMD_DAT_CONT_STOP_READWAIT (1 << 11)
  75. #define CMD_DAT_CONT_START_READWAIT (1 << 10)
  76. #define CMD_DAT_CONT_BUS_WIDTH_4 (2 << 8)
  77. #define CMD_DAT_CONT_INIT (1 << 7)
  78. #define CMD_DAT_CONT_WRITE (1 << 4)
  79. #define CMD_DAT_CONT_DATA_ENABLE (1 << 3)
  80. #define CMD_DAT_CONT_RESPONSE_48BIT_CRC (1 << 0)
  81. #define CMD_DAT_CONT_RESPONSE_136BIT (2 << 0)
  82. #define CMD_DAT_CONT_RESPONSE_48BIT (3 << 0)
  83. #define INT_SDIO_INT_WKP_EN (1 << 18)
  84. #define INT_CARD_INSERTION_WKP_EN (1 << 17)
  85. #define INT_CARD_REMOVAL_WKP_EN (1 << 16)
  86. #define INT_CARD_INSERTION_EN (1 << 15)
  87. #define INT_CARD_REMOVAL_EN (1 << 14)
  88. #define INT_SDIO_IRQ_EN (1 << 13)
  89. #define INT_DAT0_EN (1 << 12)
  90. #define INT_BUF_READ_EN (1 << 4)
  91. #define INT_BUF_WRITE_EN (1 << 3)
  92. #define INT_END_CMD_RES_EN (1 << 2)
  93. #define INT_WRITE_OP_DONE_EN (1 << 1)
  94. #define INT_READ_OP_EN (1 << 0)
  95. struct mxcmci_host {
  96. struct mmc *mmc;
  97. struct mxcmci_regs *base;
  98. int irq;
  99. int detect_irq;
  100. int dma;
  101. int do_dma;
  102. unsigned int power_mode;
  103. struct mmc_cmd *cmd;
  104. struct mmc_data *data;
  105. unsigned int dma_nents;
  106. unsigned int datasize;
  107. unsigned int dma_dir;
  108. u16 rev_no;
  109. unsigned int cmdat;
  110. int clock;
  111. };
  112. static struct mxcmci_host mxcmci_host;
  113. /* maintainer note: do we really want to have a global host pointer? */
  114. static struct mxcmci_host *host = &mxcmci_host;
  115. static inline int mxcmci_use_dma(struct mxcmci_host *host)
  116. {
  117. return host->do_dma;
  118. }
  119. static void mxcmci_softreset(struct mxcmci_host *host)
  120. {
  121. int i;
  122. /* reset sequence */
  123. writel(STR_STP_CLK_RESET, &host->base->str_stp_clk);
  124. writel(STR_STP_CLK_RESET | STR_STP_CLK_START_CLK,
  125. &host->base->str_stp_clk);
  126. for (i = 0; i < 8; i++)
  127. writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
  128. writel(0xff, &host->base->res_to);
  129. }
  130. static void mxcmci_setup_data(struct mxcmci_host *host, struct mmc_data *data)
  131. {
  132. unsigned int nob = data->blocks;
  133. unsigned int blksz = data->blocksize;
  134. unsigned int datasize = nob * blksz;
  135. host->data = data;
  136. writel(nob, &host->base->nob);
  137. writel(blksz, &host->base->blk_len);
  138. host->datasize = datasize;
  139. }
  140. static int mxcmci_start_cmd(struct mxcmci_host *host, struct mmc_cmd *cmd,
  141. unsigned int cmdat)
  142. {
  143. if (host->cmd != NULL)
  144. printf("mxcmci: error!\n");
  145. host->cmd = cmd;
  146. switch (cmd->resp_type) {
  147. case MMC_RSP_R1: /* short CRC, OPCODE */
  148. case MMC_RSP_R1b:/* short CRC, OPCODE, BUSY */
  149. cmdat |= CMD_DAT_CONT_RESPONSE_48BIT_CRC;
  150. break;
  151. case MMC_RSP_R2: /* long 136 bit + CRC */
  152. cmdat |= CMD_DAT_CONT_RESPONSE_136BIT;
  153. break;
  154. case MMC_RSP_R3: /* short */
  155. cmdat |= CMD_DAT_CONT_RESPONSE_48BIT;
  156. break;
  157. case MMC_RSP_NONE:
  158. break;
  159. default:
  160. printf("mxcmci: unhandled response type 0x%x\n",
  161. cmd->resp_type);
  162. return -EINVAL;
  163. }
  164. writel(cmd->cmdidx, &host->base->cmd);
  165. writel(cmd->cmdarg, &host->base->arg);
  166. writel(cmdat, &host->base->cmd_dat_cont);
  167. return 0;
  168. }
  169. static void mxcmci_finish_request(struct mxcmci_host *host,
  170. struct mmc_cmd *cmd, struct mmc_data *data)
  171. {
  172. host->cmd = NULL;
  173. host->data = NULL;
  174. }
  175. static int mxcmci_finish_data(struct mxcmci_host *host, unsigned int stat)
  176. {
  177. int data_error = 0;
  178. if (stat & STATUS_ERR_MASK) {
  179. printf("request failed. status: 0x%08x\n",
  180. stat);
  181. if (stat & STATUS_CRC_READ_ERR) {
  182. data_error = -EILSEQ;
  183. } else if (stat & STATUS_CRC_WRITE_ERR) {
  184. u32 err_code = (stat >> 9) & 0x3;
  185. if (err_code == 2) /* No CRC response */
  186. data_error = -ETIMEDOUT;
  187. else
  188. data_error = -EILSEQ;
  189. } else if (stat & STATUS_TIME_OUT_READ) {
  190. data_error = -ETIMEDOUT;
  191. } else {
  192. data_error = -EIO;
  193. }
  194. }
  195. host->data = NULL;
  196. return data_error;
  197. }
  198. static int mxcmci_read_response(struct mxcmci_host *host, unsigned int stat)
  199. {
  200. struct mmc_cmd *cmd = host->cmd;
  201. int i;
  202. u32 a, b, c;
  203. u32 *resp = (u32 *)cmd->response;
  204. if (!cmd)
  205. return 0;
  206. if (stat & STATUS_TIME_OUT_RESP) {
  207. printf("CMD TIMEOUT\n");
  208. return -ETIMEDOUT;
  209. } else if (stat & STATUS_RESP_CRC_ERR && cmd->resp_type & MMC_RSP_CRC) {
  210. printf("cmd crc error\n");
  211. return -EILSEQ;
  212. }
  213. if (cmd->resp_type & MMC_RSP_PRESENT) {
  214. if (cmd->resp_type & MMC_RSP_136) {
  215. for (i = 0; i < 4; i++) {
  216. a = readl(&host->base->res_fifo) & 0xFFFF;
  217. b = readl(&host->base->res_fifo) & 0xFFFF;
  218. resp[i] = a << 16 | b;
  219. }
  220. } else {
  221. a = readl(&host->base->res_fifo) & 0xFFFF;
  222. b = readl(&host->base->res_fifo) & 0xFFFF;
  223. c = readl(&host->base->res_fifo) & 0xFFFF;
  224. resp[0] = a << 24 | b << 8 | c >> 8;
  225. }
  226. }
  227. return 0;
  228. }
  229. static int mxcmci_poll_status(struct mxcmci_host *host, u32 mask)
  230. {
  231. u32 stat;
  232. unsigned long timeout = get_ticks() + CONFIG_SYS_HZ;
  233. do {
  234. stat = readl(&host->base->status);
  235. if (stat & STATUS_ERR_MASK)
  236. return stat;
  237. if (timeout < get_ticks())
  238. return STATUS_TIME_OUT_READ;
  239. if (stat & mask)
  240. return 0;
  241. } while (1);
  242. }
  243. static int mxcmci_pull(struct mxcmci_host *host, void *_buf, int bytes)
  244. {
  245. unsigned int stat;
  246. u32 *buf = _buf;
  247. while (bytes > 3) {
  248. stat = mxcmci_poll_status(host,
  249. STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
  250. if (stat)
  251. return stat;
  252. *buf++ = readl(&host->base->buffer_access);
  253. bytes -= 4;
  254. }
  255. if (bytes) {
  256. u8 *b = (u8 *)buf;
  257. u32 tmp;
  258. stat = mxcmci_poll_status(host,
  259. STATUS_BUF_READ_RDY | STATUS_READ_OP_DONE);
  260. if (stat)
  261. return stat;
  262. tmp = readl(&host->base->buffer_access);
  263. memcpy(b, &tmp, bytes);
  264. }
  265. return 0;
  266. }
  267. static int mxcmci_push(struct mxcmci_host *host, const void *_buf, int bytes)
  268. {
  269. unsigned int stat;
  270. const u32 *buf = _buf;
  271. while (bytes > 3) {
  272. stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
  273. if (stat)
  274. return stat;
  275. writel(*buf++, &host->base->buffer_access);
  276. bytes -= 4;
  277. }
  278. if (bytes) {
  279. const u8 *b = (u8 *)buf;
  280. u32 tmp;
  281. stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
  282. if (stat)
  283. return stat;
  284. memcpy(&tmp, b, bytes);
  285. writel(tmp, &host->base->buffer_access);
  286. }
  287. stat = mxcmci_poll_status(host, STATUS_BUF_WRITE_RDY);
  288. if (stat)
  289. return stat;
  290. return 0;
  291. }
  292. static int mxcmci_transfer_data(struct mxcmci_host *host)
  293. {
  294. struct mmc_data *data = host->data;
  295. int stat;
  296. unsigned long length;
  297. length = data->blocks * data->blocksize;
  298. host->datasize = 0;
  299. if (data->flags & MMC_DATA_READ) {
  300. stat = mxcmci_pull(host, data->dest, length);
  301. if (stat)
  302. return stat;
  303. host->datasize += length;
  304. } else {
  305. stat = mxcmci_push(host, (const void *)(data->src), length);
  306. if (stat)
  307. return stat;
  308. host->datasize += length;
  309. stat = mxcmci_poll_status(host, STATUS_WRITE_OP_DONE);
  310. if (stat)
  311. return stat;
  312. }
  313. return 0;
  314. }
  315. static int mxcmci_cmd_done(struct mxcmci_host *host, unsigned int stat)
  316. {
  317. int datastat;
  318. int ret;
  319. ret = mxcmci_read_response(host, stat);
  320. if (ret) {
  321. mxcmci_finish_request(host, host->cmd, host->data);
  322. return ret;
  323. }
  324. if (!host->data) {
  325. mxcmci_finish_request(host, host->cmd, host->data);
  326. return 0;
  327. }
  328. datastat = mxcmci_transfer_data(host);
  329. ret = mxcmci_finish_data(host, datastat);
  330. mxcmci_finish_request(host, host->cmd, host->data);
  331. return ret;
  332. }
  333. static int mxcmci_request(struct mmc *mmc, struct mmc_cmd *cmd,
  334. struct mmc_data *data)
  335. {
  336. struct mxcmci_host *host = mmc->priv;
  337. unsigned int cmdat = host->cmdat;
  338. u32 stat;
  339. int ret;
  340. host->cmdat &= ~CMD_DAT_CONT_INIT;
  341. if (data) {
  342. mxcmci_setup_data(host, data);
  343. cmdat |= CMD_DAT_CONT_DATA_ENABLE;
  344. if (data->flags & MMC_DATA_WRITE)
  345. cmdat |= CMD_DAT_CONT_WRITE;
  346. }
  347. if ((ret = mxcmci_start_cmd(host, cmd, cmdat))) {
  348. mxcmci_finish_request(host, cmd, data);
  349. return ret;
  350. }
  351. do {
  352. stat = readl(&host->base->status);
  353. writel(stat, &host->base->status);
  354. } while (!(stat & STATUS_END_CMD_RESP));
  355. return mxcmci_cmd_done(host, stat);
  356. }
  357. static void mxcmci_set_clk_rate(struct mxcmci_host *host, unsigned int clk_ios)
  358. {
  359. unsigned int divider;
  360. int prescaler = 0;
  361. unsigned long clk_in = mxc_get_clock(MXC_ESDHC_CLK);
  362. while (prescaler <= 0x800) {
  363. for (divider = 1; divider <= 0xF; divider++) {
  364. int x;
  365. x = (clk_in / (divider + 1));
  366. if (prescaler)
  367. x /= (prescaler * 2);
  368. if (x <= clk_ios)
  369. break;
  370. }
  371. if (divider < 0x10)
  372. break;
  373. if (prescaler == 0)
  374. prescaler = 1;
  375. else
  376. prescaler <<= 1;
  377. }
  378. writel((prescaler << 4) | divider, &host->base->clk_rate);
  379. }
  380. static int mxcmci_set_ios(struct mmc *mmc)
  381. {
  382. struct mxcmci_host *host = mmc->priv;
  383. if (mmc->bus_width == 4)
  384. host->cmdat |= CMD_DAT_CONT_BUS_WIDTH_4;
  385. else
  386. host->cmdat &= ~CMD_DAT_CONT_BUS_WIDTH_4;
  387. if (mmc->clock) {
  388. mxcmci_set_clk_rate(host, mmc->clock);
  389. writel(STR_STP_CLK_START_CLK, &host->base->str_stp_clk);
  390. } else {
  391. writel(STR_STP_CLK_STOP_CLK, &host->base->str_stp_clk);
  392. }
  393. host->clock = mmc->clock;
  394. return 0;
  395. }
  396. static int mxcmci_init(struct mmc *mmc)
  397. {
  398. struct mxcmci_host *host = mmc->priv;
  399. mxcmci_softreset(host);
  400. host->rev_no = readl(&host->base->rev_no);
  401. if (host->rev_no != 0x400) {
  402. printf("wrong rev.no. 0x%08x. aborting.\n",
  403. host->rev_no);
  404. return -ENODEV;
  405. }
  406. /* recommended in data sheet */
  407. writel(0x2db4, &host->base->read_to);
  408. writel(0, &host->base->int_cntr);
  409. return 0;
  410. }
  411. static const struct mmc_ops mxcmci_ops = {
  412. .send_cmd = mxcmci_request,
  413. .set_ios = mxcmci_set_ios,
  414. .init = mxcmci_init,
  415. };
  416. static struct mmc_config mxcmci_cfg = {
  417. .name = "MXC MCI",
  418. .ops = &mxcmci_ops,
  419. .host_caps = MMC_MODE_4BIT,
  420. .voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  421. .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  422. };
  423. static int mxcmci_initialize(struct bd_info *bis)
  424. {
  425. host->base = (struct mxcmci_regs *)CONFIG_MXC_MCI_REGS_BASE;
  426. mxcmci_cfg.f_min = mxc_get_clock(MXC_ESDHC_CLK) >> 7;
  427. mxcmci_cfg.f_max = mxc_get_clock(MXC_ESDHC_CLK) >> 1;
  428. host->mmc = mmc_create(&mxcmci_cfg, host);
  429. if (host->mmc == NULL)
  430. return -1;
  431. return 0;
  432. }
  433. int mxc_mmc_init(struct bd_info *bis)
  434. {
  435. return mxcmci_initialize(bis);
  436. }