msm_sdhci.c 5.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Qualcomm SDHCI driver - SD/eMMC controller
  4. *
  5. * (C) Copyright 2015 Mateusz Kulikowski <mateusz.kulikowski@gmail.com>
  6. *
  7. * Based on Linux driver
  8. */
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <malloc.h>
  13. #include <sdhci.h>
  14. #include <wait_bit.h>
  15. #include <asm/io.h>
  16. #include <linux/bitops.h>
  17. /* Non-standard registers needed for SDHCI startup */
  18. #define SDCC_MCI_POWER 0x0
  19. #define SDCC_MCI_POWER_SW_RST BIT(7)
  20. /* This is undocumented register */
  21. #define SDCC_MCI_VERSION 0x50
  22. #define SDCC_MCI_VERSION_MAJOR_SHIFT 28
  23. #define SDCC_MCI_VERSION_MAJOR_MASK (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
  24. #define SDCC_MCI_VERSION_MINOR_MASK 0xff
  25. #define SDCC_MCI_STATUS2 0x6C
  26. #define SDCC_MCI_STATUS2_MCI_ACT 0x1
  27. #define SDCC_MCI_HC_MODE 0x78
  28. /* Offset to SDHCI registers */
  29. #define SDCC_SDHCI_OFFSET 0x900
  30. /* Non standard (?) SDHCI register */
  31. #define SDHCI_VENDOR_SPEC_CAPABILITIES0 0x11c
  32. struct msm_sdhc_plat {
  33. struct mmc_config cfg;
  34. struct mmc mmc;
  35. };
  36. struct msm_sdhc {
  37. struct sdhci_host host;
  38. void *base;
  39. };
  40. DECLARE_GLOBAL_DATA_PTR;
  41. static int msm_sdc_clk_init(struct udevice *dev)
  42. {
  43. int node = dev_of_offset(dev);
  44. uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
  45. 400000);
  46. uint clkd[2]; /* clk_id and clk_no */
  47. int clk_offset;
  48. struct udevice *clk_dev;
  49. struct clk clk;
  50. int ret;
  51. ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
  52. if (ret)
  53. return ret;
  54. clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
  55. if (clk_offset < 0)
  56. return clk_offset;
  57. ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
  58. if (ret)
  59. return ret;
  60. clk.id = clkd[1];
  61. ret = clk_request(clk_dev, &clk);
  62. if (ret < 0)
  63. return ret;
  64. ret = clk_set_rate(&clk, clk_rate);
  65. clk_free(&clk);
  66. if (ret < 0)
  67. return ret;
  68. return 0;
  69. }
  70. static int msm_sdc_probe(struct udevice *dev)
  71. {
  72. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  73. struct msm_sdhc_plat *plat = dev_get_platdata(dev);
  74. struct msm_sdhc *prv = dev_get_priv(dev);
  75. struct sdhci_host *host = &prv->host;
  76. u32 core_version, core_minor, core_major;
  77. u32 caps;
  78. int ret;
  79. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
  80. host->max_clk = 0;
  81. /* Init clocks */
  82. ret = msm_sdc_clk_init(dev);
  83. if (ret)
  84. return ret;
  85. /* Reset the core and Enable SDHC mode */
  86. writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
  87. prv->base + SDCC_MCI_POWER);
  88. /* Wait for reset to be written to register */
  89. if (wait_for_bit_le32(prv->base + SDCC_MCI_STATUS2,
  90. SDCC_MCI_STATUS2_MCI_ACT, false, 10, false)) {
  91. printf("msm_sdhci: reset request failed\n");
  92. return -EIO;
  93. }
  94. /* SW reset can take upto 10HCLK + 15MCLK cycles. (min 40us) */
  95. if (wait_for_bit_le32(prv->base + SDCC_MCI_POWER,
  96. SDCC_MCI_POWER_SW_RST, false, 2, false)) {
  97. printf("msm_sdhci: stuck in reset\n");
  98. return -ETIMEDOUT;
  99. }
  100. /* Enable host-controller mode */
  101. writel(1, prv->base + SDCC_MCI_HC_MODE);
  102. core_version = readl(prv->base + SDCC_MCI_VERSION);
  103. core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK);
  104. core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT;
  105. core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK;
  106. /*
  107. * Support for some capabilities is not advertised by newer
  108. * controller versions and must be explicitly enabled.
  109. */
  110. if (core_major >= 1 && core_minor != 0x11 && core_minor != 0x12) {
  111. caps = readl(host->ioaddr + SDHCI_CAPABILITIES);
  112. caps |= SDHCI_CAN_VDD_300 | SDHCI_CAN_DO_8BIT;
  113. writel(caps, host->ioaddr + SDHCI_VENDOR_SPEC_CAPABILITIES0);
  114. }
  115. ret = mmc_of_parse(dev, &plat->cfg);
  116. if (ret)
  117. return ret;
  118. host->mmc = &plat->mmc;
  119. host->mmc->dev = dev;
  120. ret = sdhci_setup_cfg(&plat->cfg, host, 0, 0);
  121. if (ret)
  122. return ret;
  123. host->mmc->priv = &prv->host;
  124. upriv->mmc = host->mmc;
  125. return sdhci_probe(dev);
  126. }
  127. static int msm_sdc_remove(struct udevice *dev)
  128. {
  129. struct msm_sdhc *priv = dev_get_priv(dev);
  130. /* Disable host-controller mode */
  131. writel(0, priv->base + SDCC_MCI_HC_MODE);
  132. return 0;
  133. }
  134. static int msm_ofdata_to_platdata(struct udevice *dev)
  135. {
  136. struct udevice *parent = dev->parent;
  137. struct msm_sdhc *priv = dev_get_priv(dev);
  138. struct sdhci_host *host = &priv->host;
  139. int node = dev_of_offset(dev);
  140. host->name = strdup(dev->name);
  141. host->ioaddr = dev_read_addr_ptr(dev);
  142. host->bus_width = fdtdec_get_int(gd->fdt_blob, node, "bus-width", 4);
  143. host->index = fdtdec_get_uint(gd->fdt_blob, node, "index", 0);
  144. priv->base = (void *)fdtdec_get_addr_size_auto_parent(gd->fdt_blob,
  145. dev_of_offset(parent), node, "reg", 1, NULL, false);
  146. if (priv->base == (void *)FDT_ADDR_T_NONE ||
  147. host->ioaddr == (void *)FDT_ADDR_T_NONE)
  148. return -EINVAL;
  149. return 0;
  150. }
  151. static int msm_sdc_bind(struct udevice *dev)
  152. {
  153. struct msm_sdhc_plat *plat = dev_get_platdata(dev);
  154. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  155. }
  156. static const struct udevice_id msm_mmc_ids[] = {
  157. { .compatible = "qcom,sdhci-msm-v4" },
  158. { }
  159. };
  160. U_BOOT_DRIVER(msm_sdc_drv) = {
  161. .name = "msm_sdc",
  162. .id = UCLASS_MMC,
  163. .of_match = msm_mmc_ids,
  164. .ofdata_to_platdata = msm_ofdata_to_platdata,
  165. .ops = &sdhci_ops,
  166. .bind = msm_sdc_bind,
  167. .probe = msm_sdc_probe,
  168. .remove = msm_sdc_remove,
  169. .priv_auto_alloc_size = sizeof(struct msm_sdhc),
  170. .platdata_auto_alloc_size = sizeof(struct msm_sdhc_plat),
  171. };