jz_mmc.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Ingenic JZ MMC driver
  4. *
  5. * Copyright (c) 2013 Imagination Technologies
  6. * Author: Paul Burton <paul.burton@imgtec.com>
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <mmc.h>
  11. #include <asm/io.h>
  12. #include <asm/unaligned.h>
  13. #include <errno.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/bitops.h>
  16. #include <linux/delay.h>
  17. #include <mach/jz4780.h>
  18. #include <wait_bit.h>
  19. /* Registers */
  20. #define MSC_STRPCL 0x000
  21. #define MSC_STAT 0x004
  22. #define MSC_CLKRT 0x008
  23. #define MSC_CMDAT 0x00c
  24. #define MSC_RESTO 0x010
  25. #define MSC_RDTO 0x014
  26. #define MSC_BLKLEN 0x018
  27. #define MSC_NOB 0x01c
  28. #define MSC_SNOB 0x020
  29. #define MSC_IMASK 0x024
  30. #define MSC_IREG 0x028
  31. #define MSC_CMD 0x02c
  32. #define MSC_ARG 0x030
  33. #define MSC_RES 0x034
  34. #define MSC_RXFIFO 0x038
  35. #define MSC_TXFIFO 0x03c
  36. #define MSC_LPM 0x040
  37. #define MSC_DMAC 0x044
  38. #define MSC_DMANDA 0x048
  39. #define MSC_DMADA 0x04c
  40. #define MSC_DMALEN 0x050
  41. #define MSC_DMACMD 0x054
  42. #define MSC_CTRL2 0x058
  43. #define MSC_RTCNT 0x05c
  44. #define MSC_DBG 0x0fc
  45. /* MSC Clock and Control Register (MSC_STRPCL) */
  46. #define MSC_STRPCL_EXIT_MULTIPLE BIT(7)
  47. #define MSC_STRPCL_EXIT_TRANSFER BIT(6)
  48. #define MSC_STRPCL_START_READWAIT BIT(5)
  49. #define MSC_STRPCL_STOP_READWAIT BIT(4)
  50. #define MSC_STRPCL_RESET BIT(3)
  51. #define MSC_STRPCL_START_OP BIT(2)
  52. #define MSC_STRPCL_CLOCK_CONTROL_STOP BIT(0)
  53. #define MSC_STRPCL_CLOCK_CONTROL_START BIT(1)
  54. /* MSC Status Register (MSC_STAT) */
  55. #define MSC_STAT_AUTO_CMD_DONE BIT(31)
  56. #define MSC_STAT_IS_RESETTING BIT(15)
  57. #define MSC_STAT_SDIO_INT_ACTIVE BIT(14)
  58. #define MSC_STAT_PRG_DONE BIT(13)
  59. #define MSC_STAT_DATA_TRAN_DONE BIT(12)
  60. #define MSC_STAT_END_CMD_RES BIT(11)
  61. #define MSC_STAT_DATA_FIFO_AFULL BIT(10)
  62. #define MSC_STAT_IS_READWAIT BIT(9)
  63. #define MSC_STAT_CLK_EN BIT(8)
  64. #define MSC_STAT_DATA_FIFO_FULL BIT(7)
  65. #define MSC_STAT_DATA_FIFO_EMPTY BIT(6)
  66. #define MSC_STAT_CRC_RES_ERR BIT(5)
  67. #define MSC_STAT_CRC_READ_ERROR BIT(4)
  68. #define MSC_STAT_CRC_WRITE_ERROR BIT(2)
  69. #define MSC_STAT_CRC_WRITE_ERROR_NOSTS BIT(4)
  70. #define MSC_STAT_TIME_OUT_RES BIT(1)
  71. #define MSC_STAT_TIME_OUT_READ BIT(0)
  72. /* MSC Bus Clock Control Register (MSC_CLKRT) */
  73. #define MSC_CLKRT_CLK_RATE_MASK 0x7
  74. /* MSC Command Sequence Control Register (MSC_CMDAT) */
  75. #define MSC_CMDAT_IO_ABORT BIT(11)
  76. #define MSC_CMDAT_BUS_WIDTH_1BIT (0x0 << 9)
  77. #define MSC_CMDAT_BUS_WIDTH_4BIT (0x2 << 9)
  78. #define MSC_CMDAT_DMA_EN BIT(8)
  79. #define MSC_CMDAT_INIT BIT(7)
  80. #define MSC_CMDAT_BUSY BIT(6)
  81. #define MSC_CMDAT_STREAM_BLOCK BIT(5)
  82. #define MSC_CMDAT_WRITE BIT(4)
  83. #define MSC_CMDAT_DATA_EN BIT(3)
  84. #define MSC_CMDAT_RESPONSE_MASK (0x7 << 0)
  85. #define MSC_CMDAT_RESPONSE_NONE (0x0 << 0) /* No response */
  86. #define MSC_CMDAT_RESPONSE_R1 (0x1 << 0) /* Format R1 and R1b */
  87. #define MSC_CMDAT_RESPONSE_R2 (0x2 << 0) /* Format R2 */
  88. #define MSC_CMDAT_RESPONSE_R3 (0x3 << 0) /* Format R3 */
  89. #define MSC_CMDAT_RESPONSE_R4 (0x4 << 0) /* Format R4 */
  90. #define MSC_CMDAT_RESPONSE_R5 (0x5 << 0) /* Format R5 */
  91. #define MSC_CMDAT_RESPONSE_R6 (0x6 << 0) /* Format R6 */
  92. /* MSC Interrupts Mask Register (MSC_IMASK) */
  93. #define MSC_IMASK_TIME_OUT_RES BIT(9)
  94. #define MSC_IMASK_TIME_OUT_READ BIT(8)
  95. #define MSC_IMASK_SDIO BIT(7)
  96. #define MSC_IMASK_TXFIFO_WR_REQ BIT(6)
  97. #define MSC_IMASK_RXFIFO_RD_REQ BIT(5)
  98. #define MSC_IMASK_END_CMD_RES BIT(2)
  99. #define MSC_IMASK_PRG_DONE BIT(1)
  100. #define MSC_IMASK_DATA_TRAN_DONE BIT(0)
  101. /* MSC Interrupts Status Register (MSC_IREG) */
  102. #define MSC_IREG_TIME_OUT_RES BIT(9)
  103. #define MSC_IREG_TIME_OUT_READ BIT(8)
  104. #define MSC_IREG_SDIO BIT(7)
  105. #define MSC_IREG_TXFIFO_WR_REQ BIT(6)
  106. #define MSC_IREG_RXFIFO_RD_REQ BIT(5)
  107. #define MSC_IREG_END_CMD_RES BIT(2)
  108. #define MSC_IREG_PRG_DONE BIT(1)
  109. #define MSC_IREG_DATA_TRAN_DONE BIT(0)
  110. struct jz_mmc_plat {
  111. struct mmc_config cfg;
  112. struct mmc mmc;
  113. };
  114. struct jz_mmc_priv {
  115. void __iomem *regs;
  116. u32 flags;
  117. /* priv flags */
  118. #define JZ_MMC_BUS_WIDTH_MASK 0x3
  119. #define JZ_MMC_BUS_WIDTH_1 0x0
  120. #define JZ_MMC_BUS_WIDTH_4 0x2
  121. #define JZ_MMC_BUS_WIDTH_8 0x3
  122. #define JZ_MMC_SENT_INIT BIT(2)
  123. };
  124. static int jz_mmc_clock_rate(void)
  125. {
  126. return 24000000;
  127. }
  128. #if CONFIG_IS_ENABLED(MMC_WRITE)
  129. static inline void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
  130. {
  131. int sz = DIV_ROUND_UP(data->blocks * data->blocksize, 4);
  132. const void *buf = data->src;
  133. while (sz--) {
  134. u32 val = get_unaligned_le32(buf);
  135. wait_for_bit_le32(priv->regs + MSC_IREG,
  136. MSC_IREG_TXFIFO_WR_REQ,
  137. true, 10000, false);
  138. writel(val, priv->regs + MSC_TXFIFO);
  139. buf += 4;
  140. }
  141. }
  142. #else
  143. static void jz_mmc_write_data(struct jz_mmc_priv *priv, struct mmc_data *data)
  144. {}
  145. #endif
  146. static inline int jz_mmc_read_data(struct jz_mmc_priv *priv, struct mmc_data *data)
  147. {
  148. int sz = data->blocks * data->blocksize;
  149. void *buf = data->dest;
  150. u32 stat, val;
  151. do {
  152. stat = readl(priv->regs + MSC_STAT);
  153. if (stat & MSC_STAT_TIME_OUT_READ)
  154. return -ETIMEDOUT;
  155. if (stat & MSC_STAT_CRC_READ_ERROR)
  156. return -EINVAL;
  157. if (stat & MSC_STAT_DATA_FIFO_EMPTY) {
  158. udelay(10);
  159. continue;
  160. }
  161. do {
  162. val = readl(priv->regs + MSC_RXFIFO);
  163. if (sz == 1)
  164. *(u8 *)buf = (u8)val;
  165. else if (sz == 2)
  166. put_unaligned_le16(val, buf);
  167. else if (sz >= 4)
  168. put_unaligned_le32(val, buf);
  169. buf += 4;
  170. sz -= 4;
  171. stat = readl(priv->regs + MSC_STAT);
  172. } while (!(stat & MSC_STAT_DATA_FIFO_EMPTY));
  173. } while (!(stat & MSC_STAT_DATA_TRAN_DONE));
  174. return 0;
  175. }
  176. static int jz_mmc_send_cmd(struct mmc *mmc, struct jz_mmc_priv *priv,
  177. struct mmc_cmd *cmd, struct mmc_data *data)
  178. {
  179. u32 stat, mask, cmdat = 0;
  180. int i, ret;
  181. /* stop the clock */
  182. writel(MSC_STRPCL_CLOCK_CONTROL_STOP, priv->regs + MSC_STRPCL);
  183. ret = wait_for_bit_le32(priv->regs + MSC_STAT,
  184. MSC_STAT_CLK_EN, false, 10000, false);
  185. if (ret)
  186. return ret;
  187. writel(0, priv->regs + MSC_DMAC);
  188. /* setup command */
  189. writel(cmd->cmdidx, priv->regs + MSC_CMD);
  190. writel(cmd->cmdarg, priv->regs + MSC_ARG);
  191. if (data) {
  192. /* setup data */
  193. cmdat |= MSC_CMDAT_DATA_EN;
  194. if (data->flags & MMC_DATA_WRITE)
  195. cmdat |= MSC_CMDAT_WRITE;
  196. writel(data->blocks, priv->regs + MSC_NOB);
  197. writel(data->blocksize, priv->regs + MSC_BLKLEN);
  198. } else {
  199. writel(0, priv->regs + MSC_NOB);
  200. writel(0, priv->regs + MSC_BLKLEN);
  201. }
  202. /* setup response */
  203. switch (cmd->resp_type) {
  204. case MMC_RSP_NONE:
  205. break;
  206. case MMC_RSP_R1:
  207. case MMC_RSP_R1b:
  208. cmdat |= MSC_CMDAT_RESPONSE_R1;
  209. break;
  210. case MMC_RSP_R2:
  211. cmdat |= MSC_CMDAT_RESPONSE_R2;
  212. break;
  213. case MMC_RSP_R3:
  214. cmdat |= MSC_CMDAT_RESPONSE_R3;
  215. break;
  216. default:
  217. break;
  218. }
  219. if (cmd->resp_type & MMC_RSP_BUSY)
  220. cmdat |= MSC_CMDAT_BUSY;
  221. /* set init for the first command only */
  222. if (!(priv->flags & JZ_MMC_SENT_INIT)) {
  223. cmdat |= MSC_CMDAT_INIT;
  224. priv->flags |= JZ_MMC_SENT_INIT;
  225. }
  226. cmdat |= (priv->flags & JZ_MMC_BUS_WIDTH_MASK) << 9;
  227. /* write the data setup */
  228. writel(cmdat, priv->regs + MSC_CMDAT);
  229. /* unmask interrupts */
  230. mask = 0xffffffff & ~(MSC_IMASK_END_CMD_RES | MSC_IMASK_TIME_OUT_RES);
  231. if (data) {
  232. mask &= ~MSC_IMASK_DATA_TRAN_DONE;
  233. if (data->flags & MMC_DATA_WRITE) {
  234. mask &= ~MSC_IMASK_TXFIFO_WR_REQ;
  235. } else {
  236. mask &= ~(MSC_IMASK_RXFIFO_RD_REQ |
  237. MSC_IMASK_TIME_OUT_READ);
  238. }
  239. }
  240. writel(mask, priv->regs + MSC_IMASK);
  241. /* clear interrupts */
  242. writel(0xffffffff, priv->regs + MSC_IREG);
  243. /* start the command (& the clock) */
  244. writel(MSC_STRPCL_START_OP | MSC_STRPCL_CLOCK_CONTROL_START,
  245. priv->regs + MSC_STRPCL);
  246. /* wait for completion */
  247. for (i = 0; i < 100; i++) {
  248. stat = readl(priv->regs + MSC_IREG);
  249. stat &= MSC_IREG_END_CMD_RES | MSC_IREG_TIME_OUT_RES;
  250. if (stat)
  251. break;
  252. mdelay(1);
  253. }
  254. writel(stat, priv->regs + MSC_IREG);
  255. if (stat & MSC_IREG_TIME_OUT_RES)
  256. return -ETIMEDOUT;
  257. if (cmd->resp_type & MMC_RSP_PRESENT) {
  258. /* read the response */
  259. if (cmd->resp_type & MMC_RSP_136) {
  260. u16 a, b, c, i;
  261. a = readw(priv->regs + MSC_RES);
  262. for (i = 0; i < 4; i++) {
  263. b = readw(priv->regs + MSC_RES);
  264. c = readw(priv->regs + MSC_RES);
  265. cmd->response[i] =
  266. (a << 24) | (b << 8) | (c >> 8);
  267. a = c;
  268. }
  269. } else {
  270. cmd->response[0] = readw(priv->regs + MSC_RES) << 24;
  271. cmd->response[0] |= readw(priv->regs + MSC_RES) << 8;
  272. cmd->response[0] |= readw(priv->regs + MSC_RES) & 0xff;
  273. }
  274. }
  275. if (data) {
  276. if (data->flags & MMC_DATA_WRITE)
  277. jz_mmc_write_data(priv, data);
  278. else if (data->flags & MMC_DATA_READ) {
  279. ret = jz_mmc_read_data(priv, data);
  280. if (ret)
  281. return ret;
  282. }
  283. }
  284. return 0;
  285. }
  286. static int jz_mmc_set_ios(struct mmc *mmc, struct jz_mmc_priv *priv)
  287. {
  288. u32 real_rate = jz_mmc_clock_rate();
  289. u8 clk_div = 0;
  290. /* calculate clock divide */
  291. while ((real_rate > mmc->clock) && (clk_div < 7)) {
  292. real_rate >>= 1;
  293. clk_div++;
  294. }
  295. writel(clk_div & MSC_CLKRT_CLK_RATE_MASK, priv->regs + MSC_CLKRT);
  296. /* set the bus width for the next command */
  297. priv->flags &= ~JZ_MMC_BUS_WIDTH_MASK;
  298. if (mmc->bus_width == 8)
  299. priv->flags |= JZ_MMC_BUS_WIDTH_8;
  300. else if (mmc->bus_width == 4)
  301. priv->flags |= JZ_MMC_BUS_WIDTH_4;
  302. else
  303. priv->flags |= JZ_MMC_BUS_WIDTH_1;
  304. return 0;
  305. }
  306. static int jz_mmc_core_init(struct mmc *mmc)
  307. {
  308. struct jz_mmc_priv *priv = mmc->priv;
  309. int ret;
  310. /* Reset */
  311. writel(MSC_STRPCL_RESET, priv->regs + MSC_STRPCL);
  312. ret = wait_for_bit_le32(priv->regs + MSC_STAT,
  313. MSC_STAT_IS_RESETTING, false, 10000, false);
  314. if (ret)
  315. return ret;
  316. /* Maximum timeouts */
  317. writel(0xffff, priv->regs + MSC_RESTO);
  318. writel(0xffffffff, priv->regs + MSC_RDTO);
  319. /* Enable low power mode */
  320. writel(0x1, priv->regs + MSC_LPM);
  321. return 0;
  322. }
  323. #if !CONFIG_IS_ENABLED(DM_MMC)
  324. static int jz_mmc_legacy_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  325. struct mmc_data *data)
  326. {
  327. struct jz_mmc_priv *priv = mmc->priv;
  328. return jz_mmc_send_cmd(mmc, priv, cmd, data);
  329. }
  330. static int jz_mmc_legacy_set_ios(struct mmc *mmc)
  331. {
  332. struct jz_mmc_priv *priv = mmc->priv;
  333. return jz_mmc_set_ios(mmc, priv);
  334. };
  335. static const struct mmc_ops jz_msc_ops = {
  336. .send_cmd = jz_mmc_legacy_send_cmd,
  337. .set_ios = jz_mmc_legacy_set_ios,
  338. .init = jz_mmc_core_init,
  339. };
  340. static struct jz_mmc_priv jz_mmc_priv_static;
  341. static struct jz_mmc_plat jz_mmc_plat_static = {
  342. .cfg = {
  343. .name = "MSC",
  344. .ops = &jz_msc_ops,
  345. .voltages = MMC_VDD_27_28 | MMC_VDD_28_29 | MMC_VDD_29_30 |
  346. MMC_VDD_30_31 | MMC_VDD_31_32 | MMC_VDD_32_33 |
  347. MMC_VDD_33_34 | MMC_VDD_34_35 | MMC_VDD_35_36,
  348. .host_caps = MMC_MODE_4BIT | MMC_MODE_HS_52MHz | MMC_MODE_HS,
  349. .f_min = 375000,
  350. .f_max = 48000000,
  351. .b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT,
  352. },
  353. };
  354. int jz_mmc_init(void __iomem *base)
  355. {
  356. struct mmc *mmc;
  357. jz_mmc_priv_static.regs = base;
  358. mmc = mmc_create(&jz_mmc_plat_static.cfg, &jz_mmc_priv_static);
  359. return mmc ? 0 : -ENODEV;
  360. }
  361. #else /* CONFIG_DM_MMC */
  362. #include <dm.h>
  363. DECLARE_GLOBAL_DATA_PTR;
  364. static int jz_mmc_dm_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  365. struct mmc_data *data)
  366. {
  367. struct jz_mmc_priv *priv = dev_get_priv(dev);
  368. struct mmc *mmc = mmc_get_mmc_dev(dev);
  369. return jz_mmc_send_cmd(mmc, priv, cmd, data);
  370. }
  371. static int jz_mmc_dm_set_ios(struct udevice *dev)
  372. {
  373. struct jz_mmc_priv *priv = dev_get_priv(dev);
  374. struct mmc *mmc = mmc_get_mmc_dev(dev);
  375. return jz_mmc_set_ios(mmc, priv);
  376. };
  377. static const struct dm_mmc_ops jz_msc_ops = {
  378. .send_cmd = jz_mmc_dm_send_cmd,
  379. .set_ios = jz_mmc_dm_set_ios,
  380. };
  381. static int jz_mmc_ofdata_to_platdata(struct udevice *dev)
  382. {
  383. struct jz_mmc_priv *priv = dev_get_priv(dev);
  384. struct jz_mmc_plat *plat = dev_get_platdata(dev);
  385. struct mmc_config *cfg;
  386. int ret;
  387. priv->regs = map_physmem(dev_read_addr(dev), 0x100, MAP_NOCACHE);
  388. cfg = &plat->cfg;
  389. cfg->name = "MSC";
  390. cfg->host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS;
  391. ret = mmc_of_parse(dev, cfg);
  392. if (ret < 0) {
  393. dev_err(dev, "failed to parse host caps\n");
  394. return ret;
  395. }
  396. cfg->f_min = 400000;
  397. cfg->f_max = 52000000;
  398. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
  399. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  400. return 0;
  401. }
  402. static int jz_mmc_bind(struct udevice *dev)
  403. {
  404. struct jz_mmc_plat *plat = dev_get_platdata(dev);
  405. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  406. }
  407. static int jz_mmc_probe(struct udevice *dev)
  408. {
  409. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  410. struct jz_mmc_priv *priv = dev_get_priv(dev);
  411. struct jz_mmc_plat *plat = dev_get_platdata(dev);
  412. plat->mmc.priv = priv;
  413. upriv->mmc = &plat->mmc;
  414. return jz_mmc_core_init(&plat->mmc);
  415. }
  416. static const struct udevice_id jz_mmc_ids[] = {
  417. { .compatible = "ingenic,jz4780-mmc" },
  418. { }
  419. };
  420. U_BOOT_DRIVER(jz_mmc_drv) = {
  421. .name = "jz_mmc",
  422. .id = UCLASS_MMC,
  423. .of_match = jz_mmc_ids,
  424. .ofdata_to_platdata = jz_mmc_ofdata_to_platdata,
  425. .bind = jz_mmc_bind,
  426. .probe = jz_mmc_probe,
  427. .priv_auto_alloc_size = sizeof(struct jz_mmc_priv),
  428. .platdata_auto_alloc_size = sizeof(struct jz_mmc_plat),
  429. .ops = &jz_msc_ops,
  430. };
  431. #endif /* CONFIG_DM_MMC */