fsl_esdhc_imx.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc
  4. * Copyright 2019 NXP Semiconductors
  5. * Andy Fleming
  6. * Yangbo Lu <yangbo.lu@nxp.com>
  7. *
  8. * Based vaguely on the pxa mmc code:
  9. * (C) Copyright 2003
  10. * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
  11. */
  12. #include <config.h>
  13. #include <common.h>
  14. #include <command.h>
  15. #include <clk.h>
  16. #include <cpu_func.h>
  17. #include <errno.h>
  18. #include <hwconfig.h>
  19. #include <log.h>
  20. #include <mmc.h>
  21. #include <part.h>
  22. #include <asm/cache.h>
  23. #include <dm/device_compat.h>
  24. #include <linux/bitops.h>
  25. #include <linux/delay.h>
  26. #include <linux/err.h>
  27. #include <power/regulator.h>
  28. #include <malloc.h>
  29. #include <fsl_esdhc_imx.h>
  30. #include <fdt_support.h>
  31. #include <asm/io.h>
  32. #include <dm.h>
  33. #include <asm-generic/gpio.h>
  34. #include <dm/pinctrl.h>
  35. #include <dt-structs.h>
  36. #include <mapmem.h>
  37. #include <dm/ofnode.h>
  38. #include <linux/iopoll.h>
  39. #if !CONFIG_IS_ENABLED(BLK)
  40. #include "mmc_private.h"
  41. #endif
  42. DECLARE_GLOBAL_DATA_PTR;
  43. #define SDHCI_IRQ_EN_BITS (IRQSTATEN_CC | IRQSTATEN_TC | \
  44. IRQSTATEN_CINT | \
  45. IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
  46. IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | \
  47. IRQSTATEN_DEBE | IRQSTATEN_BRR | IRQSTATEN_BWR | \
  48. IRQSTATEN_DINT)
  49. #define MAX_TUNING_LOOP 40
  50. #define ESDHC_DRIVER_STAGE_VALUE 0xffffffff
  51. struct fsl_esdhc {
  52. uint dsaddr; /* SDMA system address register */
  53. uint blkattr; /* Block attributes register */
  54. uint cmdarg; /* Command argument register */
  55. uint xfertyp; /* Transfer type register */
  56. uint cmdrsp0; /* Command response 0 register */
  57. uint cmdrsp1; /* Command response 1 register */
  58. uint cmdrsp2; /* Command response 2 register */
  59. uint cmdrsp3; /* Command response 3 register */
  60. uint datport; /* Buffer data port register */
  61. uint prsstat; /* Present state register */
  62. uint proctl; /* Protocol control register */
  63. uint sysctl; /* System Control Register */
  64. uint irqstat; /* Interrupt status register */
  65. uint irqstaten; /* Interrupt status enable register */
  66. uint irqsigen; /* Interrupt signal enable register */
  67. uint autoc12err; /* Auto CMD error status register */
  68. uint hostcapblt; /* Host controller capabilities register */
  69. uint wml; /* Watermark level register */
  70. uint mixctrl; /* For USDHC */
  71. char reserved1[4]; /* reserved */
  72. uint fevt; /* Force event register */
  73. uint admaes; /* ADMA error status register */
  74. uint adsaddr; /* ADMA system address register */
  75. char reserved2[4];
  76. uint dllctrl;
  77. uint dllstat;
  78. uint clktunectrlstatus;
  79. char reserved3[4];
  80. uint strobe_dllctrl;
  81. uint strobe_dllstat;
  82. char reserved4[72];
  83. uint vendorspec;
  84. uint mmcboot;
  85. uint vendorspec2;
  86. uint tuning_ctrl; /* on i.MX6/7/8/RT */
  87. char reserved5[44];
  88. uint hostver; /* Host controller version register */
  89. char reserved6[4]; /* reserved */
  90. uint dmaerraddr; /* DMA error address register */
  91. char reserved7[4]; /* reserved */
  92. uint dmaerrattr; /* DMA error attribute register */
  93. char reserved8[4]; /* reserved */
  94. uint hostcapblt2; /* Host controller capabilities register 2 */
  95. char reserved9[8]; /* reserved */
  96. uint tcr; /* Tuning control register */
  97. char reserved10[28]; /* reserved */
  98. uint sddirctl; /* SD direction control register */
  99. char reserved11[712];/* reserved */
  100. uint scr; /* eSDHC control register */
  101. };
  102. struct fsl_esdhc_plat {
  103. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  104. /* Put this first since driver model will copy the data here */
  105. struct dtd_fsl_esdhc dtplat;
  106. #endif
  107. struct mmc_config cfg;
  108. struct mmc mmc;
  109. };
  110. struct esdhc_soc_data {
  111. u32 flags;
  112. };
  113. /**
  114. * struct fsl_esdhc_priv
  115. *
  116. * @esdhc_regs: registers of the sdhc controller
  117. * @sdhc_clk: Current clk of the sdhc controller
  118. * @bus_width: bus width, 1bit, 4bit or 8bit
  119. * @cfg: mmc config
  120. * @mmc: mmc
  121. * Following is used when Driver Model is enabled for MMC
  122. * @dev: pointer for the device
  123. * @non_removable: 0: removable; 1: non-removable
  124. * @broken_cd: 0: use GPIO for card detect; 1: Do not use GPIO for card detect
  125. * @wp_enable: 1: enable checking wp; 0: no check
  126. * @vs18_enable: 1: use 1.8V voltage; 0: use 3.3V
  127. * @flags: ESDHC_FLAG_xx in include/fsl_esdhc_imx.h
  128. * @caps: controller capabilities
  129. * @tuning_step: tuning step setting in tuning_ctrl register
  130. * @start_tuning_tap: the start point for tuning in tuning_ctrl register
  131. * @strobe_dll_delay_target: settings in strobe_dllctrl
  132. * @signal_voltage: indicating the current voltage
  133. * @cd_gpio: gpio for card detection
  134. * @wp_gpio: gpio for write protection
  135. */
  136. struct fsl_esdhc_priv {
  137. struct fsl_esdhc *esdhc_regs;
  138. unsigned int sdhc_clk;
  139. struct clk per_clk;
  140. unsigned int clock;
  141. unsigned int mode;
  142. unsigned int bus_width;
  143. #if !CONFIG_IS_ENABLED(BLK)
  144. struct mmc *mmc;
  145. #endif
  146. struct udevice *dev;
  147. int non_removable;
  148. int broken_cd;
  149. int wp_enable;
  150. int vs18_enable;
  151. u32 flags;
  152. u32 caps;
  153. u32 tuning_step;
  154. u32 tuning_start_tap;
  155. u32 strobe_dll_delay_target;
  156. u32 signal_voltage;
  157. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  158. struct udevice *vqmmc_dev;
  159. struct udevice *vmmc_dev;
  160. #endif
  161. #if CONFIG_IS_ENABLED(DM_GPIO)
  162. struct gpio_desc cd_gpio;
  163. struct gpio_desc wp_gpio;
  164. #endif
  165. };
  166. /* Return the XFERTYP flags for a given command and data packet */
  167. static uint esdhc_xfertyp(struct mmc_cmd *cmd, struct mmc_data *data)
  168. {
  169. uint xfertyp = 0;
  170. if (data) {
  171. xfertyp |= XFERTYP_DPSEL;
  172. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  173. xfertyp |= XFERTYP_DMAEN;
  174. #endif
  175. if (data->blocks > 1) {
  176. xfertyp |= XFERTYP_MSBSEL;
  177. xfertyp |= XFERTYP_BCEN;
  178. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  179. xfertyp |= XFERTYP_AC12EN;
  180. #endif
  181. }
  182. if (data->flags & MMC_DATA_READ)
  183. xfertyp |= XFERTYP_DTDSEL;
  184. }
  185. if (cmd->resp_type & MMC_RSP_CRC)
  186. xfertyp |= XFERTYP_CCCEN;
  187. if (cmd->resp_type & MMC_RSP_OPCODE)
  188. xfertyp |= XFERTYP_CICEN;
  189. if (cmd->resp_type & MMC_RSP_136)
  190. xfertyp |= XFERTYP_RSPTYP_136;
  191. else if (cmd->resp_type & MMC_RSP_BUSY)
  192. xfertyp |= XFERTYP_RSPTYP_48_BUSY;
  193. else if (cmd->resp_type & MMC_RSP_PRESENT)
  194. xfertyp |= XFERTYP_RSPTYP_48;
  195. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  196. xfertyp |= XFERTYP_CMDTYP_ABORT;
  197. return XFERTYP_CMD(cmd->cmdidx) | xfertyp;
  198. }
  199. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  200. /*
  201. * PIO Read/Write Mode reduce the performace as DMA is not used in this mode.
  202. */
  203. static void esdhc_pio_read_write(struct fsl_esdhc_priv *priv,
  204. struct mmc_data *data)
  205. {
  206. struct fsl_esdhc *regs = priv->esdhc_regs;
  207. uint blocks;
  208. char *buffer;
  209. uint databuf;
  210. uint size;
  211. uint irqstat;
  212. ulong start;
  213. if (data->flags & MMC_DATA_READ) {
  214. blocks = data->blocks;
  215. buffer = data->dest;
  216. while (blocks) {
  217. start = get_timer(0);
  218. size = data->blocksize;
  219. irqstat = esdhc_read32(&regs->irqstat);
  220. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BREN)) {
  221. if (get_timer(start) > PIO_TIMEOUT) {
  222. printf("\nData Read Failed in PIO Mode.");
  223. return;
  224. }
  225. }
  226. while (size && (!(irqstat & IRQSTAT_TC))) {
  227. udelay(100); /* Wait before last byte transfer complete */
  228. irqstat = esdhc_read32(&regs->irqstat);
  229. databuf = in_le32(&regs->datport);
  230. *((uint *)buffer) = databuf;
  231. buffer += 4;
  232. size -= 4;
  233. }
  234. blocks--;
  235. }
  236. } else {
  237. blocks = data->blocks;
  238. buffer = (char *)data->src;
  239. while (blocks) {
  240. start = get_timer(0);
  241. size = data->blocksize;
  242. irqstat = esdhc_read32(&regs->irqstat);
  243. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_BWEN)) {
  244. if (get_timer(start) > PIO_TIMEOUT) {
  245. printf("\nData Write Failed in PIO Mode.");
  246. return;
  247. }
  248. }
  249. while (size && (!(irqstat & IRQSTAT_TC))) {
  250. udelay(100); /* Wait before last byte transfer complete */
  251. databuf = *((uint *)buffer);
  252. buffer += 4;
  253. size -= 4;
  254. irqstat = esdhc_read32(&regs->irqstat);
  255. out_le32(&regs->datport, databuf);
  256. }
  257. blocks--;
  258. }
  259. }
  260. }
  261. #endif
  262. static int esdhc_setup_data(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  263. struct mmc_data *data)
  264. {
  265. int timeout;
  266. struct fsl_esdhc *regs = priv->esdhc_regs;
  267. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  268. dma_addr_t addr;
  269. #endif
  270. uint wml_value;
  271. wml_value = data->blocksize/4;
  272. if (data->flags & MMC_DATA_READ) {
  273. if (wml_value > WML_RD_WML_MAX)
  274. wml_value = WML_RD_WML_MAX_VAL;
  275. esdhc_clrsetbits32(&regs->wml, WML_RD_WML_MASK, wml_value);
  276. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  277. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  278. addr = virt_to_phys((void *)(data->dest));
  279. if (upper_32_bits(addr))
  280. printf("Error found for upper 32 bits\n");
  281. else
  282. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  283. #else
  284. esdhc_write32(&regs->dsaddr, (u32)data->dest);
  285. #endif
  286. #endif
  287. } else {
  288. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  289. flush_dcache_range((ulong)data->src,
  290. (ulong)data->src+data->blocks
  291. *data->blocksize);
  292. #endif
  293. if (wml_value > WML_WR_WML_MAX)
  294. wml_value = WML_WR_WML_MAX_VAL;
  295. if (priv->wp_enable) {
  296. if ((esdhc_read32(&regs->prsstat) &
  297. PRSSTAT_WPSPL) == 0) {
  298. printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
  299. return -ETIMEDOUT;
  300. }
  301. } else {
  302. #if CONFIG_IS_ENABLED(DM_GPIO)
  303. if (dm_gpio_is_valid(&priv->wp_gpio) &&
  304. dm_gpio_get_value(&priv->wp_gpio)) {
  305. printf("\nThe SD card is locked. Can not write to a locked card.\n\n");
  306. return -ETIMEDOUT;
  307. }
  308. #endif
  309. }
  310. esdhc_clrsetbits32(&regs->wml, WML_WR_WML_MASK,
  311. wml_value << 16);
  312. #ifndef CONFIG_SYS_FSL_ESDHC_USE_PIO
  313. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  314. addr = virt_to_phys((void *)(data->src));
  315. if (upper_32_bits(addr))
  316. printf("Error found for upper 32 bits\n");
  317. else
  318. esdhc_write32(&regs->dsaddr, lower_32_bits(addr));
  319. #else
  320. esdhc_write32(&regs->dsaddr, (u32)data->src);
  321. #endif
  322. #endif
  323. }
  324. esdhc_write32(&regs->blkattr, data->blocks << 16 | data->blocksize);
  325. /* Calculate the timeout period for data transactions */
  326. /*
  327. * 1)Timeout period = (2^(timeout+13)) SD Clock cycles
  328. * 2)Timeout period should be minimum 0.250sec as per SD Card spec
  329. * So, Number of SD Clock cycles for 0.25sec should be minimum
  330. * (SD Clock/sec * 0.25 sec) SD Clock cycles
  331. * = (mmc->clock * 1/4) SD Clock cycles
  332. * As 1) >= 2)
  333. * => (2^(timeout+13)) >= mmc->clock * 1/4
  334. * Taking log2 both the sides
  335. * => timeout + 13 >= log2(mmc->clock/4)
  336. * Rounding up to next power of 2
  337. * => timeout + 13 = log2(mmc->clock/4) + 1
  338. * => timeout + 13 = fls(mmc->clock/4)
  339. *
  340. * However, the MMC spec "It is strongly recommended for hosts to
  341. * implement more than 500ms timeout value even if the card
  342. * indicates the 250ms maximum busy length." Even the previous
  343. * value of 300ms is known to be insufficient for some cards.
  344. * So, we use
  345. * => timeout + 13 = fls(mmc->clock/2)
  346. */
  347. timeout = fls(mmc->clock/2);
  348. timeout -= 13;
  349. if (timeout > 14)
  350. timeout = 14;
  351. if (timeout < 0)
  352. timeout = 0;
  353. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC_A001
  354. if ((timeout == 4) || (timeout == 8) || (timeout == 12))
  355. timeout++;
  356. #endif
  357. #ifdef ESDHCI_QUIRK_BROKEN_TIMEOUT_VALUE
  358. timeout = 0xE;
  359. #endif
  360. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, timeout << 16);
  361. return 0;
  362. }
  363. static void check_and_invalidate_dcache_range
  364. (struct mmc_cmd *cmd,
  365. struct mmc_data *data) {
  366. unsigned start = 0;
  367. unsigned end = 0;
  368. unsigned size = roundup(ARCH_DMA_MINALIGN,
  369. data->blocks*data->blocksize);
  370. #if defined(CONFIG_S32V234) || defined(CONFIG_IMX8) || defined(CONFIG_IMX8M)
  371. dma_addr_t addr;
  372. addr = virt_to_phys((void *)(data->dest));
  373. if (upper_32_bits(addr))
  374. printf("Error found for upper 32 bits\n");
  375. else
  376. start = lower_32_bits(addr);
  377. #else
  378. start = (unsigned)data->dest;
  379. #endif
  380. end = start + size;
  381. invalidate_dcache_range(start, end);
  382. }
  383. #ifdef CONFIG_MCF5441x
  384. /*
  385. * Swaps 32-bit words to little-endian byte order.
  386. */
  387. static inline void sd_swap_dma_buff(struct mmc_data *data)
  388. {
  389. int i, size = data->blocksize >> 2;
  390. u32 *buffer = (u32 *)data->dest;
  391. u32 sw;
  392. while (data->blocks--) {
  393. for (i = 0; i < size; i++) {
  394. sw = __sw32(*buffer);
  395. *buffer++ = sw;
  396. }
  397. }
  398. }
  399. #endif
  400. /*
  401. * Sends a command out on the bus. Takes the mmc pointer,
  402. * a command pointer, and an optional data pointer.
  403. */
  404. static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
  405. struct mmc_cmd *cmd, struct mmc_data *data)
  406. {
  407. int err = 0;
  408. uint xfertyp;
  409. uint irqstat;
  410. u32 flags = IRQSTAT_CC | IRQSTAT_CTOE;
  411. struct fsl_esdhc *regs = priv->esdhc_regs;
  412. unsigned long start;
  413. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC111
  414. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION)
  415. return 0;
  416. #endif
  417. esdhc_write32(&regs->irqstat, -1);
  418. sync();
  419. /* Wait for the bus to be idle */
  420. while ((esdhc_read32(&regs->prsstat) & PRSSTAT_CICHB) ||
  421. (esdhc_read32(&regs->prsstat) & PRSSTAT_CIDHB))
  422. ;
  423. while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
  424. ;
  425. /* Wait at least 8 SD clock cycles before the next command */
  426. /*
  427. * Note: This is way more than 8 cycles, but 1ms seems to
  428. * resolve timing issues with some cards
  429. */
  430. udelay(1000);
  431. /* Set up for a data transfer if we have one */
  432. if (data) {
  433. err = esdhc_setup_data(priv, mmc, data);
  434. if(err)
  435. return err;
  436. if (data->flags & MMC_DATA_READ)
  437. check_and_invalidate_dcache_range(cmd, data);
  438. }
  439. /* Figure out the transfer arguments */
  440. xfertyp = esdhc_xfertyp(cmd, data);
  441. /* Mask all irqs */
  442. esdhc_write32(&regs->irqsigen, 0);
  443. /* Send the command */
  444. esdhc_write32(&regs->cmdarg, cmd->cmdarg);
  445. #if defined(CONFIG_FSL_USDHC)
  446. esdhc_write32(&regs->mixctrl,
  447. (esdhc_read32(&regs->mixctrl) & 0xFFFFFF80) | (xfertyp & 0x7F)
  448. | (mmc->ddr_mode ? XFERTYP_DDREN : 0));
  449. esdhc_write32(&regs->xfertyp, xfertyp & 0xFFFF0000);
  450. #else
  451. esdhc_write32(&regs->xfertyp, xfertyp);
  452. #endif
  453. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
  454. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200))
  455. flags = IRQSTAT_BRR;
  456. /* Wait for the command to complete */
  457. start = get_timer(0);
  458. while (!(esdhc_read32(&regs->irqstat) & flags)) {
  459. if (get_timer(start) > 1000) {
  460. err = -ETIMEDOUT;
  461. goto out;
  462. }
  463. }
  464. irqstat = esdhc_read32(&regs->irqstat);
  465. if (irqstat & CMD_ERR) {
  466. err = -ECOMM;
  467. goto out;
  468. }
  469. if (irqstat & IRQSTAT_CTOE) {
  470. err = -ETIMEDOUT;
  471. goto out;
  472. }
  473. /* Switch voltage to 1.8V if CMD11 succeeded */
  474. if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V) {
  475. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  476. printf("Run CMD11 1.8V switch\n");
  477. /* Sleep for 5 ms - max time for card to switch to 1.8V */
  478. udelay(5000);
  479. }
  480. /* Workaround for ESDHC errata ENGcm03648 */
  481. if (!data && (cmd->resp_type & MMC_RSP_BUSY)) {
  482. int timeout = 50000;
  483. /* Poll on DATA0 line for cmd with busy signal for 5000 ms */
  484. while (timeout > 0 && !(esdhc_read32(&regs->prsstat) &
  485. PRSSTAT_DAT0)) {
  486. udelay(100);
  487. timeout--;
  488. }
  489. if (timeout <= 0) {
  490. printf("Timeout waiting for DAT0 to go high!\n");
  491. err = -ETIMEDOUT;
  492. goto out;
  493. }
  494. }
  495. /* Copy the response to the response buffer */
  496. if (cmd->resp_type & MMC_RSP_136) {
  497. u32 cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
  498. cmdrsp3 = esdhc_read32(&regs->cmdrsp3);
  499. cmdrsp2 = esdhc_read32(&regs->cmdrsp2);
  500. cmdrsp1 = esdhc_read32(&regs->cmdrsp1);
  501. cmdrsp0 = esdhc_read32(&regs->cmdrsp0);
  502. cmd->response[0] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
  503. cmd->response[1] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
  504. cmd->response[2] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
  505. cmd->response[3] = (cmdrsp0 << 8);
  506. } else
  507. cmd->response[0] = esdhc_read32(&regs->cmdrsp0);
  508. /* Wait until all of the blocks are transferred */
  509. if (data) {
  510. #ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
  511. esdhc_pio_read_write(priv, data);
  512. #else
  513. flags = DATA_COMPLETE;
  514. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK) ||
  515. (cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)) {
  516. flags = IRQSTAT_BRR;
  517. }
  518. do {
  519. irqstat = esdhc_read32(&regs->irqstat);
  520. if (irqstat & IRQSTAT_DTOE) {
  521. err = -ETIMEDOUT;
  522. goto out;
  523. }
  524. if (irqstat & DATA_ERR) {
  525. err = -ECOMM;
  526. goto out;
  527. }
  528. } while ((irqstat & flags) != flags);
  529. /*
  530. * Need invalidate the dcache here again to avoid any
  531. * cache-fill during the DMA operations such as the
  532. * speculative pre-fetching etc.
  533. */
  534. if (data->flags & MMC_DATA_READ) {
  535. check_and_invalidate_dcache_range(cmd, data);
  536. #ifdef CONFIG_MCF5441x
  537. sd_swap_dma_buff(data);
  538. #endif
  539. }
  540. #endif
  541. }
  542. out:
  543. /* Reset CMD and DATA portions on error */
  544. if (err) {
  545. esdhc_write32(&regs->sysctl, esdhc_read32(&regs->sysctl) |
  546. SYSCTL_RSTC);
  547. while (esdhc_read32(&regs->sysctl) & SYSCTL_RSTC)
  548. ;
  549. if (data) {
  550. esdhc_write32(&regs->sysctl,
  551. esdhc_read32(&regs->sysctl) |
  552. SYSCTL_RSTD);
  553. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTD))
  554. ;
  555. }
  556. /* If this was CMD11, then notify that power cycle is needed */
  557. if (cmd->cmdidx == SD_CMD_SWITCH_UHS18V)
  558. printf("CMD11 to switch to 1.8V mode failed, card requires power cycle.\n");
  559. }
  560. esdhc_write32(&regs->irqstat, -1);
  561. return err;
  562. }
  563. static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock)
  564. {
  565. struct fsl_esdhc *regs = priv->esdhc_regs;
  566. int div = 1;
  567. u32 tmp;
  568. int ret;
  569. #ifdef ARCH_MXC
  570. #ifdef CONFIG_MX53
  571. /* For i.MX53 eSDHCv3, SYSCTL.SDCLKFS may not be set to 0. */
  572. int pre_div = (regs == (struct fsl_esdhc *)MMC_SDHC3_BASE_ADDR) ? 2 : 1;
  573. #else
  574. int pre_div = 1;
  575. #endif
  576. #else
  577. int pre_div = 2;
  578. #endif
  579. int ddr_pre_div = mmc->ddr_mode ? 2 : 1;
  580. int sdhc_clk = priv->sdhc_clk;
  581. uint clk;
  582. while (sdhc_clk / (16 * pre_div * ddr_pre_div) > clock && pre_div < 256)
  583. pre_div *= 2;
  584. while (sdhc_clk / (div * pre_div * ddr_pre_div) > clock && div < 16)
  585. div++;
  586. pre_div >>= 1;
  587. div -= 1;
  588. clk = (pre_div << 8) | (div << 4);
  589. #ifdef CONFIG_FSL_USDHC
  590. esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
  591. #else
  592. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  593. #endif
  594. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_CLOCK_MASK, clk);
  595. ret = readx_poll_timeout(esdhc_read32, &regs->prsstat, tmp, tmp & PRSSTAT_SDSTB, 100);
  596. if (ret)
  597. pr_warn("fsl_esdhc_imx: Internal clock never stabilised.\n");
  598. #ifdef CONFIG_FSL_USDHC
  599. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN | VENDORSPEC_CKEN);
  600. #else
  601. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  602. #endif
  603. priv->clock = clock;
  604. }
  605. #ifdef MMC_SUPPORTS_TUNING
  606. static int esdhc_change_pinstate(struct udevice *dev)
  607. {
  608. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  609. int ret;
  610. switch (priv->mode) {
  611. case UHS_SDR50:
  612. case UHS_DDR50:
  613. ret = pinctrl_select_state(dev, "state_100mhz");
  614. break;
  615. case UHS_SDR104:
  616. case MMC_HS_200:
  617. case MMC_HS_400:
  618. case MMC_HS_400_ES:
  619. ret = pinctrl_select_state(dev, "state_200mhz");
  620. break;
  621. default:
  622. ret = pinctrl_select_state(dev, "default");
  623. break;
  624. }
  625. if (ret)
  626. printf("%s %d error\n", __func__, priv->mode);
  627. return ret;
  628. }
  629. static void esdhc_reset_tuning(struct mmc *mmc)
  630. {
  631. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  632. struct fsl_esdhc *regs = priv->esdhc_regs;
  633. if (priv->flags & ESDHC_FLAG_USDHC) {
  634. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  635. esdhc_clrbits32(&regs->autoc12err,
  636. MIX_CTRL_SMPCLK_SEL |
  637. MIX_CTRL_EXE_TUNE);
  638. }
  639. }
  640. }
  641. static void esdhc_set_strobe_dll(struct mmc *mmc)
  642. {
  643. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  644. struct fsl_esdhc *regs = priv->esdhc_regs;
  645. u32 val;
  646. if (priv->clock > ESDHC_STROBE_DLL_CLK_FREQ) {
  647. writel(ESDHC_STROBE_DLL_CTRL_RESET, &regs->strobe_dllctrl);
  648. /*
  649. * enable strobe dll ctrl and adjust the delay target
  650. * for the uSDHC loopback read clock
  651. */
  652. val = ESDHC_STROBE_DLL_CTRL_ENABLE |
  653. (priv->strobe_dll_delay_target <<
  654. ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT);
  655. writel(val, &regs->strobe_dllctrl);
  656. /* wait 1us to make sure strobe dll status register stable */
  657. mdelay(1);
  658. val = readl(&regs->strobe_dllstat);
  659. if (!(val & ESDHC_STROBE_DLL_STS_REF_LOCK))
  660. pr_warn("HS400 strobe DLL status REF not lock!\n");
  661. if (!(val & ESDHC_STROBE_DLL_STS_SLV_LOCK))
  662. pr_warn("HS400 strobe DLL status SLV not lock!\n");
  663. }
  664. }
  665. static int esdhc_set_timing(struct mmc *mmc)
  666. {
  667. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  668. struct fsl_esdhc *regs = priv->esdhc_regs;
  669. u32 mixctrl;
  670. mixctrl = readl(&regs->mixctrl);
  671. mixctrl &= ~(MIX_CTRL_DDREN | MIX_CTRL_HS400_EN);
  672. switch (mmc->selected_mode) {
  673. case MMC_LEGACY:
  674. esdhc_reset_tuning(mmc);
  675. writel(mixctrl, &regs->mixctrl);
  676. break;
  677. case MMC_HS_400:
  678. case MMC_HS_400_ES:
  679. mixctrl |= MIX_CTRL_DDREN | MIX_CTRL_HS400_EN;
  680. writel(mixctrl, &regs->mixctrl);
  681. esdhc_set_strobe_dll(mmc);
  682. break;
  683. case MMC_HS:
  684. case MMC_HS_52:
  685. case MMC_HS_200:
  686. case SD_HS:
  687. case UHS_SDR12:
  688. case UHS_SDR25:
  689. case UHS_SDR50:
  690. case UHS_SDR104:
  691. writel(mixctrl, &regs->mixctrl);
  692. break;
  693. case UHS_DDR50:
  694. case MMC_DDR_52:
  695. mixctrl |= MIX_CTRL_DDREN;
  696. writel(mixctrl, &regs->mixctrl);
  697. break;
  698. default:
  699. printf("Not supported %d\n", mmc->selected_mode);
  700. return -EINVAL;
  701. }
  702. priv->mode = mmc->selected_mode;
  703. return esdhc_change_pinstate(mmc->dev);
  704. }
  705. static int esdhc_set_voltage(struct mmc *mmc)
  706. {
  707. struct fsl_esdhc_priv *priv = dev_get_priv(mmc->dev);
  708. struct fsl_esdhc *regs = priv->esdhc_regs;
  709. int ret;
  710. priv->signal_voltage = mmc->signal_voltage;
  711. switch (mmc->signal_voltage) {
  712. case MMC_SIGNAL_VOLTAGE_330:
  713. if (priv->vs18_enable)
  714. return -ENOTSUPP;
  715. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  716. if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
  717. ret = regulator_set_value(priv->vqmmc_dev, 3300000);
  718. if (ret) {
  719. printf("Setting to 3.3V error");
  720. return -EIO;
  721. }
  722. /* Wait for 5ms */
  723. mdelay(5);
  724. }
  725. #endif
  726. esdhc_clrbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  727. if (!(esdhc_read32(&regs->vendorspec) &
  728. ESDHC_VENDORSPEC_VSELECT))
  729. return 0;
  730. return -EAGAIN;
  731. case MMC_SIGNAL_VOLTAGE_180:
  732. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  733. if (!IS_ERR_OR_NULL(priv->vqmmc_dev)) {
  734. ret = regulator_set_value(priv->vqmmc_dev, 1800000);
  735. if (ret) {
  736. printf("Setting to 1.8V error");
  737. return -EIO;
  738. }
  739. }
  740. #endif
  741. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  742. if (esdhc_read32(&regs->vendorspec) & ESDHC_VENDORSPEC_VSELECT)
  743. return 0;
  744. return -EAGAIN;
  745. case MMC_SIGNAL_VOLTAGE_120:
  746. return -ENOTSUPP;
  747. default:
  748. return 0;
  749. }
  750. }
  751. static void esdhc_stop_tuning(struct mmc *mmc)
  752. {
  753. struct mmc_cmd cmd;
  754. cmd.cmdidx = MMC_CMD_STOP_TRANSMISSION;
  755. cmd.cmdarg = 0;
  756. cmd.resp_type = MMC_RSP_R1b;
  757. dm_mmc_send_cmd(mmc->dev, &cmd, NULL);
  758. }
  759. static int fsl_esdhc_execute_tuning(struct udevice *dev, uint32_t opcode)
  760. {
  761. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  762. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  763. struct fsl_esdhc *regs = priv->esdhc_regs;
  764. struct mmc *mmc = &plat->mmc;
  765. u32 irqstaten = readl(&regs->irqstaten);
  766. u32 irqsigen = readl(&regs->irqsigen);
  767. int i, ret = -ETIMEDOUT;
  768. u32 val, mixctrl;
  769. /* clock tuning is not needed for upto 52MHz */
  770. if (mmc->clock <= 52000000)
  771. return 0;
  772. /* This is readw/writew SDHCI_HOST_CONTROL2 when tuning */
  773. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  774. val = readl(&regs->autoc12err);
  775. mixctrl = readl(&regs->mixctrl);
  776. val &= ~MIX_CTRL_SMPCLK_SEL;
  777. mixctrl &= ~(MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN);
  778. val |= MIX_CTRL_EXE_TUNE;
  779. mixctrl |= MIX_CTRL_FBCLK_SEL | MIX_CTRL_AUTO_TUNE_EN;
  780. writel(val, &regs->autoc12err);
  781. writel(mixctrl, &regs->mixctrl);
  782. }
  783. /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); */
  784. mixctrl = readl(&regs->mixctrl);
  785. mixctrl = MIX_CTRL_DTDSEL_READ | (mixctrl & ~MIX_CTRL_SDHCI_MASK);
  786. writel(mixctrl, &regs->mixctrl);
  787. writel(IRQSTATEN_BRR, &regs->irqstaten);
  788. writel(IRQSTATEN_BRR, &regs->irqsigen);
  789. /*
  790. * Issue opcode repeatedly till Execute Tuning is set to 0 or the number
  791. * of loops reaches 40 times.
  792. */
  793. for (i = 0; i < MAX_TUNING_LOOP; i++) {
  794. u32 ctrl;
  795. if (opcode == MMC_CMD_SEND_TUNING_BLOCK_HS200) {
  796. if (mmc->bus_width == 8)
  797. writel(0x7080, &regs->blkattr);
  798. else if (mmc->bus_width == 4)
  799. writel(0x7040, &regs->blkattr);
  800. } else {
  801. writel(0x7040, &regs->blkattr);
  802. }
  803. /* sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE) */
  804. val = readl(&regs->mixctrl);
  805. val = MIX_CTRL_DTDSEL_READ | (val & ~MIX_CTRL_SDHCI_MASK);
  806. writel(val, &regs->mixctrl);
  807. /* We are using STD tuning, no need to check return value */
  808. mmc_send_tuning(mmc, opcode, NULL);
  809. ctrl = readl(&regs->autoc12err);
  810. if ((!(ctrl & MIX_CTRL_EXE_TUNE)) &&
  811. (ctrl & MIX_CTRL_SMPCLK_SEL)) {
  812. ret = 0;
  813. break;
  814. }
  815. }
  816. writel(irqstaten, &regs->irqstaten);
  817. writel(irqsigen, &regs->irqsigen);
  818. esdhc_stop_tuning(mmc);
  819. return ret;
  820. }
  821. #endif
  822. static int esdhc_set_ios_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  823. {
  824. struct fsl_esdhc *regs = priv->esdhc_regs;
  825. int ret __maybe_unused;
  826. u32 clock;
  827. /* Set the clock speed */
  828. clock = mmc->clock;
  829. if (clock < mmc->cfg->f_min)
  830. clock = mmc->cfg->f_min;
  831. if (priv->clock != clock)
  832. set_sysctl(priv, mmc, clock);
  833. #ifdef MMC_SUPPORTS_TUNING
  834. if (mmc->clk_disable) {
  835. #ifdef CONFIG_FSL_USDHC
  836. esdhc_clrbits32(&regs->vendorspec, VENDORSPEC_CKEN);
  837. #else
  838. esdhc_clrbits32(&regs->sysctl, SYSCTL_CKEN);
  839. #endif
  840. } else {
  841. #ifdef CONFIG_FSL_USDHC
  842. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
  843. VENDORSPEC_CKEN);
  844. #else
  845. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_CKEN);
  846. #endif
  847. }
  848. if (priv->mode != mmc->selected_mode) {
  849. ret = esdhc_set_timing(mmc);
  850. if (ret) {
  851. printf("esdhc_set_timing error %d\n", ret);
  852. return ret;
  853. }
  854. }
  855. if (priv->signal_voltage != mmc->signal_voltage) {
  856. ret = esdhc_set_voltage(mmc);
  857. if (ret) {
  858. if (ret != -ENOTSUPP)
  859. printf("esdhc_set_voltage error %d\n", ret);
  860. return ret;
  861. }
  862. }
  863. #endif
  864. /* Set the bus width */
  865. esdhc_clrbits32(&regs->proctl, PROCTL_DTW_4 | PROCTL_DTW_8);
  866. if (mmc->bus_width == 4)
  867. esdhc_setbits32(&regs->proctl, PROCTL_DTW_4);
  868. else if (mmc->bus_width == 8)
  869. esdhc_setbits32(&regs->proctl, PROCTL_DTW_8);
  870. return 0;
  871. }
  872. static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc)
  873. {
  874. struct fsl_esdhc *regs = priv->esdhc_regs;
  875. ulong start;
  876. /* Reset the entire host controller */
  877. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  878. /* Wait until the controller is available */
  879. start = get_timer(0);
  880. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  881. if (get_timer(start) > 1000)
  882. return -ETIMEDOUT;
  883. }
  884. #if defined(CONFIG_FSL_USDHC)
  885. /* RSTA doesn't reset MMC_BOOT register, so manually reset it */
  886. esdhc_write32(&regs->mmcboot, 0x0);
  887. /* Reset MIX_CTRL and CLK_TUNE_CTRL_STATUS regs to 0 */
  888. esdhc_write32(&regs->mixctrl, 0x0);
  889. esdhc_write32(&regs->clktunectrlstatus, 0x0);
  890. /* Put VEND_SPEC to default value */
  891. if (priv->vs18_enable)
  892. esdhc_write32(&regs->vendorspec, (VENDORSPEC_INIT |
  893. ESDHC_VENDORSPEC_VSELECT));
  894. else
  895. esdhc_write32(&regs->vendorspec, VENDORSPEC_INIT);
  896. /* Disable DLL_CTRL delay line */
  897. esdhc_write32(&regs->dllctrl, 0x0);
  898. #endif
  899. #ifndef ARCH_MXC
  900. /* Enable cache snooping */
  901. esdhc_write32(&regs->scr, 0x00000040);
  902. #endif
  903. #ifndef CONFIG_FSL_USDHC
  904. esdhc_setbits32(&regs->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN);
  905. #else
  906. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_HCKEN | VENDORSPEC_IPGEN);
  907. #endif
  908. /* Set the initial clock speed */
  909. mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE);
  910. /* Disable the BRR and BWR bits in IRQSTAT */
  911. esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
  912. #ifdef CONFIG_MCF5441x
  913. esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
  914. #else
  915. /* Put the PROCTL reg back to the default */
  916. esdhc_write32(&regs->proctl, PROCTL_INIT);
  917. #endif
  918. /* Set timout to the maximum value */
  919. esdhc_clrsetbits32(&regs->sysctl, SYSCTL_TIMEOUT_MASK, 14 << 16);
  920. return 0;
  921. }
  922. static int esdhc_getcd_common(struct fsl_esdhc_priv *priv)
  923. {
  924. struct fsl_esdhc *regs = priv->esdhc_regs;
  925. int timeout = 1000;
  926. #ifdef CONFIG_ESDHC_DETECT_QUIRK
  927. if (CONFIG_ESDHC_DETECT_QUIRK)
  928. return 1;
  929. #endif
  930. #if CONFIG_IS_ENABLED(DM_MMC)
  931. if (priv->non_removable)
  932. return 1;
  933. if (priv->broken_cd)
  934. return 1;
  935. #if CONFIG_IS_ENABLED(DM_GPIO)
  936. if (dm_gpio_is_valid(&priv->cd_gpio))
  937. return dm_gpio_get_value(&priv->cd_gpio);
  938. #endif
  939. #endif
  940. while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout)
  941. udelay(1000);
  942. return timeout > 0;
  943. }
  944. static int esdhc_reset(struct fsl_esdhc *regs)
  945. {
  946. ulong start;
  947. /* reset the controller */
  948. esdhc_setbits32(&regs->sysctl, SYSCTL_RSTA);
  949. /* hardware clears the bit when it is done */
  950. start = get_timer(0);
  951. while ((esdhc_read32(&regs->sysctl) & SYSCTL_RSTA)) {
  952. if (get_timer(start) > 100) {
  953. printf("MMC/SD: Reset never completed.\n");
  954. return -ETIMEDOUT;
  955. }
  956. }
  957. return 0;
  958. }
  959. #if !CONFIG_IS_ENABLED(DM_MMC)
  960. static int esdhc_getcd(struct mmc *mmc)
  961. {
  962. struct fsl_esdhc_priv *priv = mmc->priv;
  963. return esdhc_getcd_common(priv);
  964. }
  965. static int esdhc_init(struct mmc *mmc)
  966. {
  967. struct fsl_esdhc_priv *priv = mmc->priv;
  968. return esdhc_init_common(priv, mmc);
  969. }
  970. static int esdhc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
  971. struct mmc_data *data)
  972. {
  973. struct fsl_esdhc_priv *priv = mmc->priv;
  974. return esdhc_send_cmd_common(priv, mmc, cmd, data);
  975. }
  976. static int esdhc_set_ios(struct mmc *mmc)
  977. {
  978. struct fsl_esdhc_priv *priv = mmc->priv;
  979. return esdhc_set_ios_common(priv, mmc);
  980. }
  981. static const struct mmc_ops esdhc_ops = {
  982. .getcd = esdhc_getcd,
  983. .init = esdhc_init,
  984. .send_cmd = esdhc_send_cmd,
  985. .set_ios = esdhc_set_ios,
  986. };
  987. #endif
  988. static int fsl_esdhc_init(struct fsl_esdhc_priv *priv,
  989. struct fsl_esdhc_plat *plat)
  990. {
  991. struct mmc_config *cfg;
  992. struct fsl_esdhc *regs;
  993. u32 caps, voltage_caps;
  994. int ret;
  995. if (!priv)
  996. return -EINVAL;
  997. regs = priv->esdhc_regs;
  998. /* First reset the eSDHC controller */
  999. ret = esdhc_reset(regs);
  1000. if (ret)
  1001. return ret;
  1002. #ifdef CONFIG_MCF5441x
  1003. /* ColdFire, using SDHC_DATA[3] for card detection */
  1004. esdhc_write32(&regs->proctl, PROCTL_INIT | PROCTL_D3CD);
  1005. #endif
  1006. #ifndef CONFIG_FSL_USDHC
  1007. esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
  1008. | SYSCTL_IPGEN | SYSCTL_CKEN);
  1009. /* Clearing tuning bits in case ROM has set it already */
  1010. esdhc_write32(&regs->mixctrl, 0);
  1011. esdhc_write32(&regs->autoc12err, 0);
  1012. esdhc_write32(&regs->clktunectrlstatus, 0);
  1013. #else
  1014. esdhc_setbits32(&regs->vendorspec, VENDORSPEC_PEREN |
  1015. VENDORSPEC_HCKEN | VENDORSPEC_IPGEN | VENDORSPEC_CKEN);
  1016. #endif
  1017. if (priv->vs18_enable)
  1018. esdhc_setbits32(&regs->vendorspec, ESDHC_VENDORSPEC_VSELECT);
  1019. writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
  1020. cfg = &plat->cfg;
  1021. #ifndef CONFIG_DM_MMC
  1022. memset(cfg, '\0', sizeof(*cfg));
  1023. #endif
  1024. voltage_caps = 0;
  1025. caps = esdhc_read32(&regs->hostcapblt);
  1026. #ifdef CONFIG_MCF5441x
  1027. /*
  1028. * MCF5441x RM declares in more points that sdhc clock speed must
  1029. * never exceed 25 Mhz. From this, the HS bit needs to be disabled
  1030. * from host capabilities.
  1031. */
  1032. caps &= ~ESDHC_HOSTCAPBLT_HSS;
  1033. #endif
  1034. #ifdef CONFIG_SYS_FSL_ERRATUM_ESDHC135
  1035. caps = caps & ~(ESDHC_HOSTCAPBLT_SRS |
  1036. ESDHC_HOSTCAPBLT_VS18 | ESDHC_HOSTCAPBLT_VS30);
  1037. #endif
  1038. /* T4240 host controller capabilities register should have VS33 bit */
  1039. #ifdef CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
  1040. caps = caps | ESDHC_HOSTCAPBLT_VS33;
  1041. #endif
  1042. if (caps & ESDHC_HOSTCAPBLT_VS18)
  1043. voltage_caps |= MMC_VDD_165_195;
  1044. if (caps & ESDHC_HOSTCAPBLT_VS30)
  1045. voltage_caps |= MMC_VDD_29_30 | MMC_VDD_30_31;
  1046. if (caps & ESDHC_HOSTCAPBLT_VS33)
  1047. voltage_caps |= MMC_VDD_32_33 | MMC_VDD_33_34;
  1048. cfg->name = "FSL_SDHC";
  1049. #if !CONFIG_IS_ENABLED(DM_MMC)
  1050. cfg->ops = &esdhc_ops;
  1051. #endif
  1052. #ifdef CONFIG_SYS_SD_VOLTAGE
  1053. cfg->voltages = CONFIG_SYS_SD_VOLTAGE;
  1054. #else
  1055. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34;
  1056. #endif
  1057. if ((cfg->voltages & voltage_caps) == 0) {
  1058. printf("voltage not supported by controller\n");
  1059. return -1;
  1060. }
  1061. if (priv->bus_width == 8)
  1062. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  1063. else if (priv->bus_width == 4)
  1064. cfg->host_caps = MMC_MODE_4BIT;
  1065. cfg->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT;
  1066. #ifdef CONFIG_SYS_FSL_ESDHC_HAS_DDR_MODE
  1067. cfg->host_caps |= MMC_MODE_DDR_52MHz;
  1068. #endif
  1069. if (priv->bus_width > 0) {
  1070. if (priv->bus_width < 8)
  1071. cfg->host_caps &= ~MMC_MODE_8BIT;
  1072. if (priv->bus_width < 4)
  1073. cfg->host_caps &= ~MMC_MODE_4BIT;
  1074. }
  1075. if (caps & ESDHC_HOSTCAPBLT_HSS)
  1076. cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
  1077. #ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
  1078. if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
  1079. cfg->host_caps &= ~MMC_MODE_8BIT;
  1080. #endif
  1081. cfg->host_caps |= priv->caps;
  1082. cfg->f_min = 400000;
  1083. cfg->f_max = min(priv->sdhc_clk, (u32)200000000);
  1084. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  1085. writel(0, &regs->dllctrl);
  1086. if (priv->flags & ESDHC_FLAG_USDHC) {
  1087. if (priv->flags & ESDHC_FLAG_STD_TUNING) {
  1088. u32 val = readl(&regs->tuning_ctrl);
  1089. val |= ESDHC_STD_TUNING_EN;
  1090. val &= ~ESDHC_TUNING_START_TAP_MASK;
  1091. val |= priv->tuning_start_tap;
  1092. val &= ~ESDHC_TUNING_STEP_MASK;
  1093. val |= (priv->tuning_step) << ESDHC_TUNING_STEP_SHIFT;
  1094. /* Disable the CMD CRC check for tuning, if not, need to
  1095. * add some delay after every tuning command, because
  1096. * hardware standard tuning logic will directly go to next
  1097. * step once it detect the CMD CRC error, will not wait for
  1098. * the card side to finally send out the tuning data, trigger
  1099. * the buffer read ready interrupt immediately. If usdhc send
  1100. * the next tuning command some eMMC card will stuck, can't
  1101. * response, block the tuning procedure or the first command
  1102. * after the whole tuning procedure always can't get any response.
  1103. */
  1104. val |= ESDHC_TUNING_CMD_CRC_CHECK_DISABLE;
  1105. writel(val, &regs->tuning_ctrl);
  1106. }
  1107. }
  1108. return 0;
  1109. }
  1110. #if !CONFIG_IS_ENABLED(DM_MMC)
  1111. static int fsl_esdhc_cfg_to_priv(struct fsl_esdhc_cfg *cfg,
  1112. struct fsl_esdhc_priv *priv)
  1113. {
  1114. if (!cfg || !priv)
  1115. return -EINVAL;
  1116. priv->esdhc_regs = (struct fsl_esdhc *)(unsigned long)(cfg->esdhc_base);
  1117. priv->bus_width = cfg->max_bus_width;
  1118. priv->sdhc_clk = cfg->sdhc_clk;
  1119. priv->wp_enable = cfg->wp_enable;
  1120. priv->vs18_enable = cfg->vs18_enable;
  1121. return 0;
  1122. };
  1123. int fsl_esdhc_initialize(struct bd_info *bis, struct fsl_esdhc_cfg *cfg)
  1124. {
  1125. struct fsl_esdhc_plat *plat;
  1126. struct fsl_esdhc_priv *priv;
  1127. struct mmc *mmc;
  1128. int ret;
  1129. if (!cfg)
  1130. return -EINVAL;
  1131. priv = calloc(sizeof(struct fsl_esdhc_priv), 1);
  1132. if (!priv)
  1133. return -ENOMEM;
  1134. plat = calloc(sizeof(struct fsl_esdhc_plat), 1);
  1135. if (!plat) {
  1136. free(priv);
  1137. return -ENOMEM;
  1138. }
  1139. ret = fsl_esdhc_cfg_to_priv(cfg, priv);
  1140. if (ret) {
  1141. debug("%s xlate failure\n", __func__);
  1142. free(plat);
  1143. free(priv);
  1144. return ret;
  1145. }
  1146. ret = fsl_esdhc_init(priv, plat);
  1147. if (ret) {
  1148. debug("%s init failure\n", __func__);
  1149. free(plat);
  1150. free(priv);
  1151. return ret;
  1152. }
  1153. mmc = mmc_create(&plat->cfg, priv);
  1154. if (!mmc)
  1155. return -EIO;
  1156. priv->mmc = mmc;
  1157. return 0;
  1158. }
  1159. int fsl_esdhc_mmc_init(struct bd_info *bis)
  1160. {
  1161. struct fsl_esdhc_cfg *cfg;
  1162. cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1);
  1163. cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR;
  1164. cfg->sdhc_clk = gd->arch.sdhc_clk;
  1165. return fsl_esdhc_initialize(bis, cfg);
  1166. }
  1167. #endif
  1168. #ifdef CONFIG_OF_LIBFDT
  1169. __weak int esdhc_status_fixup(void *blob, const char *compat)
  1170. {
  1171. #ifdef CONFIG_FSL_ESDHC_PIN_MUX
  1172. if (!hwconfig("esdhc")) {
  1173. do_fixup_by_compat(blob, compat, "status", "disabled",
  1174. sizeof("disabled"), 1);
  1175. return 1;
  1176. }
  1177. #endif
  1178. return 0;
  1179. }
  1180. void fdt_fixup_esdhc(void *blob, struct bd_info *bd)
  1181. {
  1182. const char *compat = "fsl,esdhc";
  1183. if (esdhc_status_fixup(blob, compat))
  1184. return;
  1185. do_fixup_by_compat_u32(blob, compat, "clock-frequency",
  1186. gd->arch.sdhc_clk, 1);
  1187. }
  1188. #endif
  1189. #if CONFIG_IS_ENABLED(DM_MMC)
  1190. #include <asm/arch/clock.h>
  1191. __weak void init_clk_usdhc(u32 index)
  1192. {
  1193. }
  1194. static int fsl_esdhc_ofdata_to_platdata(struct udevice *dev)
  1195. {
  1196. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  1197. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1198. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1199. struct udevice *vqmmc_dev;
  1200. int ret;
  1201. #endif
  1202. const void *fdt = gd->fdt_blob;
  1203. int node = dev_of_offset(dev);
  1204. fdt_addr_t addr;
  1205. unsigned int val;
  1206. addr = dev_read_addr(dev);
  1207. if (addr == FDT_ADDR_T_NONE)
  1208. return -EINVAL;
  1209. priv->esdhc_regs = (struct fsl_esdhc *)addr;
  1210. priv->dev = dev;
  1211. priv->mode = -1;
  1212. val = dev_read_u32_default(dev, "bus-width", -1);
  1213. if (val == 8)
  1214. priv->bus_width = 8;
  1215. else if (val == 4)
  1216. priv->bus_width = 4;
  1217. else
  1218. priv->bus_width = 1;
  1219. val = fdtdec_get_int(fdt, node, "fsl,tuning-step", 1);
  1220. priv->tuning_step = val;
  1221. val = fdtdec_get_int(fdt, node, "fsl,tuning-start-tap",
  1222. ESDHC_TUNING_START_TAP_DEFAULT);
  1223. priv->tuning_start_tap = val;
  1224. val = fdtdec_get_int(fdt, node, "fsl,strobe-dll-delay-target",
  1225. ESDHC_STROBE_DLL_CTRL_SLV_DLY_TARGET_DEFAULT);
  1226. priv->strobe_dll_delay_target = val;
  1227. if (dev_read_bool(dev, "broken-cd"))
  1228. priv->broken_cd = 1;
  1229. if (dev_read_bool(dev, "non-removable")) {
  1230. priv->non_removable = 1;
  1231. } else {
  1232. priv->non_removable = 0;
  1233. #if CONFIG_IS_ENABLED(DM_GPIO)
  1234. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio,
  1235. GPIOD_IS_IN);
  1236. #endif
  1237. }
  1238. if (dev_read_prop(dev, "fsl,wp-controller", NULL)) {
  1239. priv->wp_enable = 1;
  1240. } else {
  1241. priv->wp_enable = 0;
  1242. #if CONFIG_IS_ENABLED(DM_GPIO)
  1243. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio,
  1244. GPIOD_IS_IN);
  1245. #endif
  1246. }
  1247. priv->vs18_enable = 0;
  1248. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  1249. /*
  1250. * If emmc I/O has a fixed voltage at 1.8V, this must be provided,
  1251. * otherwise, emmc will work abnormally.
  1252. */
  1253. ret = device_get_supply_regulator(dev, "vqmmc-supply", &vqmmc_dev);
  1254. if (ret) {
  1255. dev_dbg(dev, "no vqmmc-supply\n");
  1256. } else {
  1257. priv->vqmmc_dev = vqmmc_dev;
  1258. ret = regulator_set_enable(vqmmc_dev, true);
  1259. if (ret) {
  1260. dev_err(dev, "fail to enable vqmmc-supply\n");
  1261. return ret;
  1262. }
  1263. if (regulator_get_value(vqmmc_dev) == 1800000)
  1264. priv->vs18_enable = 1;
  1265. }
  1266. #endif
  1267. #endif
  1268. return 0;
  1269. }
  1270. static int fsl_esdhc_probe(struct udevice *dev)
  1271. {
  1272. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  1273. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1274. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1275. struct esdhc_soc_data *data =
  1276. (struct esdhc_soc_data *)dev_get_driver_data(dev);
  1277. struct mmc *mmc;
  1278. #if !CONFIG_IS_ENABLED(BLK)
  1279. struct blk_desc *bdesc;
  1280. #endif
  1281. int ret;
  1282. #if CONFIG_IS_ENABLED(OF_PLATDATA)
  1283. struct dtd_fsl_esdhc *dtplat = &plat->dtplat;
  1284. unsigned int val;
  1285. priv->esdhc_regs = map_sysmem(dtplat->reg[0], dtplat->reg[1]);
  1286. val = plat->dtplat.bus_width;
  1287. if (val == 8)
  1288. priv->bus_width = 8;
  1289. else if (val == 4)
  1290. priv->bus_width = 4;
  1291. else
  1292. priv->bus_width = 1;
  1293. if (dtplat->non_removable)
  1294. priv->non_removable = 1;
  1295. else
  1296. priv->non_removable = 0;
  1297. if (CONFIG_IS_ENABLED(DM_GPIO) && !priv->non_removable) {
  1298. struct udevice *gpiodev;
  1299. struct driver_info *info;
  1300. info = (struct driver_info *)dtplat->cd_gpios->node;
  1301. ret = device_get_by_driver_info(info, &gpiodev);
  1302. if (ret)
  1303. return ret;
  1304. ret = gpio_dev_request_index(gpiodev, gpiodev->name, "cd-gpios",
  1305. dtplat->cd_gpios->arg[0], GPIOD_IS_IN,
  1306. dtplat->cd_gpios->arg[1], &priv->cd_gpio);
  1307. if (ret)
  1308. return ret;
  1309. }
  1310. #endif
  1311. if (data)
  1312. priv->flags = data->flags;
  1313. /*
  1314. * TODO:
  1315. * Because lack of clk driver, if SDHC clk is not enabled,
  1316. * need to enable it first before this driver is invoked.
  1317. *
  1318. * we use MXC_ESDHC_CLK to get clk freq.
  1319. * If one would like to make this function work,
  1320. * the aliases should be provided in dts as this:
  1321. *
  1322. * aliases {
  1323. * mmc0 = &usdhc1;
  1324. * mmc1 = &usdhc2;
  1325. * mmc2 = &usdhc3;
  1326. * mmc3 = &usdhc4;
  1327. * };
  1328. * Then if your board only supports mmc2 and mmc3, but we can
  1329. * correctly get the seq as 2 and 3, then let mxc_get_clock
  1330. * work as expected.
  1331. */
  1332. init_clk_usdhc(dev->seq);
  1333. #if CONFIG_IS_ENABLED(CLK)
  1334. /* Assigned clock already set clock */
  1335. ret = clk_get_by_name(dev, "per", &priv->per_clk);
  1336. if (ret) {
  1337. printf("Failed to get per_clk\n");
  1338. return ret;
  1339. }
  1340. ret = clk_enable(&priv->per_clk);
  1341. if (ret) {
  1342. printf("Failed to enable per_clk\n");
  1343. return ret;
  1344. }
  1345. priv->sdhc_clk = clk_get_rate(&priv->per_clk);
  1346. #else
  1347. priv->sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK + dev->seq);
  1348. if (priv->sdhc_clk <= 0) {
  1349. dev_err(dev, "Unable to get clk for %s\n", dev->name);
  1350. return -EINVAL;
  1351. }
  1352. #endif
  1353. ret = fsl_esdhc_init(priv, plat);
  1354. if (ret) {
  1355. dev_err(dev, "fsl_esdhc_init failure\n");
  1356. return ret;
  1357. }
  1358. #if !CONFIG_IS_ENABLED(OF_PLATDATA)
  1359. ret = mmc_of_parse(dev, &plat->cfg);
  1360. if (ret)
  1361. return ret;
  1362. #endif
  1363. mmc = &plat->mmc;
  1364. mmc->cfg = &plat->cfg;
  1365. mmc->dev = dev;
  1366. #if !CONFIG_IS_ENABLED(BLK)
  1367. mmc->priv = priv;
  1368. /* Setup dsr related values */
  1369. mmc->dsr_imp = 0;
  1370. mmc->dsr = ESDHC_DRIVER_STAGE_VALUE;
  1371. /* Setup the universal parts of the block interface just once */
  1372. bdesc = mmc_get_blk_desc(mmc);
  1373. bdesc->if_type = IF_TYPE_MMC;
  1374. bdesc->removable = 1;
  1375. bdesc->devnum = mmc_get_next_devnum();
  1376. bdesc->block_read = mmc_bread;
  1377. bdesc->block_write = mmc_bwrite;
  1378. bdesc->block_erase = mmc_berase;
  1379. /* setup initial part type */
  1380. bdesc->part_type = mmc->cfg->part_type;
  1381. mmc_list_add(mmc);
  1382. #endif
  1383. upriv->mmc = mmc;
  1384. return esdhc_init_common(priv, mmc);
  1385. }
  1386. #if CONFIG_IS_ENABLED(DM_MMC)
  1387. static int fsl_esdhc_get_cd(struct udevice *dev)
  1388. {
  1389. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1390. return esdhc_getcd_common(priv);
  1391. }
  1392. static int fsl_esdhc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  1393. struct mmc_data *data)
  1394. {
  1395. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1396. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1397. return esdhc_send_cmd_common(priv, &plat->mmc, cmd, data);
  1398. }
  1399. static int fsl_esdhc_set_ios(struct udevice *dev)
  1400. {
  1401. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1402. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1403. return esdhc_set_ios_common(priv, &plat->mmc);
  1404. }
  1405. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1406. static int fsl_esdhc_set_enhanced_strobe(struct udevice *dev)
  1407. {
  1408. struct fsl_esdhc_priv *priv = dev_get_priv(dev);
  1409. struct fsl_esdhc *regs = priv->esdhc_regs;
  1410. u32 m;
  1411. m = readl(&regs->mixctrl);
  1412. m |= MIX_CTRL_HS400_ES;
  1413. writel(m, &regs->mixctrl);
  1414. return 0;
  1415. }
  1416. #endif
  1417. static const struct dm_mmc_ops fsl_esdhc_ops = {
  1418. .get_cd = fsl_esdhc_get_cd,
  1419. .send_cmd = fsl_esdhc_send_cmd,
  1420. .set_ios = fsl_esdhc_set_ios,
  1421. #ifdef MMC_SUPPORTS_TUNING
  1422. .execute_tuning = fsl_esdhc_execute_tuning,
  1423. #endif
  1424. #if CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
  1425. .set_enhanced_strobe = fsl_esdhc_set_enhanced_strobe,
  1426. #endif
  1427. };
  1428. #endif
  1429. static struct esdhc_soc_data usdhc_imx7d_data = {
  1430. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING
  1431. | ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200
  1432. | ESDHC_FLAG_HS400,
  1433. };
  1434. static struct esdhc_soc_data usdhc_imx8qm_data = {
  1435. .flags = ESDHC_FLAG_USDHC | ESDHC_FLAG_STD_TUNING |
  1436. ESDHC_FLAG_HAVE_CAP1 | ESDHC_FLAG_HS200 |
  1437. ESDHC_FLAG_HS400 | ESDHC_FLAG_HS400_ES,
  1438. };
  1439. static const struct udevice_id fsl_esdhc_ids[] = {
  1440. { .compatible = "fsl,imx53-esdhc", },
  1441. { .compatible = "fsl,imx6ul-usdhc", },
  1442. { .compatible = "fsl,imx6sx-usdhc", },
  1443. { .compatible = "fsl,imx6sl-usdhc", },
  1444. { .compatible = "fsl,imx6q-usdhc", },
  1445. { .compatible = "fsl,imx7d-usdhc", .data = (ulong)&usdhc_imx7d_data,},
  1446. { .compatible = "fsl,imx7ulp-usdhc", },
  1447. { .compatible = "fsl,imx8qm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1448. { .compatible = "fsl,imx8mm-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1449. { .compatible = "fsl,imx8mn-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1450. { .compatible = "fsl,imx8mq-usdhc", .data = (ulong)&usdhc_imx8qm_data,},
  1451. { .compatible = "fsl,imxrt-usdhc", },
  1452. { .compatible = "fsl,esdhc", },
  1453. { /* sentinel */ }
  1454. };
  1455. #if CONFIG_IS_ENABLED(BLK)
  1456. static int fsl_esdhc_bind(struct udevice *dev)
  1457. {
  1458. struct fsl_esdhc_plat *plat = dev_get_platdata(dev);
  1459. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  1460. }
  1461. #endif
  1462. U_BOOT_DRIVER(fsl_esdhc) = {
  1463. .name = "fsl_esdhc",
  1464. .id = UCLASS_MMC,
  1465. .of_match = fsl_esdhc_ids,
  1466. .ofdata_to_platdata = fsl_esdhc_ofdata_to_platdata,
  1467. .ops = &fsl_esdhc_ops,
  1468. #if CONFIG_IS_ENABLED(BLK)
  1469. .bind = fsl_esdhc_bind,
  1470. #endif
  1471. .probe = fsl_esdhc_probe,
  1472. .platdata_auto_alloc_size = sizeof(struct fsl_esdhc_plat),
  1473. .priv_auto_alloc_size = sizeof(struct fsl_esdhc_priv),
  1474. };
  1475. U_BOOT_DRIVER_ALIAS(fsl_esdhc, fsl_imx6q_usdhc)
  1476. #endif