exynos_dw_mmc.c 7.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012 SAMSUNG Electronics
  4. * Jaehoon Chung <jh80.chung@samsung.com>
  5. */
  6. #include <common.h>
  7. #include <dwmmc.h>
  8. #include <fdtdec.h>
  9. #include <linux/libfdt.h>
  10. #include <malloc.h>
  11. #include <errno.h>
  12. #include <asm/arch/dwmmc.h>
  13. #include <asm/arch/clk.h>
  14. #include <asm/arch/pinmux.h>
  15. #include <asm/arch/power.h>
  16. #include <asm/gpio.h>
  17. #define DWMMC_MAX_CH_NUM 4
  18. #define DWMMC_MAX_FREQ 52000000
  19. #define DWMMC_MIN_FREQ 400000
  20. #define DWMMC_MMC0_SDR_TIMING_VAL 0x03030001
  21. #define DWMMC_MMC2_SDR_TIMING_VAL 0x03020001
  22. #ifdef CONFIG_DM_MMC
  23. #include <dm.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. struct exynos_mmc_plat {
  26. struct mmc_config cfg;
  27. struct mmc mmc;
  28. };
  29. #endif
  30. /* Exynos implmentation specific drver private data */
  31. struct dwmci_exynos_priv_data {
  32. #ifdef CONFIG_DM_MMC
  33. struct dwmci_host host;
  34. #endif
  35. u32 sdr_timing;
  36. };
  37. /*
  38. * Function used as callback function to initialise the
  39. * CLKSEL register for every mmc channel.
  40. */
  41. static void exynos_dwmci_clksel(struct dwmci_host *host)
  42. {
  43. #ifdef CONFIG_DM_MMC
  44. struct dwmci_exynos_priv_data *priv =
  45. container_of(host, struct dwmci_exynos_priv_data, host);
  46. #else
  47. struct dwmci_exynos_priv_data *priv = host->priv;
  48. #endif
  49. dwmci_writel(host, DWMCI_CLKSEL, priv->sdr_timing);
  50. }
  51. unsigned int exynos_dwmci_get_clk(struct dwmci_host *host, uint freq)
  52. {
  53. unsigned long sclk;
  54. int8_t clk_div;
  55. /*
  56. * Since SDCLKIN is divided inside controller by the DIVRATIO
  57. * value set in the CLKSEL register, we need to use the same output
  58. * clock value to calculate the CLKDIV value.
  59. * as per user manual:cclk_in = SDCLKIN / (DIVRATIO + 1)
  60. */
  61. clk_div = ((dwmci_readl(host, DWMCI_CLKSEL) >> DWMCI_DIVRATIO_BIT)
  62. & DWMCI_DIVRATIO_MASK) + 1;
  63. sclk = get_mmc_clk(host->dev_index);
  64. /*
  65. * Assume to know divider value.
  66. * When clock unit is broken, need to set "host->div"
  67. */
  68. return sclk / clk_div / (host->div + 1);
  69. }
  70. static void exynos_dwmci_board_init(struct dwmci_host *host)
  71. {
  72. struct dwmci_exynos_priv_data *priv = host->priv;
  73. if (host->quirks & DWMCI_QUIRK_DISABLE_SMU) {
  74. dwmci_writel(host, EMMCP_MPSBEGIN0, 0);
  75. dwmci_writel(host, EMMCP_SEND0, 0);
  76. dwmci_writel(host, EMMCP_CTRL0,
  77. MPSCTRL_SECURE_READ_BIT |
  78. MPSCTRL_SECURE_WRITE_BIT |
  79. MPSCTRL_NON_SECURE_READ_BIT |
  80. MPSCTRL_NON_SECURE_WRITE_BIT | MPSCTRL_VALID);
  81. }
  82. /* Set to timing value at initial time */
  83. if (priv->sdr_timing)
  84. exynos_dwmci_clksel(host);
  85. }
  86. static int exynos_dwmci_core_init(struct dwmci_host *host)
  87. {
  88. unsigned int div;
  89. unsigned long freq, sclk;
  90. if (host->bus_hz)
  91. freq = host->bus_hz;
  92. else
  93. freq = DWMMC_MAX_FREQ;
  94. /* request mmc clock vlaue of 52MHz. */
  95. sclk = get_mmc_clk(host->dev_index);
  96. div = DIV_ROUND_UP(sclk, freq);
  97. /* set the clock divisor for mmc */
  98. set_mmc_clk(host->dev_index, div);
  99. host->name = "EXYNOS DWMMC";
  100. #ifdef CONFIG_EXYNOS5420
  101. host->quirks = DWMCI_QUIRK_DISABLE_SMU;
  102. #endif
  103. host->board_init = exynos_dwmci_board_init;
  104. host->caps = MMC_MODE_DDR_52MHz;
  105. host->clksel = exynos_dwmci_clksel;
  106. host->get_mmc_clk = exynos_dwmci_get_clk;
  107. #ifndef CONFIG_DM_MMC
  108. /* Add the mmc channel to be registered with mmc core */
  109. if (add_dwmci(host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ)) {
  110. printf("DWMMC%d registration failed\n", host->dev_index);
  111. return -1;
  112. }
  113. #endif
  114. return 0;
  115. }
  116. static struct dwmci_host dwmci_host[DWMMC_MAX_CH_NUM];
  117. static int do_dwmci_init(struct dwmci_host *host)
  118. {
  119. int flag, err;
  120. flag = host->buswidth == 8 ? PINMUX_FLAG_8BIT_MODE : PINMUX_FLAG_NONE;
  121. err = exynos_pinmux_config(host->dev_id, flag);
  122. if (err) {
  123. printf("DWMMC%d not configure\n", host->dev_index);
  124. return err;
  125. }
  126. return exynos_dwmci_core_init(host);
  127. }
  128. static int exynos_dwmci_get_config(const void *blob, int node,
  129. struct dwmci_host *host,
  130. struct dwmci_exynos_priv_data *priv)
  131. {
  132. int err = 0;
  133. u32 base, timing[3];
  134. /* Extract device id for each mmc channel */
  135. host->dev_id = pinmux_decode_periph_id(blob, node);
  136. host->dev_index = fdtdec_get_int(blob, node, "index", host->dev_id);
  137. if (host->dev_index == host->dev_id)
  138. host->dev_index = host->dev_id - PERIPH_ID_SDMMC0;
  139. if (host->dev_index > 4) {
  140. printf("DWMMC%d: Can't get the dev index\n", host->dev_index);
  141. return -EINVAL;
  142. }
  143. /* Get the bus width from the device node (Default is 4bit buswidth) */
  144. host->buswidth = fdtdec_get_int(blob, node, "samsung,bus-width", 4);
  145. /* Set the base address from the device node */
  146. base = fdtdec_get_addr(blob, node, "reg");
  147. if (!base) {
  148. printf("DWMMC%d: Can't get base address\n", host->dev_index);
  149. return -EINVAL;
  150. }
  151. host->ioaddr = (void *)base;
  152. /* Extract the timing info from the node */
  153. err = fdtdec_get_int_array(blob, node, "samsung,timing", timing, 3);
  154. if (err) {
  155. printf("DWMMC%d: Can't get sdr-timings for devider\n",
  156. host->dev_index);
  157. return -EINVAL;
  158. }
  159. priv->sdr_timing = (DWMCI_SET_SAMPLE_CLK(timing[0]) |
  160. DWMCI_SET_DRV_CLK(timing[1]) |
  161. DWMCI_SET_DIV_RATIO(timing[2]));
  162. /* sdr_timing didn't assigned anything, use the default value */
  163. if (!priv->sdr_timing) {
  164. if (host->dev_index == 0)
  165. priv->sdr_timing = DWMMC_MMC0_SDR_TIMING_VAL;
  166. else if (host->dev_index == 2)
  167. priv->sdr_timing = DWMMC_MMC2_SDR_TIMING_VAL;
  168. }
  169. host->fifoth_val = fdtdec_get_int(blob, node, "fifoth_val", 0);
  170. host->bus_hz = fdtdec_get_int(blob, node, "bus_hz", 0);
  171. host->div = fdtdec_get_int(blob, node, "div", 0);
  172. return 0;
  173. }
  174. static int exynos_dwmci_process_node(const void *blob,
  175. int node_list[], int count)
  176. {
  177. struct dwmci_exynos_priv_data *priv;
  178. struct dwmci_host *host;
  179. int i, node, err;
  180. for (i = 0; i < count; i++) {
  181. node = node_list[i];
  182. if (node <= 0)
  183. continue;
  184. host = &dwmci_host[i];
  185. priv = malloc(sizeof(struct dwmci_exynos_priv_data));
  186. if (!priv) {
  187. pr_err("dwmci_exynos_priv_data malloc fail!\n");
  188. return -ENOMEM;
  189. }
  190. err = exynos_dwmci_get_config(blob, node, host, priv);
  191. if (err) {
  192. printf("%s: failed to decode dev %d\n", __func__, i);
  193. free(priv);
  194. return err;
  195. }
  196. host->priv = priv;
  197. do_dwmci_init(host);
  198. }
  199. return 0;
  200. }
  201. int exynos_dwmmc_init(const void *blob)
  202. {
  203. int node_list[DWMMC_MAX_CH_NUM];
  204. int boot_dev_node;
  205. int err = 0, count;
  206. count = fdtdec_find_aliases_for_id(blob, "mmc",
  207. COMPAT_SAMSUNG_EXYNOS_DWMMC, node_list,
  208. DWMMC_MAX_CH_NUM);
  209. /* For DWMMC always set boot device as mmc 0 */
  210. if (count >= 3 && get_boot_mode() == BOOT_MODE_SD) {
  211. boot_dev_node = node_list[2];
  212. node_list[2] = node_list[0];
  213. node_list[0] = boot_dev_node;
  214. }
  215. err = exynos_dwmci_process_node(blob, node_list, count);
  216. return err;
  217. }
  218. #ifdef CONFIG_DM_MMC
  219. static int exynos_dwmmc_probe(struct udevice *dev)
  220. {
  221. struct exynos_mmc_plat *plat = dev_get_platdata(dev);
  222. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  223. struct dwmci_exynos_priv_data *priv = dev_get_priv(dev);
  224. struct dwmci_host *host = &priv->host;
  225. int err;
  226. err = exynos_dwmci_get_config(gd->fdt_blob, dev_of_offset(dev), host,
  227. priv);
  228. if (err)
  229. return err;
  230. err = do_dwmci_init(host);
  231. if (err)
  232. return err;
  233. dwmci_setup_cfg(&plat->cfg, host, DWMMC_MAX_FREQ, DWMMC_MIN_FREQ);
  234. host->mmc = &plat->mmc;
  235. host->mmc->priv = &priv->host;
  236. host->priv = dev;
  237. upriv->mmc = host->mmc;
  238. return dwmci_probe(dev);
  239. }
  240. static int exynos_dwmmc_bind(struct udevice *dev)
  241. {
  242. struct exynos_mmc_plat *plat = dev_get_platdata(dev);
  243. return dwmci_bind(dev, &plat->mmc, &plat->cfg);
  244. }
  245. static const struct udevice_id exynos_dwmmc_ids[] = {
  246. { .compatible = "samsung,exynos4412-dw-mshc" },
  247. { .compatible = "samsung,exynos-dwmmc" },
  248. { }
  249. };
  250. U_BOOT_DRIVER(exynos_dwmmc_drv) = {
  251. .name = "exynos_dwmmc",
  252. .id = UCLASS_MMC,
  253. .of_match = exynos_dwmmc_ids,
  254. .bind = exynos_dwmmc_bind,
  255. .ops = &dm_dwmci_ops,
  256. .probe = exynos_dwmmc_probe,
  257. .priv_auto_alloc_size = sizeof(struct dwmci_exynos_priv_data),
  258. .platdata_auto_alloc_size = sizeof(struct exynos_mmc_plat),
  259. };
  260. #endif