davinci_mmc.c 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Davinci MMC Controller Driver
  4. *
  5. * Copyright (C) 2010 Texas Instruments Incorporated
  6. */
  7. #include <config.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <errno.h>
  11. #include <mmc.h>
  12. #include <command.h>
  13. #include <part.h>
  14. #include <malloc.h>
  15. #include <asm/io.h>
  16. #include <asm/arch/sdmmc_defs.h>
  17. #include <asm-generic/gpio.h>
  18. #include <linux/delay.h>
  19. #define WATCHDOG_COUNT (100000)
  20. #define get_val(addr) REG(addr)
  21. #define set_val(addr, val) REG(addr) = (val)
  22. #define set_bit(addr, val) set_val((addr), (get_val(addr) | (val)))
  23. #define clear_bit(addr, val) set_val((addr), (get_val(addr) & ~(val)))
  24. #ifdef CONFIG_DM_MMC
  25. /* Davinci MMC board definitions */
  26. struct davinci_mmc_priv {
  27. struct davinci_mmc_regs *reg_base; /* Register base address */
  28. uint input_clk; /* Input clock to MMC controller */
  29. struct gpio_desc cd_gpio; /* Card Detect GPIO */
  30. struct gpio_desc wp_gpio; /* Write Protect GPIO */
  31. };
  32. #endif
  33. /* Set davinci clock prescalar value based on the required clock in HZ */
  34. #if !CONFIG_IS_ENABLED(DM_MMC)
  35. static void dmmc_set_clock(struct mmc *mmc, uint clock)
  36. {
  37. struct davinci_mmc *host = mmc->priv;
  38. #else
  39. static void davinci_mmc_set_clock(struct udevice *dev, uint clock)
  40. {
  41. struct davinci_mmc_priv *host = dev_get_priv(dev);
  42. struct mmc *mmc = mmc_get_mmc_dev(dev);
  43. #endif
  44. struct davinci_mmc_regs *regs = host->reg_base;
  45. uint clkrt, sysclk2, act_clock;
  46. if (clock < mmc->cfg->f_min)
  47. clock = mmc->cfg->f_min;
  48. if (clock > mmc->cfg->f_max)
  49. clock = mmc->cfg->f_max;
  50. set_val(&regs->mmcclk, 0);
  51. sysclk2 = host->input_clk;
  52. clkrt = (sysclk2 / (2 * clock)) - 1;
  53. /* Calculate the actual clock for the divider used */
  54. act_clock = (sysclk2 / (2 * (clkrt + 1)));
  55. /* Adjust divider if actual clock exceeds the required clock */
  56. if (act_clock > clock)
  57. clkrt++;
  58. /* check clock divider boundary and correct it */
  59. if (clkrt > 0xFF)
  60. clkrt = 0xFF;
  61. set_val(&regs->mmcclk, (clkrt | MMCCLK_CLKEN));
  62. }
  63. /* Status bit wait loop for MMCST1 */
  64. static int
  65. dmmc_wait_fifo_status(volatile struct davinci_mmc_regs *regs, uint status)
  66. {
  67. uint wdog = WATCHDOG_COUNT;
  68. while (--wdog && ((get_val(&regs->mmcst1) & status) != status))
  69. udelay(10);
  70. if (!(get_val(&regs->mmcctl) & MMCCTL_WIDTH_4_BIT))
  71. udelay(100);
  72. if (wdog == 0)
  73. return -ECOMM;
  74. return 0;
  75. }
  76. /* Busy bit wait loop for MMCST1 */
  77. static int dmmc_busy_wait(volatile struct davinci_mmc_regs *regs)
  78. {
  79. uint wdog = WATCHDOG_COUNT;
  80. while (--wdog && (get_val(&regs->mmcst1) & MMCST1_BUSY))
  81. udelay(10);
  82. if (wdog == 0)
  83. return -ECOMM;
  84. return 0;
  85. }
  86. /* Status bit wait loop for MMCST0 - Checks for error bits as well */
  87. static int dmmc_check_status(volatile struct davinci_mmc_regs *regs,
  88. uint *cur_st, uint st_ready, uint st_error)
  89. {
  90. uint wdog = WATCHDOG_COUNT;
  91. uint mmcstatus = *cur_st;
  92. while (wdog--) {
  93. if (mmcstatus & st_ready) {
  94. *cur_st = mmcstatus;
  95. mmcstatus = get_val(&regs->mmcst1);
  96. return 0;
  97. } else if (mmcstatus & st_error) {
  98. if (mmcstatus & MMCST0_TOUTRS)
  99. return -ETIMEDOUT;
  100. printf("[ ST0 ERROR %x]\n", mmcstatus);
  101. /*
  102. * Ignore CRC errors as some MMC cards fail to
  103. * initialize on DM365-EVM on the SD1 slot
  104. */
  105. if (mmcstatus & MMCST0_CRCRS)
  106. return 0;
  107. return -ECOMM;
  108. }
  109. udelay(10);
  110. mmcstatus = get_val(&regs->mmcst0);
  111. }
  112. printf("Status %x Timeout ST0:%x ST1:%x\n", st_ready, mmcstatus,
  113. get_val(&regs->mmcst1));
  114. return -ECOMM;
  115. }
  116. /*
  117. * Sends a command out on the bus. Takes the device pointer,
  118. * a command pointer, and an optional data pointer.
  119. */
  120. #if !CONFIG_IS_ENABLED(DM_MMC)
  121. static int dmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data)
  122. {
  123. struct davinci_mmc *host = mmc->priv;
  124. #else
  125. static int
  126. davinci_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd, struct mmc_data *data)
  127. {
  128. struct davinci_mmc_priv *host = dev_get_priv(dev);
  129. #endif
  130. volatile struct davinci_mmc_regs *regs = host->reg_base;
  131. uint mmcstatus, status_rdy, status_err;
  132. uint i, cmddata, bytes_left = 0;
  133. int fifo_words, fifo_bytes, err;
  134. char *data_buf = NULL;
  135. /* Clear status registers */
  136. mmcstatus = get_val(&regs->mmcst0);
  137. fifo_words = 16;
  138. fifo_bytes = fifo_words << 2;
  139. /* Wait for any previous busy signal to be cleared */
  140. dmmc_busy_wait(regs);
  141. cmddata = cmd->cmdidx;
  142. cmddata |= MMCCMD_PPLEN;
  143. /* Send init clock for CMD0 */
  144. if (cmd->cmdidx == MMC_CMD_GO_IDLE_STATE)
  145. cmddata |= MMCCMD_INITCK;
  146. switch (cmd->resp_type) {
  147. case MMC_RSP_R1b:
  148. cmddata |= MMCCMD_BSYEXP;
  149. /* Fall-through */
  150. case MMC_RSP_R1: /* R1, R1b, R5, R6, R7 */
  151. cmddata |= MMCCMD_RSPFMT_R1567;
  152. break;
  153. case MMC_RSP_R2:
  154. cmddata |= MMCCMD_RSPFMT_R2;
  155. break;
  156. case MMC_RSP_R3: /* R3, R4 */
  157. cmddata |= MMCCMD_RSPFMT_R3;
  158. break;
  159. }
  160. set_val(&regs->mmcim, 0);
  161. if (data) {
  162. /* clear previous data transfer if any and set new one */
  163. bytes_left = (data->blocksize * data->blocks);
  164. /* Reset FIFO - Always use 32 byte fifo threshold */
  165. set_val(&regs->mmcfifoctl,
  166. (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
  167. cmddata |= MMCCMD_DMATRIG;
  168. cmddata |= MMCCMD_WDATX;
  169. if (data->flags == MMC_DATA_READ) {
  170. set_val(&regs->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
  171. } else if (data->flags == MMC_DATA_WRITE) {
  172. set_val(&regs->mmcfifoctl,
  173. (MMCFIFOCTL_FIFOLEV |
  174. MMCFIFOCTL_FIFODIR));
  175. cmddata |= MMCCMD_DTRW;
  176. }
  177. set_val(&regs->mmctod, 0xFFFF);
  178. set_val(&regs->mmcnblk, (data->blocks & MMCNBLK_NBLK_MASK));
  179. set_val(&regs->mmcblen, (data->blocksize & MMCBLEN_BLEN_MASK));
  180. if (data->flags == MMC_DATA_WRITE) {
  181. uint val;
  182. data_buf = (char *)data->src;
  183. /* For write, fill FIFO with data before issue of CMD */
  184. for (i = 0; (i < fifo_words) && bytes_left; i++) {
  185. memcpy((char *)&val, data_buf, 4);
  186. set_val(&regs->mmcdxr, val);
  187. data_buf += 4;
  188. bytes_left -= 4;
  189. }
  190. }
  191. } else {
  192. set_val(&regs->mmcblen, 0);
  193. set_val(&regs->mmcnblk, 0);
  194. }
  195. set_val(&regs->mmctor, 0x1FFF);
  196. /* Send the command */
  197. set_val(&regs->mmcarghl, cmd->cmdarg);
  198. set_val(&regs->mmccmd, cmddata);
  199. status_rdy = MMCST0_RSPDNE;
  200. status_err = (MMCST0_TOUTRS | MMCST0_TOUTRD |
  201. MMCST0_CRCWR | MMCST0_CRCRD);
  202. if (cmd->resp_type & MMC_RSP_CRC)
  203. status_err |= MMCST0_CRCRS;
  204. mmcstatus = get_val(&regs->mmcst0);
  205. err = dmmc_check_status(regs, &mmcstatus, status_rdy, status_err);
  206. if (err)
  207. return err;
  208. /* For R1b wait for busy done */
  209. if (cmd->resp_type == MMC_RSP_R1b)
  210. dmmc_busy_wait(regs);
  211. /* Collect response from controller for specific commands */
  212. if (mmcstatus & MMCST0_RSPDNE) {
  213. /* Copy the response to the response buffer */
  214. if (cmd->resp_type & MMC_RSP_136) {
  215. cmd->response[0] = get_val(&regs->mmcrsp67);
  216. cmd->response[1] = get_val(&regs->mmcrsp45);
  217. cmd->response[2] = get_val(&regs->mmcrsp23);
  218. cmd->response[3] = get_val(&regs->mmcrsp01);
  219. } else if (cmd->resp_type & MMC_RSP_PRESENT) {
  220. cmd->response[0] = get_val(&regs->mmcrsp67);
  221. }
  222. }
  223. if (data == NULL)
  224. return 0;
  225. if (data->flags == MMC_DATA_READ) {
  226. /* check for DATDNE along with DRRDY as the controller might
  227. * set the DATDNE without DRRDY for smaller transfers with
  228. * less than FIFO threshold bytes
  229. */
  230. status_rdy = MMCST0_DRRDY | MMCST0_DATDNE;
  231. status_err = MMCST0_TOUTRD | MMCST0_CRCRD;
  232. data_buf = data->dest;
  233. } else {
  234. status_rdy = MMCST0_DXRDY | MMCST0_DATDNE;
  235. status_err = MMCST0_CRCWR;
  236. }
  237. /* Wait until all of the blocks are transferred */
  238. while (bytes_left) {
  239. err = dmmc_check_status(regs, &mmcstatus, status_rdy,
  240. status_err);
  241. if (err)
  242. return err;
  243. if (data->flags == MMC_DATA_READ) {
  244. /*
  245. * MMC controller sets the Data receive ready bit
  246. * (DRRDY) in MMCST0 even before the entire FIFO is
  247. * full. This results in erratic behavior if we start
  248. * reading the FIFO soon after DRRDY. Wait for the
  249. * FIFO full bit in MMCST1 for proper FIFO clearing.
  250. */
  251. if (bytes_left > fifo_bytes)
  252. dmmc_wait_fifo_status(regs, 0x4a);
  253. else if (bytes_left == fifo_bytes) {
  254. dmmc_wait_fifo_status(regs, 0x40);
  255. if (cmd->cmdidx == MMC_CMD_SEND_EXT_CSD)
  256. udelay(600);
  257. }
  258. for (i = 0; bytes_left && (i < fifo_words); i++) {
  259. cmddata = get_val(&regs->mmcdrr);
  260. memcpy(data_buf, (char *)&cmddata, 4);
  261. data_buf += 4;
  262. bytes_left -= 4;
  263. }
  264. } else {
  265. /*
  266. * MMC controller sets the Data transmit ready bit
  267. * (DXRDY) in MMCST0 even before the entire FIFO is
  268. * empty. This results in erratic behavior if we start
  269. * writing the FIFO soon after DXRDY. Wait for the
  270. * FIFO empty bit in MMCST1 for proper FIFO clearing.
  271. */
  272. dmmc_wait_fifo_status(regs, MMCST1_FIFOEMP);
  273. for (i = 0; bytes_left && (i < fifo_words); i++) {
  274. memcpy((char *)&cmddata, data_buf, 4);
  275. set_val(&regs->mmcdxr, cmddata);
  276. data_buf += 4;
  277. bytes_left -= 4;
  278. }
  279. dmmc_busy_wait(regs);
  280. }
  281. }
  282. err = dmmc_check_status(regs, &mmcstatus, MMCST0_DATDNE, status_err);
  283. if (err)
  284. return err;
  285. return 0;
  286. }
  287. /* Initialize Davinci MMC controller */
  288. #if !CONFIG_IS_ENABLED(DM_MMC)
  289. static int dmmc_init(struct mmc *mmc)
  290. {
  291. struct davinci_mmc *host = mmc->priv;
  292. #else
  293. static int davinci_dm_mmc_init(struct udevice *dev)
  294. {
  295. struct davinci_mmc_priv *host = dev_get_priv(dev);
  296. #endif
  297. struct davinci_mmc_regs *regs = host->reg_base;
  298. /* Clear status registers explicitly - soft reset doesn't clear it
  299. * If Uboot is invoked from UBL with SDMMC Support, the status
  300. * registers can have uncleared bits
  301. */
  302. get_val(&regs->mmcst0);
  303. get_val(&regs->mmcst1);
  304. /* Hold software reset */
  305. set_bit(&regs->mmcctl, MMCCTL_DATRST);
  306. set_bit(&regs->mmcctl, MMCCTL_CMDRST);
  307. udelay(10);
  308. set_val(&regs->mmcclk, 0x0);
  309. set_val(&regs->mmctor, 0x1FFF);
  310. set_val(&regs->mmctod, 0xFFFF);
  311. /* Clear software reset */
  312. clear_bit(&regs->mmcctl, MMCCTL_DATRST);
  313. clear_bit(&regs->mmcctl, MMCCTL_CMDRST);
  314. udelay(10);
  315. /* Reset FIFO - Always use the maximum fifo threshold */
  316. set_val(&regs->mmcfifoctl, (MMCFIFOCTL_FIFOLEV | MMCFIFOCTL_FIFORST));
  317. set_val(&regs->mmcfifoctl, MMCFIFOCTL_FIFOLEV);
  318. return 0;
  319. }
  320. /* Set buswidth or clock as indicated by the MMC framework */
  321. #if !CONFIG_IS_ENABLED(DM_MMC)
  322. static int dmmc_set_ios(struct mmc *mmc)
  323. {
  324. struct davinci_mmc *host = mmc->priv;
  325. struct davinci_mmc_regs *regs = host->reg_base;
  326. #else
  327. static int davinci_mmc_set_ios(struct udevice *dev)
  328. {
  329. struct mmc *mmc = mmc_get_mmc_dev(dev);
  330. struct davinci_mmc_priv *host = dev_get_priv(dev);
  331. struct davinci_mmc_regs *regs = host->reg_base;
  332. #endif
  333. /* Set the bus width */
  334. if (mmc->bus_width == 4)
  335. set_bit(&regs->mmcctl, MMCCTL_WIDTH_4_BIT);
  336. else
  337. clear_bit(&regs->mmcctl, MMCCTL_WIDTH_4_BIT);
  338. /* Set clock speed */
  339. if (mmc->clock) {
  340. #if !CONFIG_IS_ENABLED(DM_MMC)
  341. dmmc_set_clock(mmc, mmc->clock);
  342. #else
  343. davinci_mmc_set_clock(dev, mmc->clock);
  344. #endif
  345. }
  346. return 0;
  347. }
  348. #if !CONFIG_IS_ENABLED(DM_MMC)
  349. static const struct mmc_ops dmmc_ops = {
  350. .send_cmd = dmmc_send_cmd,
  351. .set_ios = dmmc_set_ios,
  352. .init = dmmc_init,
  353. };
  354. #else
  355. static int davinci_mmc_getcd(struct udevice *dev)
  356. {
  357. int value = -1;
  358. #if CONFIG_IS_ENABLED(DM_GPIO)
  359. struct davinci_mmc_priv *priv = dev_get_priv(dev);
  360. value = dm_gpio_get_value(&priv->cd_gpio);
  361. #endif
  362. /* if no CD return as 1 */
  363. if (value < 0)
  364. return 1;
  365. return value;
  366. }
  367. static int davinci_mmc_getwp(struct udevice *dev)
  368. {
  369. int value = -1;
  370. #if CONFIG_IS_ENABLED(DM_GPIO)
  371. struct davinci_mmc_priv *priv = dev_get_priv(dev);
  372. value = dm_gpio_get_value(&priv->wp_gpio);
  373. #endif
  374. /* if no WP return as 0 */
  375. if (value < 0)
  376. return 0;
  377. return value;
  378. }
  379. static const struct dm_mmc_ops davinci_mmc_ops = {
  380. .send_cmd = davinci_mmc_send_cmd,
  381. .set_ios = davinci_mmc_set_ios,
  382. .get_cd = davinci_mmc_getcd,
  383. .get_wp = davinci_mmc_getwp,
  384. };
  385. #endif
  386. #if !CONFIG_IS_ENABLED(DM_MMC)
  387. /* Called from board_mmc_init during startup. Can be called multiple times
  388. * depending on the number of slots available on board and controller
  389. */
  390. int davinci_mmc_init(struct bd_info *bis, struct davinci_mmc *host)
  391. {
  392. host->cfg.name = "davinci";
  393. host->cfg.ops = &dmmc_ops;
  394. host->cfg.f_min = 200000;
  395. host->cfg.f_max = 25000000;
  396. host->cfg.voltages = host->voltages;
  397. host->cfg.host_caps = host->host_caps;
  398. host->cfg.b_max = DAVINCI_MAX_BLOCKS;
  399. mmc_create(&host->cfg, host);
  400. return 0;
  401. }
  402. #else
  403. static int davinci_mmc_probe(struct udevice *dev)
  404. {
  405. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  406. struct davinci_mmc_plat *plat = dev_get_platdata(dev);
  407. struct davinci_mmc_priv *priv = dev_get_priv(dev);
  408. priv->reg_base = plat->reg_base;
  409. priv->input_clk = clk_get(DAVINCI_MMCSD_CLKID);
  410. #if CONFIG_IS_ENABLED(DM_GPIO)
  411. /* These GPIOs are optional */
  412. gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
  413. gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
  414. #endif
  415. upriv->mmc = &plat->mmc;
  416. return davinci_dm_mmc_init(dev);
  417. }
  418. static int davinci_mmc_bind(struct udevice *dev)
  419. {
  420. struct davinci_mmc_plat *plat = dev_get_platdata(dev);
  421. return mmc_bind(dev, &plat->mmc, &plat->cfg);
  422. }
  423. #if CONFIG_IS_ENABLED(OF_CONTROL)
  424. static int davinci_mmc_ofdata_to_platdata(struct udevice *dev)
  425. {
  426. struct davinci_mmc_plat *plat = dev_get_platdata(dev);
  427. struct mmc_config *cfg = &plat->cfg;
  428. plat->reg_base = (struct davinci_mmc_regs *)dev_read_addr(dev);
  429. cfg->f_min = 200000;
  430. cfg->f_max = 25000000;
  431. cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34,
  432. cfg->host_caps = MMC_MODE_4BIT, /* DA850 supports only 4-bit SD/MMC */
  433. cfg->b_max = DAVINCI_MAX_BLOCKS;
  434. cfg->name = "da830-mmc";
  435. return 0;
  436. }
  437. static const struct udevice_id davinci_mmc_ids[] = {
  438. { .compatible = "ti,da830-mmc" },
  439. {},
  440. };
  441. #endif
  442. U_BOOT_DRIVER(ti_da830_mmc) = {
  443. .name = "davinci_mmc",
  444. .id = UCLASS_MMC,
  445. #if CONFIG_IS_ENABLED(OF_CONTROL)
  446. .of_match = davinci_mmc_ids,
  447. .platdata_auto_alloc_size = sizeof(struct davinci_mmc_plat),
  448. .ofdata_to_platdata = davinci_mmc_ofdata_to_platdata,
  449. #endif
  450. #if CONFIG_BLK
  451. .bind = davinci_mmc_bind,
  452. #endif
  453. .probe = davinci_mmc_probe,
  454. .ops = &davinci_mmc_ops,
  455. .priv_auto_alloc_size = sizeof(struct davinci_mmc_priv),
  456. #if !CONFIG_IS_ENABLED(OF_CONTROL)
  457. .flags = DM_FLAG_PRE_RELOC,
  458. #endif
  459. };
  460. #endif