am654_sdhci.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
  4. *
  5. * Texas Instruments' K3 SD Host Controller Interface
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <malloc.h>
  11. #include <power-domain.h>
  12. #include <regmap.h>
  13. #include <sdhci.h>
  14. #include <dm/device_compat.h>
  15. #include <linux/bitops.h>
  16. #include <linux/err.h>
  17. /* CTL_CFG Registers */
  18. #define CTL_CFG_2 0x14
  19. #define SLOTTYPE_MASK GENMASK(31, 30)
  20. #define SLOTTYPE_EMBEDDED BIT(30)
  21. /* PHY Registers */
  22. #define PHY_CTRL1 0x100
  23. #define PHY_CTRL2 0x104
  24. #define PHY_CTRL3 0x108
  25. #define PHY_CTRL4 0x10C
  26. #define PHY_CTRL5 0x110
  27. #define PHY_CTRL6 0x114
  28. #define PHY_STAT1 0x130
  29. #define PHY_STAT2 0x134
  30. #define IOMUX_ENABLE_SHIFT 31
  31. #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT)
  32. #define OTAPDLYENA_SHIFT 20
  33. #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT)
  34. #define OTAPDLYSEL_SHIFT 12
  35. #define OTAPDLYSEL_MASK GENMASK(15, 12)
  36. #define STRBSEL_SHIFT 24
  37. #define STRBSEL_4BIT_MASK GENMASK(27, 24)
  38. #define STRBSEL_8BIT_MASK GENMASK(31, 24)
  39. #define SEL50_SHIFT 8
  40. #define SEL50_MASK BIT(SEL50_SHIFT)
  41. #define SEL100_SHIFT 9
  42. #define SEL100_MASK BIT(SEL100_SHIFT)
  43. #define FREQSEL_SHIFT 8
  44. #define FREQSEL_MASK GENMASK(10, 8)
  45. #define DLL_TRIM_ICP_SHIFT 4
  46. #define DLL_TRIM_ICP_MASK GENMASK(7, 4)
  47. #define DR_TY_SHIFT 20
  48. #define DR_TY_MASK GENMASK(22, 20)
  49. #define ENDLL_SHIFT 1
  50. #define ENDLL_MASK BIT(ENDLL_SHIFT)
  51. #define DLLRDY_SHIFT 0
  52. #define DLLRDY_MASK BIT(DLLRDY_SHIFT)
  53. #define PDB_SHIFT 0
  54. #define PDB_MASK BIT(PDB_SHIFT)
  55. #define CALDONE_SHIFT 1
  56. #define CALDONE_MASK BIT(CALDONE_SHIFT)
  57. #define RETRIM_SHIFT 17
  58. #define RETRIM_MASK BIT(RETRIM_SHIFT)
  59. #define DRIVER_STRENGTH_50_OHM 0x0
  60. #define DRIVER_STRENGTH_33_OHM 0x1
  61. #define DRIVER_STRENGTH_66_OHM 0x2
  62. #define DRIVER_STRENGTH_100_OHM 0x3
  63. #define DRIVER_STRENGTH_40_OHM 0x4
  64. #define AM654_SDHCI_MIN_FREQ 400000
  65. struct am654_sdhci_plat {
  66. struct mmc_config cfg;
  67. struct mmc mmc;
  68. struct regmap *base;
  69. bool non_removable;
  70. u32 otap_del_sel[MMC_MODES_END];
  71. u32 trm_icp;
  72. u32 drv_strength;
  73. u32 strb_sel;
  74. u32 flags;
  75. #define DLL_PRESENT (1 << 0)
  76. #define IOMUX_PRESENT (1 << 1)
  77. #define FREQSEL_2_BIT (1 << 2)
  78. #define STRBSEL_4_BIT (1 << 3)
  79. bool dll_on;
  80. };
  81. struct timing_data {
  82. const char *binding;
  83. u32 capability;
  84. };
  85. static const struct timing_data td[] = {
  86. [MMC_LEGACY] = {"ti,otap-del-sel-legacy", 0},
  87. [MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP(MMC_HS)},
  88. [SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP(SD_HS)},
  89. [UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP(UHS_SDR12)},
  90. [UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP(UHS_SDR25)},
  91. [UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP(UHS_SDR50)},
  92. [UHS_SDR104] = {"ti,otap-del-sel-sdr104", MMC_CAP(UHS_SDR104)},
  93. [UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP(UHS_DDR50)},
  94. [MMC_DDR_52] = {"ti,otap-del-sel-ddr52", MMC_CAP(MMC_DDR_52)},
  95. [MMC_HS_200] = {"ti,otap-del-sel-hs200", MMC_CAP(MMC_HS_200)},
  96. [MMC_HS_400] = {"ti,otap-del-sel-hs400", MMC_CAP(MMC_HS_400)},
  97. };
  98. struct am654_driver_data {
  99. const struct sdhci_ops *ops;
  100. u32 flags;
  101. };
  102. static void am654_sdhci_set_control_reg(struct sdhci_host *host)
  103. {
  104. struct mmc *mmc = (struct mmc *)host->mmc;
  105. u32 reg;
  106. if (IS_SD(host->mmc) &&
  107. mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  108. reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  109. reg |= SDHCI_CTRL_VDD_180;
  110. sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  111. }
  112. sdhci_set_uhs_timing(host);
  113. }
  114. static int am654_sdhci_set_ios_post(struct sdhci_host *host)
  115. {
  116. struct udevice *dev = host->mmc->dev;
  117. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  118. unsigned int speed = host->mmc->clock;
  119. int sel50, sel100, freqsel;
  120. u32 otap_del_sel;
  121. u32 mask, val;
  122. int ret;
  123. /* Reset SD Clock Enable */
  124. val = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  125. val &= ~SDHCI_CLOCK_CARD_EN;
  126. sdhci_writew(host, val, SDHCI_CLOCK_CONTROL);
  127. /* power off phy */
  128. if (plat->dll_on) {
  129. regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK, 0);
  130. plat->dll_on = false;
  131. }
  132. /* restart clock */
  133. sdhci_set_clock(host->mmc, speed);
  134. /* switch phy back on */
  135. if (speed > AM654_SDHCI_MIN_FREQ) {
  136. otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
  137. mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
  138. val = (1 << OTAPDLYENA_SHIFT) |
  139. (otap_del_sel << OTAPDLYSEL_SHIFT);
  140. /* Write to STRBSEL for HS400 speed mode */
  141. if (host->mmc->selected_mode == MMC_HS_400) {
  142. if (plat->flags & STRBSEL_4_BIT)
  143. mask |= STRBSEL_4BIT_MASK;
  144. else
  145. mask |= STRBSEL_8BIT_MASK;
  146. val |= plat->strb_sel << STRBSEL_SHIFT;
  147. }
  148. regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
  149. if (plat->flags & FREQSEL_2_BIT) {
  150. switch (speed) {
  151. case 200000000:
  152. sel50 = 0;
  153. sel100 = 0;
  154. break;
  155. case 100000000:
  156. sel50 = 0;
  157. sel100 = 1;
  158. break;
  159. default:
  160. sel50 = 1;
  161. sel100 = 0;
  162. }
  163. /* Configure PHY DLL frequency */
  164. mask = SEL50_MASK | SEL100_MASK;
  165. val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT);
  166. regmap_update_bits(plat->base, PHY_CTRL5, mask, val);
  167. } else {
  168. switch (speed) {
  169. case 200000000:
  170. freqsel = 0x0;
  171. break;
  172. default:
  173. freqsel = 0x4;
  174. }
  175. regmap_update_bits(plat->base, PHY_CTRL5, FREQSEL_MASK,
  176. freqsel << FREQSEL_SHIFT);
  177. }
  178. /* Enable DLL */
  179. regmap_update_bits(plat->base, PHY_CTRL1, ENDLL_MASK,
  180. 0x1 << ENDLL_SHIFT);
  181. /*
  182. * Poll for DLL ready. Use a one second timeout.
  183. * Works in all experiments done so far
  184. */
  185. ret = regmap_read_poll_timeout(plat->base, PHY_STAT1, val,
  186. val & DLLRDY_MASK, 1000, 1000000);
  187. if (ret)
  188. return ret;
  189. plat->dll_on = true;
  190. }
  191. return 0;
  192. }
  193. int am654_sdhci_init(struct am654_sdhci_plat *plat)
  194. {
  195. u32 ctl_cfg_2 = 0;
  196. u32 mask, val;
  197. int ret;
  198. /* Reset OTAP to default value */
  199. mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
  200. regmap_update_bits(plat->base, PHY_CTRL4, mask, 0x0);
  201. if (plat->flags & DLL_PRESENT) {
  202. regmap_read(plat->base, PHY_STAT1, &val);
  203. if (~val & CALDONE_MASK) {
  204. /* Calibrate IO lines */
  205. regmap_update_bits(plat->base, PHY_CTRL1, PDB_MASK,
  206. PDB_MASK);
  207. ret = regmap_read_poll_timeout(plat->base, PHY_STAT1,
  208. val, val & CALDONE_MASK,
  209. 1, 20);
  210. if (ret)
  211. return ret;
  212. }
  213. /* Configure DLL TRIM */
  214. mask = DLL_TRIM_ICP_MASK;
  215. val = plat->trm_icp << DLL_TRIM_ICP_SHIFT;
  216. /* Configure DLL driver strength */
  217. mask |= DR_TY_MASK;
  218. val |= plat->drv_strength << DR_TY_SHIFT;
  219. regmap_update_bits(plat->base, PHY_CTRL1, mask, val);
  220. }
  221. /* Enable pins by setting IO mux to 0 */
  222. if (plat->flags & IOMUX_PRESENT)
  223. regmap_update_bits(plat->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0);
  224. /* Set slot type based on SD or eMMC */
  225. if (plat->non_removable)
  226. ctl_cfg_2 = SLOTTYPE_EMBEDDED;
  227. regmap_update_bits(plat->base, CTL_CFG_2, SLOTTYPE_MASK, ctl_cfg_2);
  228. return 0;
  229. }
  230. #define MAX_SDCD_DEBOUNCE_TIME 2000
  231. static int am654_sdhci_deferred_probe(struct sdhci_host *host)
  232. {
  233. struct udevice *dev = host->mmc->dev;
  234. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  235. unsigned long start;
  236. int val;
  237. /*
  238. * The controller takes about 1 second to debounce the card detect line
  239. * and doesn't let us power on until that time is up. Instead of waiting
  240. * for 1 second at every stage, poll on the CARD_PRESENT bit upto a
  241. * maximum of 2 seconds to be safe..
  242. */
  243. start = get_timer(0);
  244. do {
  245. if (get_timer(start) > MAX_SDCD_DEBOUNCE_TIME)
  246. return -ENOMEDIUM;
  247. val = mmc_getcd(host->mmc);
  248. } while (!val);
  249. am654_sdhci_init(plat);
  250. return sdhci_probe(dev);
  251. }
  252. const struct sdhci_ops am654_sdhci_ops = {
  253. .deferred_probe = am654_sdhci_deferred_probe,
  254. .set_ios_post = &am654_sdhci_set_ios_post,
  255. .set_control_reg = &am654_sdhci_set_control_reg,
  256. };
  257. const struct am654_driver_data am654_drv_data = {
  258. .ops = &am654_sdhci_ops,
  259. .flags = IOMUX_PRESENT | FREQSEL_2_BIT | DLL_PRESENT | STRBSEL_4_BIT,
  260. };
  261. const struct am654_driver_data j721e_8bit_drv_data = {
  262. .ops = &am654_sdhci_ops,
  263. .flags = DLL_PRESENT,
  264. };
  265. static int j721e_4bit_sdhci_set_ios_post(struct sdhci_host *host)
  266. {
  267. struct udevice *dev = host->mmc->dev;
  268. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  269. u32 otap_del_sel, mask, val;
  270. otap_del_sel = plat->otap_del_sel[host->mmc->selected_mode];
  271. mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK;
  272. val = (1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT);
  273. regmap_update_bits(plat->base, PHY_CTRL4, mask, val);
  274. return 0;
  275. }
  276. const struct sdhci_ops j721e_4bit_sdhci_ops = {
  277. .deferred_probe = am654_sdhci_deferred_probe,
  278. .set_ios_post = &j721e_4bit_sdhci_set_ios_post,
  279. };
  280. const struct am654_driver_data j721e_4bit_drv_data = {
  281. .ops = &j721e_4bit_sdhci_ops,
  282. .flags = IOMUX_PRESENT,
  283. };
  284. static int sdhci_am654_get_otap_delay(struct udevice *dev,
  285. struct mmc_config *cfg)
  286. {
  287. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  288. int ret;
  289. int i;
  290. /* ti,otap-del-sel-legacy is mandatory */
  291. ret = dev_read_u32(dev, "ti,otap-del-sel-legacy",
  292. &plat->otap_del_sel[0]);
  293. if (ret)
  294. return ret;
  295. /*
  296. * Remove the corresponding capability if an otap-del-sel
  297. * value is not found
  298. */
  299. for (i = MMC_HS; i <= MMC_HS_400; i++) {
  300. ret = dev_read_u32(dev, td[i].binding, &plat->otap_del_sel[i]);
  301. if (ret) {
  302. dev_dbg(dev, "Couldn't find %s\n", td[i].binding);
  303. /*
  304. * Remove the corresponding capability
  305. * if an otap-del-sel value is not found
  306. */
  307. cfg->host_caps &= ~td[i].capability;
  308. }
  309. }
  310. return 0;
  311. }
  312. static int am654_sdhci_probe(struct udevice *dev)
  313. {
  314. struct am654_driver_data *drv_data =
  315. (struct am654_driver_data *)dev_get_driver_data(dev);
  316. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  317. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  318. struct sdhci_host *host = dev_get_priv(dev);
  319. struct mmc_config *cfg = &plat->cfg;
  320. struct clk clk;
  321. unsigned long clock;
  322. int ret;
  323. ret = clk_get_by_name(dev, "clk_xin", &clk);
  324. if (ret) {
  325. dev_err(dev, "failed to get clock\n");
  326. return ret;
  327. }
  328. clock = clk_get_rate(&clk);
  329. if (IS_ERR_VALUE(clock)) {
  330. dev_err(dev, "failed to get rate\n");
  331. return clock;
  332. }
  333. host->max_clk = clock;
  334. host->mmc = &plat->mmc;
  335. host->mmc->dev = dev;
  336. ret = sdhci_setup_cfg(cfg, host, cfg->f_max,
  337. AM654_SDHCI_MIN_FREQ);
  338. if (ret)
  339. return ret;
  340. ret = sdhci_am654_get_otap_delay(dev, cfg);
  341. if (ret)
  342. return ret;
  343. host->ops = drv_data->ops;
  344. host->mmc->priv = host;
  345. upriv->mmc = host->mmc;
  346. regmap_init_mem_index(dev_ofnode(dev), &plat->base, 1);
  347. return 0;
  348. }
  349. static int am654_sdhci_ofdata_to_platdata(struct udevice *dev)
  350. {
  351. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  352. struct sdhci_host *host = dev_get_priv(dev);
  353. struct mmc_config *cfg = &plat->cfg;
  354. u32 drv_strength;
  355. int ret;
  356. host->name = dev->name;
  357. host->ioaddr = (void *)dev_read_addr(dev);
  358. plat->non_removable = dev_read_bool(dev, "non-removable");
  359. if (plat->flags & DLL_PRESENT) {
  360. ret = dev_read_u32(dev, "ti,trm-icp", &plat->trm_icp);
  361. if (ret)
  362. return ret;
  363. ret = dev_read_u32(dev, "ti,driver-strength-ohm",
  364. &drv_strength);
  365. if (ret)
  366. return ret;
  367. switch (drv_strength) {
  368. case 50:
  369. plat->drv_strength = DRIVER_STRENGTH_50_OHM;
  370. break;
  371. case 33:
  372. plat->drv_strength = DRIVER_STRENGTH_33_OHM;
  373. break;
  374. case 66:
  375. plat->drv_strength = DRIVER_STRENGTH_66_OHM;
  376. break;
  377. case 100:
  378. plat->drv_strength = DRIVER_STRENGTH_100_OHM;
  379. break;
  380. case 40:
  381. plat->drv_strength = DRIVER_STRENGTH_40_OHM;
  382. break;
  383. default:
  384. dev_err(dev, "Invalid driver strength\n");
  385. return -EINVAL;
  386. }
  387. }
  388. ret = mmc_of_parse(dev, cfg);
  389. if (ret)
  390. return ret;
  391. return 0;
  392. }
  393. static int am654_sdhci_bind(struct udevice *dev)
  394. {
  395. struct am654_driver_data *drv_data =
  396. (struct am654_driver_data *)dev_get_driver_data(dev);
  397. struct am654_sdhci_plat *plat = dev_get_platdata(dev);
  398. plat->flags = drv_data->flags;
  399. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  400. }
  401. static const struct udevice_id am654_sdhci_ids[] = {
  402. {
  403. .compatible = "ti,am654-sdhci-5.1",
  404. .data = (ulong)&am654_drv_data,
  405. },
  406. {
  407. .compatible = "ti,j721e-sdhci-8bit",
  408. .data = (ulong)&j721e_8bit_drv_data,
  409. },
  410. {
  411. .compatible = "ti,j721e-sdhci-4bit",
  412. .data = (ulong)&j721e_4bit_drv_data,
  413. },
  414. { }
  415. };
  416. U_BOOT_DRIVER(am654_sdhci_drv) = {
  417. .name = "am654_sdhci",
  418. .id = UCLASS_MMC,
  419. .of_match = am654_sdhci_ids,
  420. .ofdata_to_platdata = am654_sdhci_ofdata_to_platdata,
  421. .ops = &sdhci_ops,
  422. .bind = am654_sdhci_bind,
  423. .probe = am654_sdhci_probe,
  424. .priv_auto_alloc_size = sizeof(struct sdhci_host),
  425. .platdata_auto_alloc_size = sizeof(struct am654_sdhci_plat),
  426. };