fsl_iim.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009-2013 ADVANSEE
  4. * Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
  5. *
  6. * Based on the mpc512x iim code:
  7. * Copyright 2008 Silicon Turnkey Express, Inc.
  8. * Martha Marx <mmarx@silicontkx.com>
  9. */
  10. #include <common.h>
  11. #include <fuse.h>
  12. #include <linux/delay.h>
  13. #include <linux/errno.h>
  14. #include <asm/io.h>
  15. #include <asm/arch/imx-regs.h>
  16. #if defined(CONFIG_MX51) || defined(CONFIG_MX53)
  17. #include <asm/arch/clock.h>
  18. #endif
  19. /* FSL IIM-specific constants */
  20. #define STAT_BUSY 0x80
  21. #define STAT_PRGD 0x02
  22. #define STAT_SNSD 0x01
  23. #define STATM_PRGD_M 0x02
  24. #define STATM_SNSD_M 0x01
  25. #define ERR_PRGE 0x80
  26. #define ERR_WPE 0x40
  27. #define ERR_OPE 0x20
  28. #define ERR_RPE 0x10
  29. #define ERR_WLRE 0x08
  30. #define ERR_SNSE 0x04
  31. #define ERR_PARITYE 0x02
  32. #define EMASK_PRGE_M 0x80
  33. #define EMASK_WPE_M 0x40
  34. #define EMASK_OPE_M 0x20
  35. #define EMASK_RPE_M 0x10
  36. #define EMASK_WLRE_M 0x08
  37. #define EMASK_SNSE_M 0x04
  38. #define EMASK_PARITYE_M 0x02
  39. #define FCTL_DPC 0x80
  40. #define FCTL_PRG_LENGTH_MASK 0x70
  41. #define FCTL_ESNS_N 0x08
  42. #define FCTL_ESNS_0 0x04
  43. #define FCTL_ESNS_1 0x02
  44. #define FCTL_PRG 0x01
  45. #define UA_A_BANK_MASK 0x38
  46. #define UA_A_ROWH_MASK 0x07
  47. #define LA_A_ROWL_MASK 0xf8
  48. #define LA_A_BIT_MASK 0x07
  49. #define PREV_PROD_REV_MASK 0xf8
  50. #define PREV_PROD_VT_MASK 0x07
  51. /* Select the correct accessors depending on endianness */
  52. #if __BYTE_ORDER == __LITTLE_ENDIAN
  53. #define iim_read32 in_le32
  54. #define iim_write32 out_le32
  55. #define iim_clrsetbits32 clrsetbits_le32
  56. #define iim_clrbits32 clrbits_le32
  57. #define iim_setbits32 setbits_le32
  58. #elif __BYTE_ORDER == __BIG_ENDIAN
  59. #define iim_read32 in_be32
  60. #define iim_write32 out_be32
  61. #define iim_clrsetbits32 clrsetbits_be32
  62. #define iim_clrbits32 clrbits_be32
  63. #define iim_setbits32 setbits_be32
  64. #else
  65. #error Endianess is not defined: please fix to continue
  66. #endif
  67. /* IIM control registers */
  68. struct fsl_iim {
  69. u32 stat;
  70. u32 statm;
  71. u32 err;
  72. u32 emask;
  73. u32 fctl;
  74. u32 ua;
  75. u32 la;
  76. u32 sdat;
  77. u32 prev;
  78. u32 srev;
  79. u32 prg_p;
  80. u32 scs[0x1f5];
  81. struct {
  82. u32 word[0x100];
  83. } bank[8];
  84. };
  85. #if !defined(CONFIG_MX51) && !defined(CONFIG_MX53)
  86. #define enable_efuse_prog_supply(enable)
  87. #endif
  88. static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert,
  89. const char *caller)
  90. {
  91. *regs = (struct fsl_iim *)IIM_BASE_ADDR;
  92. if (bank >= ARRAY_SIZE((*regs)->bank) ||
  93. word >= ARRAY_SIZE((*regs)->bank[0].word) ||
  94. !assert) {
  95. printf("fsl_iim %s(): Invalid argument\n", caller);
  96. return -EINVAL;
  97. }
  98. return 0;
  99. }
  100. static void clear_status(struct fsl_iim *regs)
  101. {
  102. iim_setbits32(&regs->stat, 0);
  103. iim_setbits32(&regs->err, 0);
  104. }
  105. static void finish_access(struct fsl_iim *regs, u32 *stat, u32 *err)
  106. {
  107. *stat = iim_read32(&regs->stat);
  108. *err = iim_read32(&regs->err);
  109. clear_status(regs);
  110. }
  111. static int prepare_read(struct fsl_iim **regs, u32 bank, u32 word, u32 *val,
  112. const char *caller)
  113. {
  114. int ret;
  115. ret = prepare_access(regs, bank, word, val != NULL, caller);
  116. if (ret)
  117. return ret;
  118. clear_status(*regs);
  119. return 0;
  120. }
  121. int fuse_read(u32 bank, u32 word, u32 *val)
  122. {
  123. struct fsl_iim *regs;
  124. u32 stat, err;
  125. int ret;
  126. ret = prepare_read(&regs, bank, word, val, __func__);
  127. if (ret)
  128. return ret;
  129. *val = iim_read32(&regs->bank[bank].word[word]);
  130. finish_access(regs, &stat, &err);
  131. if (err & ERR_RPE) {
  132. puts("fsl_iim fuse_read(): Read protect error\n");
  133. return -EIO;
  134. }
  135. return 0;
  136. }
  137. static void direct_access(struct fsl_iim *regs, u32 bank, u32 word, u32 bit,
  138. u32 fctl, u32 *stat, u32 *err)
  139. {
  140. iim_write32(&regs->ua, bank << 3 | word >> 5);
  141. iim_write32(&regs->la, (word << 3 | bit) & 0xff);
  142. if (fctl == FCTL_PRG)
  143. iim_write32(&regs->prg_p, 0xaa);
  144. iim_setbits32(&regs->fctl, fctl);
  145. while (iim_read32(&regs->stat) & STAT_BUSY)
  146. udelay(20);
  147. finish_access(regs, stat, err);
  148. }
  149. int fuse_sense(u32 bank, u32 word, u32 *val)
  150. {
  151. struct fsl_iim *regs;
  152. u32 stat, err;
  153. int ret;
  154. ret = prepare_read(&regs, bank, word, val, __func__);
  155. if (ret)
  156. return ret;
  157. direct_access(regs, bank, word, 0, FCTL_ESNS_N, &stat, &err);
  158. if (err & ERR_SNSE) {
  159. puts("fsl_iim fuse_sense(): Explicit sense cycle error\n");
  160. return -EIO;
  161. }
  162. if (!(stat & STAT_SNSD)) {
  163. puts("fsl_iim fuse_sense(): Explicit sense cycle did not complete\n");
  164. return -EIO;
  165. }
  166. *val = iim_read32(&regs->sdat);
  167. return 0;
  168. }
  169. static int prog_bit(struct fsl_iim *regs, u32 bank, u32 word, u32 bit)
  170. {
  171. u32 stat, err;
  172. clear_status(regs);
  173. direct_access(regs, bank, word, bit, FCTL_PRG, &stat, &err);
  174. iim_write32(&regs->prg_p, 0x00);
  175. if (err & ERR_PRGE) {
  176. puts("fsl_iim fuse_prog(): Program error\n");
  177. return -EIO;
  178. }
  179. if (err & ERR_WPE) {
  180. puts("fsl_iim fuse_prog(): Write protect error\n");
  181. return -EIO;
  182. }
  183. if (!(stat & STAT_PRGD)) {
  184. puts("fsl_iim fuse_prog(): Program did not complete\n");
  185. return -EIO;
  186. }
  187. return 0;
  188. }
  189. static int prepare_write(struct fsl_iim **regs, u32 bank, u32 word, u32 val,
  190. const char *caller)
  191. {
  192. return prepare_access(regs, bank, word, !(val & ~0xff), caller);
  193. }
  194. int fuse_prog(u32 bank, u32 word, u32 val)
  195. {
  196. struct fsl_iim *regs;
  197. u32 bit;
  198. int ret;
  199. ret = prepare_write(&regs, bank, word, val, __func__);
  200. if (ret)
  201. return ret;
  202. enable_efuse_prog_supply(1);
  203. for (bit = 0; val; bit++, val >>= 1)
  204. if (val & 0x01) {
  205. ret = prog_bit(regs, bank, word, bit);
  206. if (ret) {
  207. enable_efuse_prog_supply(0);
  208. return ret;
  209. }
  210. }
  211. enable_efuse_prog_supply(0);
  212. return 0;
  213. }
  214. int fuse_override(u32 bank, u32 word, u32 val)
  215. {
  216. struct fsl_iim *regs;
  217. u32 stat, err;
  218. int ret;
  219. ret = prepare_write(&regs, bank, word, val, __func__);
  220. if (ret)
  221. return ret;
  222. clear_status(regs);
  223. iim_write32(&regs->bank[bank].word[word], val);
  224. finish_access(regs, &stat, &err);
  225. if (err & ERR_OPE) {
  226. puts("fsl_iim fuse_override(): Override protect error\n");
  227. return -EIO;
  228. }
  229. return 0;
  230. }