Kconfig 16 KB

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  1. #
  2. # Multifunction miscellaneous devices
  3. #
  4. menu "Multifunction device drivers"
  5. config MISC
  6. bool "Enable Driver Model for Misc drivers"
  7. depends on DM
  8. help
  9. Enable driver model for miscellaneous devices. This class is
  10. used only for those do not fit other more general classes. A
  11. set of generic read, write and ioctl methods may be used to
  12. access the device.
  13. config SPL_MISC
  14. bool "Enable Driver Model for Misc drivers in SPL"
  15. depends on SPL_DM
  16. help
  17. Enable driver model for miscellaneous devices. This class is
  18. used only for those do not fit other more general classes. A
  19. set of generic read, write and ioctl methods may be used to
  20. access the device.
  21. config TPL_MISC
  22. bool "Enable Driver Model for Misc drivers in TPL"
  23. depends on TPL_DM
  24. help
  25. Enable driver model for miscellaneous devices. This class is
  26. used only for those do not fit other more general classes. A
  27. set of generic read, write and ioctl methods may be used to
  28. access the device.
  29. config ALTERA_SYSID
  30. bool "Altera Sysid support"
  31. depends on MISC
  32. help
  33. Select this to enable a sysid for Altera devices. Please find
  34. details on the "Embedded Peripherals IP User Guide" of Altera.
  35. config ATSHA204A
  36. bool "Support for Atmel ATSHA204A module"
  37. depends on MISC
  38. help
  39. Enable support for I2C connected Atmel's ATSHA204A
  40. CryptoAuthentication module found for example on the Turris Omnia
  41. board.
  42. config ROCKCHIP_EFUSE
  43. bool "Rockchip e-fuse support"
  44. depends on MISC
  45. help
  46. Enable (read-only) access for the e-fuse block found in Rockchip
  47. SoCs: accesses can either be made using byte addressing and a length
  48. or through child-nodes that are generated based on the e-fuse map
  49. retrieved from the DTS.
  50. This driver currently supports the RK3399 only, but can easily be
  51. extended (by porting the read function from the Linux kernel sources)
  52. to support other recent Rockchip devices.
  53. config ROCKCHIP_OTP
  54. bool "Rockchip OTP Support"
  55. depends on MISC
  56. help
  57. Enable (read-only) access for the one-time-programmable memory block
  58. found in Rockchip SoCs: accesses can either be made using byte
  59. addressing and a length or through child-nodes that are generated
  60. based on the e-fuse map retrieved from the DTS.
  61. config SIFIVE_OTP
  62. bool "SiFive eMemory OTP driver"
  63. depends on MISC
  64. help
  65. Enable support for reading and writing the eMemory OTP on the
  66. SiFive SoCs.
  67. config VEXPRESS_CONFIG
  68. bool "Enable support for Arm Versatile Express config bus"
  69. depends on MISC
  70. help
  71. If you say Y here, you will get support for accessing the
  72. configuration bus on the Arm Versatile Express boards via
  73. a sysreg driver.
  74. config CMD_CROS_EC
  75. bool "Enable crosec command"
  76. depends on CROS_EC
  77. help
  78. Enable command-line access to the Chrome OS EC (Embedded
  79. Controller). This provides the 'crosec' command which has
  80. a number of sub-commands for performing EC tasks such as
  81. updating its flash, accessing a small saved context area
  82. and talking to the I2C bus behind the EC (if there is one).
  83. config CROS_EC
  84. bool "Enable Chrome OS EC"
  85. help
  86. Enable access to the Chrome OS EC. This is a separate
  87. microcontroller typically available on a SPI bus on Chromebooks. It
  88. provides access to the keyboard, some internal storage and may
  89. control access to the battery and main PMIC depending on the
  90. device. You can use the 'crosec' command to access it.
  91. config SPL_CROS_EC
  92. bool "Enable Chrome OS EC in SPL"
  93. depends on SPL
  94. help
  95. Enable access to the Chrome OS EC in SPL. This is a separate
  96. microcontroller typically available on a SPI bus on Chromebooks. It
  97. provides access to the keyboard, some internal storage and may
  98. control access to the battery and main PMIC depending on the
  99. device. You can use the 'crosec' command to access it.
  100. config TPL_CROS_EC
  101. bool "Enable Chrome OS EC in TPL"
  102. depends on TPL
  103. help
  104. Enable access to the Chrome OS EC in TPL. This is a separate
  105. microcontroller typically available on a SPI bus on Chromebooks. It
  106. provides access to the keyboard, some internal storage and may
  107. control access to the battery and main PMIC depending on the
  108. device. You can use the 'crosec' command to access it.
  109. config CROS_EC_I2C
  110. bool "Enable Chrome OS EC I2C driver"
  111. depends on CROS_EC
  112. help
  113. Enable I2C access to the Chrome OS EC. This is used on older
  114. ARM Chromebooks such as snow and spring before the standard bus
  115. changed to SPI. The EC will accept commands across the I2C using
  116. a special message protocol, and provide responses.
  117. config CROS_EC_LPC
  118. bool "Enable Chrome OS EC LPC driver"
  119. depends on CROS_EC
  120. help
  121. Enable I2C access to the Chrome OS EC. This is used on x86
  122. Chromebooks such as link and falco. The keyboard is provided
  123. through a legacy port interface, so on x86 machines the main
  124. function of the EC is power and thermal management.
  125. config SPL_CROS_EC_LPC
  126. bool "Enable Chrome OS EC LPC driver in SPL"
  127. depends on CROS_EC
  128. help
  129. Enable I2C access to the Chrome OS EC. This is used on x86
  130. Chromebooks such as link and falco. The keyboard is provided
  131. through a legacy port interface, so on x86 machines the main
  132. function of the EC is power and thermal management.
  133. config TPL_CROS_EC_LPC
  134. bool "Enable Chrome OS EC LPC driver in TPL"
  135. depends on CROS_EC
  136. help
  137. Enable I2C access to the Chrome OS EC. This is used on x86
  138. Chromebooks such as link and falco. The keyboard is provided
  139. through a legacy port interface, so on x86 machines the main
  140. function of the EC is power and thermal management.
  141. config CROS_EC_SANDBOX
  142. bool "Enable Chrome OS EC sandbox driver"
  143. depends on CROS_EC && SANDBOX
  144. help
  145. Enable a sandbox emulation of the Chrome OS EC. This supports
  146. keyboard (use the -l flag to enable the LCD), verified boot context,
  147. EC flash read/write/erase support and a few other things. It is
  148. enough to perform a Chrome OS verified boot on sandbox.
  149. config SPL_CROS_EC_SANDBOX
  150. bool "Enable Chrome OS EC sandbox driver in SPL"
  151. depends on SPL_CROS_EC && SANDBOX
  152. help
  153. Enable a sandbox emulation of the Chrome OS EC in SPL. This supports
  154. keyboard (use the -l flag to enable the LCD), verified boot context,
  155. EC flash read/write/erase support and a few other things. It is
  156. enough to perform a Chrome OS verified boot on sandbox.
  157. config TPL_CROS_EC_SANDBOX
  158. bool "Enable Chrome OS EC sandbox driver in TPL"
  159. depends on TPL_CROS_EC && SANDBOX
  160. help
  161. Enable a sandbox emulation of the Chrome OS EC in TPL. This supports
  162. keyboard (use the -l flag to enable the LCD), verified boot context,
  163. EC flash read/write/erase support and a few other things. It is
  164. enough to perform a Chrome OS verified boot on sandbox.
  165. config CROS_EC_SPI
  166. bool "Enable Chrome OS EC SPI driver"
  167. depends on CROS_EC
  168. help
  169. Enable SPI access to the Chrome OS EC. This is used on newer
  170. ARM Chromebooks such as pit, pi and nyan-big. The SPI interface
  171. provides a faster and more robust interface than I2C but the bugs
  172. are less interesting.
  173. config DS4510
  174. bool "Enable support for DS4510 CPU supervisor"
  175. help
  176. Enable support for the Maxim DS4510 CPU supervisor. It has an
  177. integrated 64-byte EEPROM, four programmable non-volatile I/O pins
  178. and a configurable timer for the supervisor function. The device is
  179. connected over I2C.
  180. config FSL_SEC_MON
  181. bool "Enable FSL SEC_MON Driver"
  182. help
  183. Freescale Security Monitor block is responsible for monitoring
  184. system states.
  185. Security Monitor can be transitioned on any security failures,
  186. like software violations or hardware security violations.
  187. config IRQ
  188. bool "Intel Interrupt controller"
  189. depends on X86 || SANDBOX
  190. help
  191. This enables support for Intel interrupt controllers, including ITSS.
  192. Some devices have extra features, such as Apollo Lake. The
  193. device has its own uclass since there are several operations
  194. involved.
  195. config JZ4780_EFUSE
  196. bool "Ingenic JZ4780 eFUSE support"
  197. depends on ARCH_JZ47XX
  198. help
  199. This selects support for the eFUSE on Ingenic JZ4780 SoCs.
  200. config MXC_OCOTP
  201. bool "Enable MXC OCOTP Driver"
  202. depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
  203. default y
  204. help
  205. If you say Y here, you will get support for the One Time
  206. Programmable memory pages that are stored on the some
  207. Freescale i.MX processors.
  208. config NUVOTON_NCT6102D
  209. bool "Enable Nuvoton NCT6102D Super I/O driver"
  210. help
  211. If you say Y here, you will get support for the Nuvoton
  212. NCT6102D Super I/O driver. This can be used to enable or
  213. disable the legacy UART, the watchdog or other devices
  214. in the Nuvoton Super IO chips on X86 platforms.
  215. config P2SB
  216. bool "Intel Primary to Sideband Bridge"
  217. depends on X86 || SANDBOX
  218. help
  219. This enables support for the Intel Primary to Sideband Bridge,
  220. abbreviated to P2SB. The P2SB is used to access various peripherals
  221. such as eSPI, GPIO, through memory-mapped I/O in a large chunk of PCI
  222. space. The space is segmented into different channels and peripherals
  223. are accessed by device-specific means within those channels. Devices
  224. should be added in the device tree as subnodes of the P2SB. A
  225. Peripheral Channel Register? (PCR) API is provided to access those
  226. devices - see pcr_readl(), etc.
  227. config SPL_P2SB
  228. bool "Intel Primary to Sideband Bridge in SPL"
  229. depends on SPL && (X86 || SANDBOX)
  230. help
  231. The Primary to Sideband Bridge is used to access various peripherals
  232. through memory-mapped I/O in a large chunk of PCI space. The space is
  233. segmented into different channels and peripherals are accessed by
  234. device-specific means within those channels. Devices should be added
  235. in the device tree as subnodes of the p2sb.
  236. config TPL_P2SB
  237. bool "Intel Primary to Sideband Bridge in TPL"
  238. depends on TPL && (X86 || SANDBOX)
  239. help
  240. The Primary to Sideband Bridge is used to access various peripherals
  241. through memory-mapped I/O in a large chunk of PCI space. The space is
  242. segmented into different channels and peripherals are accessed by
  243. device-specific means within those channels. Devices should be added
  244. in the device tree as subnodes of the p2sb.
  245. config PWRSEQ
  246. bool "Enable power-sequencing drivers"
  247. depends on DM
  248. help
  249. Power-sequencing drivers provide support for controlling power for
  250. devices. They are typically referenced by a phandle from another
  251. device. When the device is started up, its power sequence can be
  252. initiated.
  253. config SPL_PWRSEQ
  254. bool "Enable power-sequencing drivers for SPL"
  255. depends on PWRSEQ
  256. help
  257. Power-sequencing drivers provide support for controlling power for
  258. devices. They are typically referenced by a phandle from another
  259. device. When the device is started up, its power sequence can be
  260. initiated.
  261. config PCA9551_LED
  262. bool "Enable PCA9551 LED driver"
  263. help
  264. Enable driver for PCA9551 LED controller. This controller
  265. is connected via I2C. So I2C needs to be enabled.
  266. config PCA9551_I2C_ADDR
  267. hex "I2C address of PCA9551 LED controller"
  268. depends on PCA9551_LED
  269. default 0x60
  270. help
  271. The I2C address of the PCA9551 LED controller.
  272. config STM32MP_FUSE
  273. bool "Enable STM32MP fuse wrapper providing the fuse API"
  274. depends on ARCH_STM32MP && MISC
  275. default y if CMD_FUSE
  276. help
  277. If you say Y here, you will get support for the fuse API (OTP)
  278. for STM32MP architecture.
  279. This API is needed for CMD_FUSE.
  280. config STM32_RCC
  281. bool "Enable RCC driver for the STM32 SoC's family"
  282. depends on (ARCH_STM32 || ARCH_STM32MP) && MISC
  283. help
  284. Enable the STM32 RCC driver. The RCC block (Reset and Clock Control
  285. block) is responsible of the management of the clock and reset
  286. generation.
  287. This driver is similar to an MFD driver in the Linux kernel.
  288. config TEGRA_CAR
  289. bool "Enable support for the Tegra CAR driver"
  290. depends on TEGRA_NO_BPMP
  291. help
  292. The Tegra CAR (Clock and Reset Controller) is a HW module that
  293. controls almost all clocks and resets in a Tegra SoC.
  294. config TEGRA186_BPMP
  295. bool "Enable support for the Tegra186 BPMP driver"
  296. depends on TEGRA186
  297. help
  298. The Tegra BPMP (Boot and Power Management Processor) is a separate
  299. auxiliary CPU embedded into Tegra to perform power management work,
  300. and controls related features such as clocks, resets, power domains,
  301. PMIC I2C bus, etc. This driver provides the core low-level
  302. communication path by which feature-specific drivers (such as clock)
  303. can make requests to the BPMP. This driver is similar to an MFD
  304. driver in the Linux kernel.
  305. config TWL4030_LED
  306. bool "Enable TWL4030 LED controller"
  307. help
  308. Enable this to add support for the TWL4030 LED controller.
  309. config WINBOND_W83627
  310. bool "Enable Winbond Super I/O driver"
  311. help
  312. If you say Y here, you will get support for the Winbond
  313. W83627 Super I/O driver. This can be used to enable the
  314. legacy UART or other devices in the Winbond Super IO chips
  315. on X86 platforms.
  316. config QFW
  317. bool
  318. help
  319. Hidden option to enable QEMU fw_cfg interface. This will be selected by
  320. either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE.
  321. config I2C_EEPROM
  322. bool "Enable driver for generic I2C-attached EEPROMs"
  323. depends on MISC
  324. help
  325. Enable a generic driver for EEPROMs attached via I2C.
  326. config SPL_I2C_EEPROM
  327. bool "Enable driver for generic I2C-attached EEPROMs for SPL"
  328. depends on MISC && SPL && SPL_DM
  329. help
  330. This option is an SPL-variant of the I2C_EEPROM option.
  331. See the help of I2C_EEPROM for details.
  332. config ZYNQ_GEM_I2C_MAC_OFFSET
  333. hex "Set the I2C MAC offset"
  334. default 0x0
  335. depends on DM_I2C
  336. help
  337. Set the MAC offset for i2C.
  338. if I2C_EEPROM
  339. config SYS_I2C_EEPROM_ADDR
  340. hex "Chip address of the EEPROM device"
  341. default 0
  342. config SYS_I2C_EEPROM_BUS
  343. int "I2C bus of the EEPROM device."
  344. default 0
  345. config SYS_EEPROM_SIZE
  346. int "Size in bytes of the EEPROM device"
  347. default 256
  348. config SYS_EEPROM_PAGE_WRITE_BITS
  349. int "Number of bits used to address bytes in a single page"
  350. default 0
  351. help
  352. The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS.
  353. A 64 byte page, for example would require six bits.
  354. config SYS_EEPROM_PAGE_WRITE_DELAY_MS
  355. int "Number of milliseconds to delay between page writes"
  356. default 0
  357. config SYS_I2C_EEPROM_ADDR_LEN
  358. int "Length in bytes of the EEPROM memory array address"
  359. default 1
  360. help
  361. Note: This is NOT the chip address length!
  362. config SYS_I2C_EEPROM_ADDR_OVERFLOW
  363. hex "EEPROM Address Overflow"
  364. default 0
  365. help
  366. EEPROM chips that implement "address overflow" are ones
  367. like Catalyst 24WC04/08/16 which has 9/10/11 bits of
  368. address and the extra bits end up in the "chip address" bit
  369. slots. This makes a 24WC08 (1Kbyte) chip look like four 256
  370. byte chips.
  371. endif
  372. config GDSYS_RXAUI_CTRL
  373. bool "Enable gdsys RXAUI control driver"
  374. depends on MISC
  375. help
  376. Support gdsys FPGA's RXAUI control.
  377. config GDSYS_IOEP
  378. bool "Enable gdsys IOEP driver"
  379. depends on MISC
  380. help
  381. Support gdsys FPGA's IO endpoint driver.
  382. config MPC83XX_SERDES
  383. bool "Enable MPC83xx serdes driver"
  384. depends on MISC
  385. help
  386. Support for serdes found on MPC83xx SoCs.
  387. config FS_LOADER
  388. bool "Enable loader driver for file system"
  389. help
  390. This is file system generic loader which can be used to load
  391. the file image from the storage into target such as memory.
  392. The consumer driver would then use this loader to program whatever,
  393. ie. the FPGA device.
  394. config GDSYS_SOC
  395. bool "Enable gdsys SOC driver"
  396. depends on MISC
  397. help
  398. Support for gdsys IHS SOC, a simple bus associated with each gdsys
  399. IHS (Integrated Hardware Systems) FPGA, which holds all devices whose
  400. register maps are contained within the FPGA's register map.
  401. config IHS_FPGA
  402. bool "Enable IHS FPGA driver"
  403. depends on MISC
  404. help
  405. Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on
  406. gdsys devices, which supply the majority of the functionality offered
  407. by the devices. This driver supports both CON and CPU variants of the
  408. devices, depending on the device tree entry.
  409. config ESM_K3
  410. bool "Enable K3 ESM driver"
  411. depends on ARCH_K3
  412. help
  413. Support ESM (Error Signaling Module) on TI K3 SoCs.
  414. config MICROCHIP_FLEXCOM
  415. bool "Enable Microchip Flexcom driver"
  416. depends on MISC
  417. help
  418. The Atmel Flexcom is just a wrapper which embeds a SPI controller,
  419. an I2C controller and an USART.
  420. Only one function can be used at a time and is chosen at boot time
  421. according to the device tree.
  422. config K3_AVS0
  423. depends on ARCH_K3 && SPL_DM_REGULATOR
  424. bool "AVS class 0 support for K3 devices"
  425. help
  426. K3 devices have the optimized voltage values for the main voltage
  427. domains stored in efuse within the VTM IP. This driver reads the
  428. optimized voltage from the efuse, so that it can be programmed
  429. to the PMIC on board.
  430. config ESM_PMIC
  431. bool "Enable PMIC ESM driver"
  432. depends on DM_PMIC
  433. help
  434. Support ESM (Error Signal Monitor) on PMIC devices. ESM is used
  435. typically to reboot the board in error condition.
  436. endmenu