rk_i2c.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2015 Google, Inc
  4. *
  5. * (C) Copyright 2008-2014 Rockchip Electronics
  6. * Peter, Software Engineering, <superpeter.cai@gmail.com>.
  7. */
  8. #include <common.h>
  9. #include <clk.h>
  10. #include <dm.h>
  11. #include <errno.h>
  12. #include <i2c.h>
  13. #include <log.h>
  14. #include <asm/io.h>
  15. #include <asm/arch-rockchip/clock.h>
  16. #include <asm/arch-rockchip/i2c.h>
  17. #include <asm/arch-rockchip/periph.h>
  18. #include <dm/pinctrl.h>
  19. #include <linux/delay.h>
  20. #include <linux/sizes.h>
  21. /* i2c timerout */
  22. #define I2C_TIMEOUT_MS 100
  23. #define I2C_RETRY_COUNT 3
  24. /* rk i2c fifo max transfer bytes */
  25. #define RK_I2C_FIFO_SIZE 32
  26. struct rk_i2c {
  27. struct clk clk;
  28. struct i2c_regs *regs;
  29. unsigned int speed;
  30. };
  31. enum {
  32. RK_I2C_LEGACY,
  33. RK_I2C_NEW,
  34. };
  35. /**
  36. * @controller_type: i2c controller type
  37. */
  38. struct rk_i2c_soc_data {
  39. int controller_type;
  40. };
  41. static inline void rk_i2c_get_div(int div, int *divh, int *divl)
  42. {
  43. *divl = div / 2;
  44. if (div % 2 == 0)
  45. *divh = div / 2;
  46. else
  47. *divh = DIV_ROUND_UP(div, 2);
  48. }
  49. /*
  50. * SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1)
  51. * SCL = PCLK / SCLK Divisor
  52. * i2c_rate = PCLK
  53. */
  54. static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate)
  55. {
  56. uint32_t i2c_rate;
  57. int div, divl, divh;
  58. /* First get i2c rate from pclk */
  59. i2c_rate = clk_get_rate(&i2c->clk);
  60. div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
  61. divh = 0;
  62. divl = 0;
  63. if (div >= 0)
  64. rk_i2c_get_div(div, &divh, &divl);
  65. writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv);
  66. debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate,
  67. scl_rate);
  68. debug("set i2c clk div = %d, divh = %d, divl = %d\n", div, divh, divl);
  69. debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv));
  70. }
  71. static void rk_i2c_show_regs(struct i2c_regs *regs)
  72. {
  73. #ifdef DEBUG
  74. uint i;
  75. debug("i2c_con: 0x%08x\n", readl(&regs->con));
  76. debug("i2c_clkdiv: 0x%08x\n", readl(&regs->clkdiv));
  77. debug("i2c_mrxaddr: 0x%08x\n", readl(&regs->mrxaddr));
  78. debug("i2c_mrxraddR: 0x%08x\n", readl(&regs->mrxraddr));
  79. debug("i2c_mtxcnt: 0x%08x\n", readl(&regs->mtxcnt));
  80. debug("i2c_mrxcnt: 0x%08x\n", readl(&regs->mrxcnt));
  81. debug("i2c_ien: 0x%08x\n", readl(&regs->ien));
  82. debug("i2c_ipd: 0x%08x\n", readl(&regs->ipd));
  83. debug("i2c_fcnt: 0x%08x\n", readl(&regs->fcnt));
  84. for (i = 0; i < 8; i++)
  85. debug("i2c_txdata%d: 0x%08x\n", i, readl(&regs->txdata[i]));
  86. for (i = 0; i < 8; i++)
  87. debug("i2c_rxdata%d: 0x%08x\n", i, readl(&regs->rxdata[i]));
  88. #endif
  89. }
  90. static int rk_i2c_send_start_bit(struct rk_i2c *i2c)
  91. {
  92. struct i2c_regs *regs = i2c->regs;
  93. ulong start;
  94. debug("I2c Send Start bit.\n");
  95. writel(I2C_IPD_ALL_CLEAN, &regs->ipd);
  96. writel(I2C_CON_EN | I2C_CON_START, &regs->con);
  97. writel(I2C_STARTIEN, &regs->ien);
  98. start = get_timer(0);
  99. while (1) {
  100. if (readl(&regs->ipd) & I2C_STARTIPD) {
  101. writel(I2C_STARTIPD, &regs->ipd);
  102. break;
  103. }
  104. if (get_timer(start) > I2C_TIMEOUT_MS) {
  105. debug("I2C Send Start Bit Timeout\n");
  106. rk_i2c_show_regs(regs);
  107. return -ETIMEDOUT;
  108. }
  109. udelay(1);
  110. }
  111. return 0;
  112. }
  113. static int rk_i2c_send_stop_bit(struct rk_i2c *i2c)
  114. {
  115. struct i2c_regs *regs = i2c->regs;
  116. ulong start;
  117. debug("I2c Send Stop bit.\n");
  118. writel(I2C_IPD_ALL_CLEAN, &regs->ipd);
  119. writel(I2C_CON_EN | I2C_CON_STOP, &regs->con);
  120. writel(I2C_CON_STOP, &regs->ien);
  121. start = get_timer(0);
  122. while (1) {
  123. if (readl(&regs->ipd) & I2C_STOPIPD) {
  124. writel(I2C_STOPIPD, &regs->ipd);
  125. break;
  126. }
  127. if (get_timer(start) > I2C_TIMEOUT_MS) {
  128. debug("I2C Send Start Bit Timeout\n");
  129. rk_i2c_show_regs(regs);
  130. return -ETIMEDOUT;
  131. }
  132. udelay(1);
  133. }
  134. return 0;
  135. }
  136. static inline void rk_i2c_disable(struct rk_i2c *i2c)
  137. {
  138. writel(0, &i2c->regs->con);
  139. }
  140. static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
  141. uchar *buf, uint b_len)
  142. {
  143. struct i2c_regs *regs = i2c->regs;
  144. uchar *pbuf = buf;
  145. uint bytes_remain_len = b_len;
  146. uint bytes_xferred = 0;
  147. uint words_xferred = 0;
  148. ulong start;
  149. uint con = 0;
  150. uint rxdata;
  151. uint i, j;
  152. int err;
  153. bool snd_chunk = false;
  154. debug("rk_i2c_read: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
  155. chip, reg, r_len, b_len);
  156. err = rk_i2c_send_start_bit(i2c);
  157. if (err)
  158. return err;
  159. writel(I2C_MRXADDR_SET(1, chip << 1 | 1), &regs->mrxaddr);
  160. if (r_len == 0) {
  161. writel(0, &regs->mrxraddr);
  162. } else if (r_len < 4) {
  163. writel(I2C_MRXRADDR_SET(r_len, reg), &regs->mrxraddr);
  164. } else {
  165. debug("I2C Read: addr len %d not supported\n", r_len);
  166. return -EIO;
  167. }
  168. while (bytes_remain_len) {
  169. if (bytes_remain_len > RK_I2C_FIFO_SIZE) {
  170. con = I2C_CON_EN;
  171. bytes_xferred = 32;
  172. } else {
  173. /*
  174. * The hw can read up to 32 bytes at a time. If we need
  175. * more than one chunk, send an ACK after the last byte.
  176. */
  177. con = I2C_CON_EN | I2C_CON_LASTACK;
  178. bytes_xferred = bytes_remain_len;
  179. }
  180. words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
  181. /*
  182. * make sure we are in plain RX mode if we read a second chunk
  183. */
  184. if (snd_chunk)
  185. con |= I2C_CON_MOD(I2C_MODE_RX);
  186. else
  187. con |= I2C_CON_MOD(I2C_MODE_TRX);
  188. writel(con, &regs->con);
  189. writel(bytes_xferred, &regs->mrxcnt);
  190. writel(I2C_MBRFIEN | I2C_NAKRCVIEN, &regs->ien);
  191. start = get_timer(0);
  192. while (1) {
  193. if (readl(&regs->ipd) & I2C_NAKRCVIPD) {
  194. writel(I2C_NAKRCVIPD, &regs->ipd);
  195. err = -EREMOTEIO;
  196. }
  197. if (readl(&regs->ipd) & I2C_MBRFIPD) {
  198. writel(I2C_MBRFIPD, &regs->ipd);
  199. break;
  200. }
  201. if (get_timer(start) > I2C_TIMEOUT_MS) {
  202. debug("I2C Read Data Timeout\n");
  203. err = -ETIMEDOUT;
  204. rk_i2c_show_regs(regs);
  205. goto i2c_exit;
  206. }
  207. udelay(1);
  208. }
  209. for (i = 0; i < words_xferred; i++) {
  210. rxdata = readl(&regs->rxdata[i]);
  211. debug("I2c Read RXDATA[%d] = 0x%x\n", i, rxdata);
  212. for (j = 0; j < 4; j++) {
  213. if ((i * 4 + j) == bytes_xferred)
  214. break;
  215. *pbuf++ = (rxdata >> (j * 8)) & 0xff;
  216. }
  217. }
  218. bytes_remain_len -= bytes_xferred;
  219. snd_chunk = true;
  220. debug("I2C Read bytes_remain_len %d\n", bytes_remain_len);
  221. }
  222. i2c_exit:
  223. rk_i2c_disable(i2c);
  224. return err;
  225. }
  226. static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
  227. uchar *buf, uint b_len)
  228. {
  229. struct i2c_regs *regs = i2c->regs;
  230. int err;
  231. uchar *pbuf = buf;
  232. uint bytes_remain_len = b_len + r_len + 1;
  233. uint bytes_xferred = 0;
  234. uint words_xferred = 0;
  235. ulong start;
  236. uint txdata;
  237. uint i, j;
  238. debug("rk_i2c_write: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
  239. chip, reg, r_len, b_len);
  240. err = rk_i2c_send_start_bit(i2c);
  241. if (err)
  242. return err;
  243. while (bytes_remain_len) {
  244. if (bytes_remain_len > RK_I2C_FIFO_SIZE)
  245. bytes_xferred = RK_I2C_FIFO_SIZE;
  246. else
  247. bytes_xferred = bytes_remain_len;
  248. words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
  249. for (i = 0; i < words_xferred; i++) {
  250. txdata = 0;
  251. for (j = 0; j < 4; j++) {
  252. if ((i * 4 + j) == bytes_xferred)
  253. break;
  254. if (i == 0 && j == 0 && pbuf == buf) {
  255. txdata |= (chip << 1);
  256. } else if (i == 0 && j <= r_len && pbuf == buf) {
  257. txdata |= (reg &
  258. (0xff << ((j - 1) * 8))) << 8;
  259. } else {
  260. txdata |= (*pbuf++)<<(j * 8);
  261. }
  262. }
  263. writel(txdata, &regs->txdata[i]);
  264. debug("I2c Write TXDATA[%d] = 0x%08x\n", i, txdata);
  265. }
  266. writel(I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TX), &regs->con);
  267. writel(bytes_xferred, &regs->mtxcnt);
  268. writel(I2C_MBTFIEN | I2C_NAKRCVIEN, &regs->ien);
  269. start = get_timer(0);
  270. while (1) {
  271. if (readl(&regs->ipd) & I2C_NAKRCVIPD) {
  272. writel(I2C_NAKRCVIPD, &regs->ipd);
  273. err = -EREMOTEIO;
  274. }
  275. if (readl(&regs->ipd) & I2C_MBTFIPD) {
  276. writel(I2C_MBTFIPD, &regs->ipd);
  277. break;
  278. }
  279. if (get_timer(start) > I2C_TIMEOUT_MS) {
  280. debug("I2C Write Data Timeout\n");
  281. err = -ETIMEDOUT;
  282. rk_i2c_show_regs(regs);
  283. goto i2c_exit;
  284. }
  285. udelay(1);
  286. }
  287. bytes_remain_len -= bytes_xferred;
  288. debug("I2C Write bytes_remain_len %d\n", bytes_remain_len);
  289. }
  290. i2c_exit:
  291. rk_i2c_disable(i2c);
  292. return err;
  293. }
  294. static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
  295. int nmsgs)
  296. {
  297. struct rk_i2c *i2c = dev_get_priv(bus);
  298. int ret;
  299. debug("i2c_xfer: %d messages\n", nmsgs);
  300. for (; nmsgs > 0; nmsgs--, msg++) {
  301. debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
  302. if (msg->flags & I2C_M_RD) {
  303. ret = rk_i2c_read(i2c, msg->addr, 0, 0, msg->buf,
  304. msg->len);
  305. } else {
  306. ret = rk_i2c_write(i2c, msg->addr, 0, 0, msg->buf,
  307. msg->len);
  308. }
  309. if (ret) {
  310. debug("i2c_write: error sending\n");
  311. return -EREMOTEIO;
  312. }
  313. }
  314. rk_i2c_send_stop_bit(i2c);
  315. rk_i2c_disable(i2c);
  316. return 0;
  317. }
  318. int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
  319. {
  320. struct rk_i2c *i2c = dev_get_priv(bus);
  321. rk_i2c_set_clk(i2c, speed);
  322. return 0;
  323. }
  324. static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
  325. {
  326. struct rk_i2c *priv = dev_get_priv(bus);
  327. int ret;
  328. ret = clk_get_by_index(bus, 0, &priv->clk);
  329. if (ret < 0) {
  330. debug("%s: Could not get clock for %s: %d\n", __func__,
  331. bus->name, ret);
  332. return ret;
  333. }
  334. return 0;
  335. }
  336. static int rockchip_i2c_probe(struct udevice *bus)
  337. {
  338. struct rk_i2c *priv = dev_get_priv(bus);
  339. struct rk_i2c_soc_data *soc_data;
  340. struct udevice *pinctrl;
  341. int bus_nr;
  342. int ret;
  343. priv->regs = dev_read_addr_ptr(bus);
  344. soc_data = (struct rk_i2c_soc_data*)dev_get_driver_data(bus);
  345. if (soc_data->controller_type == RK_I2C_LEGACY) {
  346. ret = dev_read_alias_seq(bus, &bus_nr);
  347. if (ret < 0) {
  348. debug("%s: Could not get alias for %s: %d\n",
  349. __func__, bus->name, ret);
  350. return ret;
  351. }
  352. ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl);
  353. if (ret) {
  354. debug("%s: Cannot find pinctrl device\n", __func__);
  355. return ret;
  356. }
  357. /* pinctrl will switch I2C to new type */
  358. ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_I2C0 + bus_nr);
  359. if (ret) {
  360. debug("%s: Failed to switch I2C to new type %s: %d\n",
  361. __func__, bus->name, ret);
  362. return ret;
  363. }
  364. }
  365. return 0;
  366. }
  367. static const struct dm_i2c_ops rockchip_i2c_ops = {
  368. .xfer = rockchip_i2c_xfer,
  369. .set_bus_speed = rockchip_i2c_set_bus_speed,
  370. };
  371. static const struct rk_i2c_soc_data rk3066_soc_data = {
  372. .controller_type = RK_I2C_LEGACY,
  373. };
  374. static const struct rk_i2c_soc_data rk3188_soc_data = {
  375. .controller_type = RK_I2C_LEGACY,
  376. };
  377. static const struct rk_i2c_soc_data rk3228_soc_data = {
  378. .controller_type = RK_I2C_NEW,
  379. };
  380. static const struct rk_i2c_soc_data rk3288_soc_data = {
  381. .controller_type = RK_I2C_NEW,
  382. };
  383. static const struct rk_i2c_soc_data rk3328_soc_data = {
  384. .controller_type = RK_I2C_NEW,
  385. };
  386. static const struct rk_i2c_soc_data rk3399_soc_data = {
  387. .controller_type = RK_I2C_NEW,
  388. };
  389. static const struct udevice_id rockchip_i2c_ids[] = {
  390. {
  391. .compatible = "rockchip,rk3066-i2c",
  392. .data = (ulong)&rk3066_soc_data,
  393. },
  394. {
  395. .compatible = "rockchip,rk3188-i2c",
  396. .data = (ulong)&rk3188_soc_data,
  397. },
  398. {
  399. .compatible = "rockchip,rk3228-i2c",
  400. .data = (ulong)&rk3228_soc_data,
  401. },
  402. {
  403. .compatible = "rockchip,rk3288-i2c",
  404. .data = (ulong)&rk3288_soc_data,
  405. },
  406. {
  407. .compatible = "rockchip,rk3328-i2c",
  408. .data = (ulong)&rk3328_soc_data,
  409. },
  410. {
  411. .compatible = "rockchip,rk3399-i2c",
  412. .data = (ulong)&rk3399_soc_data,
  413. },
  414. { }
  415. };
  416. U_BOOT_DRIVER(rockchip_rk3066_i2c) = {
  417. .name = "rockchip_rk3066_i2c",
  418. .id = UCLASS_I2C,
  419. .of_match = rockchip_i2c_ids,
  420. .ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata,
  421. .probe = rockchip_i2c_probe,
  422. .priv_auto_alloc_size = sizeof(struct rk_i2c),
  423. .ops = &rockchip_i2c_ops,
  424. };
  425. U_BOOT_DRIVER_ALIAS(rockchip_rk3066_i2c, rockchip_rk3288_i2c)