at91_i2c.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Atmel I2C driver.
  4. *
  5. * (C) Copyright 2016 Songjun Wu <songjun.wu@atmel.com>
  6. */
  7. #include <malloc.h>
  8. #include <asm/io.h>
  9. #include <common.h>
  10. #include <clk.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <fdtdec.h>
  14. #include <i2c.h>
  15. #include <linux/bitops.h>
  16. #include <mach/clk.h>
  17. #include "at91_i2c.h"
  18. DECLARE_GLOBAL_DATA_PTR;
  19. #define I2C_TIMEOUT_MS 100
  20. static int at91_wait_for_xfer(struct at91_i2c_bus *bus, u32 status)
  21. {
  22. struct at91_i2c_regs *reg = bus->regs;
  23. ulong start_time = get_timer(0);
  24. u32 sr;
  25. bus->status = 0;
  26. do {
  27. sr = readl(&reg->sr);
  28. bus->status |= sr;
  29. if (sr & TWI_SR_NACK)
  30. return -EREMOTEIO;
  31. else if (sr & status)
  32. return 0;
  33. } while (get_timer(start_time) < I2C_TIMEOUT_MS);
  34. return -ETIMEDOUT;
  35. }
  36. static int at91_i2c_xfer_msg(struct at91_i2c_bus *bus, struct i2c_msg *msg)
  37. {
  38. struct at91_i2c_regs *reg = bus->regs;
  39. bool is_read = msg->flags & I2C_M_RD;
  40. u32 i;
  41. int ret = 0;
  42. readl(&reg->sr);
  43. if (is_read) {
  44. writel(TWI_CR_START, &reg->cr);
  45. for (i = 0; !ret && i < (msg->len - 1); i++) {
  46. ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY);
  47. msg->buf[i] = readl(&reg->rhr);
  48. }
  49. if (ret)
  50. goto error;
  51. writel(TWI_CR_STOP, &reg->cr);
  52. ret = at91_wait_for_xfer(bus, TWI_SR_RXRDY);
  53. if (ret)
  54. goto error;
  55. msg->buf[i] = readl(&reg->rhr);
  56. } else {
  57. writel(msg->buf[0], &reg->thr);
  58. ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY);
  59. for (i = 1; !ret && (i < msg->len); i++) {
  60. writel(msg->buf[i], &reg->thr);
  61. ret = at91_wait_for_xfer(bus, TWI_SR_TXRDY);
  62. }
  63. if (ret)
  64. goto error;
  65. writel(TWI_CR_STOP, &reg->cr);
  66. }
  67. if (!ret)
  68. ret = at91_wait_for_xfer(bus, TWI_SR_TXCOMP);
  69. if (ret)
  70. goto error;
  71. if (bus->status & (TWI_SR_OVRE | TWI_SR_UNRE | TWI_SR_LOCK)) {
  72. ret = -EIO;
  73. goto error;
  74. }
  75. return 0;
  76. error:
  77. if (bus->status & TWI_SR_LOCK)
  78. writel(TWI_CR_LOCKCLR, &reg->cr);
  79. return ret;
  80. }
  81. static int at91_i2c_xfer(struct udevice *dev, struct i2c_msg *msg, int nmsgs)
  82. {
  83. struct at91_i2c_bus *bus = dev_get_priv(dev);
  84. struct at91_i2c_regs *reg = bus->regs;
  85. struct i2c_msg *m_start = msg;
  86. bool is_read;
  87. u32 int_addr_flag = 0;
  88. int ret = 0;
  89. if (nmsgs == 2) {
  90. int internal_address = 0;
  91. int i;
  92. /* 1st msg is put into the internal address, start with 2nd */
  93. m_start = &msg[1];
  94. /* the max length of internal address is 3 bytes */
  95. if (msg->len > 3)
  96. return -EFAULT;
  97. for (i = 0; i < msg->len; ++i) {
  98. const unsigned addr = msg->buf[msg->len - 1 - i];
  99. internal_address |= addr << (8 * i);
  100. int_addr_flag += TWI_MMR_IADRSZ_1;
  101. }
  102. writel(internal_address, &reg->iadr);
  103. }
  104. is_read = m_start->flags & I2C_M_RD;
  105. writel((m_start->addr << 16) | int_addr_flag |
  106. (is_read ? TWI_MMR_MREAD : 0), &reg->mmr);
  107. ret = at91_i2c_xfer_msg(bus, m_start);
  108. return ret;
  109. }
  110. /*
  111. * Calculate symmetric clock as stated in datasheet:
  112. * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
  113. */
  114. static void at91_calc_i2c_clock(struct udevice *dev, int i2c_clk)
  115. {
  116. struct at91_i2c_bus *bus = dev_get_priv(dev);
  117. const struct at91_i2c_pdata *pdata = bus->pdata;
  118. int offset = pdata->clk_offset;
  119. int max_ckdiv = pdata->clk_max_div;
  120. int ckdiv, cdiv, div;
  121. unsigned long src_rate;
  122. src_rate = bus->bus_clk_rate;
  123. div = max(0, (int)DIV_ROUND_UP(src_rate, 2 * i2c_clk) - offset);
  124. ckdiv = fls(div >> 8);
  125. cdiv = div >> ckdiv;
  126. if (ckdiv > max_ckdiv) {
  127. ckdiv = max_ckdiv;
  128. cdiv = 255;
  129. }
  130. bus->speed = DIV_ROUND_UP(src_rate,
  131. (cdiv * (1 << ckdiv) + offset) * 2);
  132. bus->cwgr_val = (ckdiv << 16) | (cdiv << 8) | cdiv;
  133. }
  134. static int at91_i2c_enable_clk(struct udevice *dev)
  135. {
  136. struct at91_i2c_bus *bus = dev_get_priv(dev);
  137. struct clk clk;
  138. ulong clk_rate;
  139. int ret;
  140. ret = clk_get_by_index(dev, 0, &clk);
  141. if (ret)
  142. return -EINVAL;
  143. ret = clk_enable(&clk);
  144. if (ret)
  145. return ret;
  146. clk_rate = clk_get_rate(&clk);
  147. if (!clk_rate)
  148. return -EINVAL;
  149. bus->bus_clk_rate = clk_rate;
  150. clk_free(&clk);
  151. return 0;
  152. }
  153. static int at91_i2c_set_bus_speed(struct udevice *dev, unsigned int speed)
  154. {
  155. struct at91_i2c_bus *bus = dev_get_priv(dev);
  156. at91_calc_i2c_clock(dev, speed);
  157. writel(bus->cwgr_val, &bus->regs->cwgr);
  158. return 0;
  159. }
  160. int at91_i2c_get_bus_speed(struct udevice *dev)
  161. {
  162. struct at91_i2c_bus *bus = dev_get_priv(dev);
  163. return bus->speed;
  164. }
  165. static int at91_i2c_ofdata_to_platdata(struct udevice *dev)
  166. {
  167. const void *blob = gd->fdt_blob;
  168. struct at91_i2c_bus *bus = dev_get_priv(dev);
  169. int node = dev_of_offset(dev);
  170. bus->regs = dev_read_addr_ptr(dev);
  171. bus->pdata = (struct at91_i2c_pdata *)dev_get_driver_data(dev);
  172. bus->clock_frequency = fdtdec_get_int(blob, node,
  173. "clock-frequency", 100000);
  174. return 0;
  175. }
  176. static const struct dm_i2c_ops at91_i2c_ops = {
  177. .xfer = at91_i2c_xfer,
  178. .set_bus_speed = at91_i2c_set_bus_speed,
  179. .get_bus_speed = at91_i2c_get_bus_speed,
  180. };
  181. static int at91_i2c_probe(struct udevice *dev)
  182. {
  183. struct at91_i2c_bus *bus = dev_get_priv(dev);
  184. struct at91_i2c_regs *reg = bus->regs;
  185. int ret;
  186. ret = at91_i2c_enable_clk(dev);
  187. if (ret)
  188. return ret;
  189. writel(TWI_CR_SWRST, &reg->cr);
  190. at91_calc_i2c_clock(dev, bus->clock_frequency);
  191. writel(bus->cwgr_val, &reg->cwgr);
  192. writel(TWI_CR_MSEN, &reg->cr);
  193. writel(TWI_CR_SVDIS, &reg->cr);
  194. return 0;
  195. }
  196. static const struct at91_i2c_pdata at91rm9200_config = {
  197. .clk_max_div = 5,
  198. .clk_offset = 3,
  199. };
  200. static const struct at91_i2c_pdata at91sam9261_config = {
  201. .clk_max_div = 5,
  202. .clk_offset = 4,
  203. };
  204. static const struct at91_i2c_pdata at91sam9260_config = {
  205. .clk_max_div = 7,
  206. .clk_offset = 4,
  207. };
  208. static const struct at91_i2c_pdata at91sam9g20_config = {
  209. .clk_max_div = 7,
  210. .clk_offset = 4,
  211. };
  212. static const struct at91_i2c_pdata at91sam9g10_config = {
  213. .clk_max_div = 7,
  214. .clk_offset = 4,
  215. };
  216. static const struct at91_i2c_pdata at91sam9x5_config = {
  217. .clk_max_div = 7,
  218. .clk_offset = 4,
  219. };
  220. static const struct at91_i2c_pdata sama5d4_config = {
  221. .clk_max_div = 7,
  222. .clk_offset = 4,
  223. };
  224. static const struct at91_i2c_pdata sama5d2_config = {
  225. .clk_max_div = 7,
  226. .clk_offset = 3,
  227. };
  228. static const struct udevice_id at91_i2c_ids[] = {
  229. { .compatible = "atmel,at91rm9200-i2c", .data = (long)&at91rm9200_config },
  230. { .compatible = "atmel,at91sam9260-i2c", .data = (long)&at91sam9260_config },
  231. { .compatible = "atmel,at91sam9261-i2c", .data = (long)&at91sam9261_config },
  232. { .compatible = "atmel,at91sam9g20-i2c", .data = (long)&at91sam9g20_config },
  233. { .compatible = "atmel,at91sam9g10-i2c", .data = (long)&at91sam9g10_config },
  234. { .compatible = "atmel,at91sam9x5-i2c", .data = (long)&at91sam9x5_config },
  235. { .compatible = "atmel,sama5d4-i2c", .data = (long)&sama5d4_config },
  236. { .compatible = "atmel,sama5d2-i2c", .data = (long)&sama5d2_config },
  237. { }
  238. };
  239. U_BOOT_DRIVER(i2c_at91) = {
  240. .name = "i2c_at91",
  241. .id = UCLASS_I2C,
  242. .of_match = at91_i2c_ids,
  243. .probe = at91_i2c_probe,
  244. .ofdata_to_platdata = at91_i2c_ofdata_to_platdata,
  245. .per_child_auto_alloc_size = sizeof(struct dm_i2c_chip),
  246. .priv_auto_alloc_size = sizeof(struct at91_i2c_bus),
  247. .ops = &at91_i2c_ops,
  248. };