zynq_gpio.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Xilinx Zynq GPIO device driver
  4. *
  5. * Copyright (C) 2015 DAVE Embedded Systems <devel@dave.eu>
  6. *
  7. * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
  8. * Copyright (C) 2009 - 2014 Xilinx, Inc.
  9. */
  10. #include <common.h>
  11. #include <asm/gpio.h>
  12. #include <asm/io.h>
  13. #include <linux/bitops.h>
  14. #include <linux/errno.h>
  15. #include <dm.h>
  16. #include <fdtdec.h>
  17. /* Maximum banks */
  18. #define ZYNQ_GPIO_MAX_BANK 4
  19. #define ZYNQ_GPIO_BANK0_NGPIO 32
  20. #define ZYNQ_GPIO_BANK1_NGPIO 22
  21. #define ZYNQ_GPIO_BANK2_NGPIO 32
  22. #define ZYNQ_GPIO_BANK3_NGPIO 32
  23. #define ZYNQ_GPIO_NR_GPIOS (ZYNQ_GPIO_BANK0_NGPIO + \
  24. ZYNQ_GPIO_BANK1_NGPIO + \
  25. ZYNQ_GPIO_BANK2_NGPIO + \
  26. ZYNQ_GPIO_BANK3_NGPIO)
  27. #define ZYNQMP_GPIO_MAX_BANK 6
  28. #define ZYNQMP_GPIO_BANK0_NGPIO 26
  29. #define ZYNQMP_GPIO_BANK1_NGPIO 26
  30. #define ZYNQMP_GPIO_BANK2_NGPIO 26
  31. #define ZYNQMP_GPIO_BANK3_NGPIO 32
  32. #define ZYNQMP_GPIO_BANK4_NGPIO 32
  33. #define ZYNQMP_GPIO_BANK5_NGPIO 32
  34. #define ZYNQMP_GPIO_NR_GPIOS 174
  35. #define ZYNQ_GPIO_BANK0_PIN_MIN(str) 0
  36. #define ZYNQ_GPIO_BANK0_PIN_MAX(str) (ZYNQ_GPIO_BANK0_PIN_MIN(str) + \
  37. ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
  38. #define ZYNQ_GPIO_BANK1_PIN_MIN(str) (ZYNQ_GPIO_BANK0_PIN_MAX(str) + 1)
  39. #define ZYNQ_GPIO_BANK1_PIN_MAX(str) (ZYNQ_GPIO_BANK1_PIN_MIN(str) + \
  40. ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
  41. #define ZYNQ_GPIO_BANK2_PIN_MIN(str) (ZYNQ_GPIO_BANK1_PIN_MAX(str) + 1)
  42. #define ZYNQ_GPIO_BANK2_PIN_MAX(str) (ZYNQ_GPIO_BANK2_PIN_MIN(str) + \
  43. ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
  44. #define ZYNQ_GPIO_BANK3_PIN_MIN(str) (ZYNQ_GPIO_BANK2_PIN_MAX(str) + 1)
  45. #define ZYNQ_GPIO_BANK3_PIN_MAX(str) (ZYNQ_GPIO_BANK3_PIN_MIN(str) + \
  46. ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
  47. #define ZYNQ_GPIO_BANK4_PIN_MIN(str) (ZYNQ_GPIO_BANK3_PIN_MAX(str) + 1)
  48. #define ZYNQ_GPIO_BANK4_PIN_MAX(str) (ZYNQ_GPIO_BANK4_PIN_MIN(str) + \
  49. ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
  50. #define ZYNQ_GPIO_BANK5_PIN_MIN(str) (ZYNQ_GPIO_BANK4_PIN_MAX(str) + 1)
  51. #define ZYNQ_GPIO_BANK5_PIN_MAX(str) (ZYNQ_GPIO_BANK5_PIN_MIN(str) + \
  52. ZYNQ##str##_GPIO_BANK5_NGPIO - 1)
  53. /* Register offsets for the GPIO device */
  54. /* LSW Mask & Data -WO */
  55. #define ZYNQ_GPIO_DATA_LSW_OFFSET(BANK) (0x000 + (8 * BANK))
  56. /* MSW Mask & Data -WO */
  57. #define ZYNQ_GPIO_DATA_MSW_OFFSET(BANK) (0x004 + (8 * BANK))
  58. /* Data Register-RW */
  59. #define ZYNQ_GPIO_DATA_RO_OFFSET(BANK) (0x060 + (4 * BANK))
  60. /* Direction mode reg-RW */
  61. #define ZYNQ_GPIO_DIRM_OFFSET(BANK) (0x204 + (0x40 * BANK))
  62. /* Output enable reg-RW */
  63. #define ZYNQ_GPIO_OUTEN_OFFSET(BANK) (0x208 + (0x40 * BANK))
  64. /* Interrupt mask reg-RO */
  65. #define ZYNQ_GPIO_INTMASK_OFFSET(BANK) (0x20C + (0x40 * BANK))
  66. /* Interrupt enable reg-WO */
  67. #define ZYNQ_GPIO_INTEN_OFFSET(BANK) (0x210 + (0x40 * BANK))
  68. /* Interrupt disable reg-WO */
  69. #define ZYNQ_GPIO_INTDIS_OFFSET(BANK) (0x214 + (0x40 * BANK))
  70. /* Interrupt status reg-RO */
  71. #define ZYNQ_GPIO_INTSTS_OFFSET(BANK) (0x218 + (0x40 * BANK))
  72. /* Interrupt type reg-RW */
  73. #define ZYNQ_GPIO_INTTYPE_OFFSET(BANK) (0x21C + (0x40 * BANK))
  74. /* Interrupt polarity reg-RW */
  75. #define ZYNQ_GPIO_INTPOL_OFFSET(BANK) (0x220 + (0x40 * BANK))
  76. /* Interrupt on any, reg-RW */
  77. #define ZYNQ_GPIO_INTANY_OFFSET(BANK) (0x224 + (0x40 * BANK))
  78. /* Disable all interrupts mask */
  79. #define ZYNQ_GPIO_IXR_DISABLE_ALL 0xFFFFFFFF
  80. /* Mid pin number of a bank */
  81. #define ZYNQ_GPIO_MID_PIN_NUM 16
  82. /* GPIO upper 16 bit mask */
  83. #define ZYNQ_GPIO_UPPER_MASK 0xFFFF0000
  84. #define PMC_GPIO_NR_GPIOS 116
  85. #define PMC_GPIO_MAX_BANK 5
  86. struct zynq_gpio_platdata {
  87. phys_addr_t base;
  88. const struct zynq_platform_data *p_data;
  89. };
  90. /**
  91. * struct zynq_platform_data - zynq gpio platform data structure
  92. * @label: string to store in gpio->label
  93. * @ngpio: max number of gpio pins
  94. * @max_bank: maximum number of gpio banks
  95. * @bank_min: this array represents bank's min pin
  96. * @bank_max: this array represents bank's max pin
  97. */
  98. struct zynq_platform_data {
  99. const char *label;
  100. u16 ngpio;
  101. u32 max_bank;
  102. u32 bank_min[ZYNQMP_GPIO_MAX_BANK];
  103. u32 bank_max[ZYNQMP_GPIO_MAX_BANK];
  104. };
  105. #define VERSAL_GPIO_NR_GPIOS 58
  106. #define VERSAL_GPIO_MAX_BANK 4
  107. static const struct zynq_platform_data versal_gpio_def = {
  108. .label = "versal_gpio",
  109. .ngpio = VERSAL_GPIO_NR_GPIOS,
  110. .max_bank = VERSAL_GPIO_MAX_BANK,
  111. .bank_min[0] = 0,
  112. .bank_max[0] = 25,
  113. .bank_min[3] = 26,
  114. .bank_max[3] = 57,
  115. };
  116. static const struct zynq_platform_data pmc_gpio_def = {
  117. .label = "pmc_gpio",
  118. .ngpio = PMC_GPIO_NR_GPIOS,
  119. .max_bank = PMC_GPIO_MAX_BANK,
  120. .bank_min[0] = 0,
  121. .bank_max[0] = 25,
  122. .bank_min[1] = 26,
  123. .bank_max[1] = 51,
  124. .bank_min[3] = 52,
  125. .bank_max[3] = 83,
  126. .bank_min[4] = 84,
  127. .bank_max[4] = 115,
  128. };
  129. static const struct zynq_platform_data zynqmp_gpio_def = {
  130. .label = "zynqmp_gpio",
  131. .ngpio = ZYNQMP_GPIO_NR_GPIOS,
  132. .max_bank = ZYNQMP_GPIO_MAX_BANK,
  133. .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(MP),
  134. .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(MP),
  135. .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(MP),
  136. .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(MP),
  137. .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(MP),
  138. .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(MP),
  139. .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(MP),
  140. .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(MP),
  141. .bank_min[4] = ZYNQ_GPIO_BANK4_PIN_MIN(MP),
  142. .bank_max[4] = ZYNQ_GPIO_BANK4_PIN_MAX(MP),
  143. .bank_min[5] = ZYNQ_GPIO_BANK5_PIN_MIN(MP),
  144. .bank_max[5] = ZYNQ_GPIO_BANK5_PIN_MAX(MP),
  145. };
  146. static const struct zynq_platform_data zynq_gpio_def = {
  147. .label = "zynq_gpio",
  148. .ngpio = ZYNQ_GPIO_NR_GPIOS,
  149. .max_bank = ZYNQ_GPIO_MAX_BANK,
  150. .bank_min[0] = ZYNQ_GPIO_BANK0_PIN_MIN(),
  151. .bank_max[0] = ZYNQ_GPIO_BANK0_PIN_MAX(),
  152. .bank_min[1] = ZYNQ_GPIO_BANK1_PIN_MIN(),
  153. .bank_max[1] = ZYNQ_GPIO_BANK1_PIN_MAX(),
  154. .bank_min[2] = ZYNQ_GPIO_BANK2_PIN_MIN(),
  155. .bank_max[2] = ZYNQ_GPIO_BANK2_PIN_MAX(),
  156. .bank_min[3] = ZYNQ_GPIO_BANK3_PIN_MIN(),
  157. .bank_max[3] = ZYNQ_GPIO_BANK3_PIN_MAX(),
  158. };
  159. /**
  160. * zynq_gpio_get_bank_pin - Get the bank number and pin number within that bank
  161. * for a given pin in the GPIO device
  162. * @pin_num: gpio pin number within the device
  163. * @bank_num: an output parameter used to return the bank number of the gpio
  164. * pin
  165. * @bank_pin_num: an output parameter used to return pin number within a bank
  166. * for the given gpio pin
  167. *
  168. * Returns the bank number and pin offset within the bank.
  169. */
  170. static inline void zynq_gpio_get_bank_pin(unsigned int pin_num,
  171. unsigned int *bank_num,
  172. unsigned int *bank_pin_num,
  173. struct udevice *dev)
  174. {
  175. struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
  176. u32 bank;
  177. for (bank = 0; bank < platdata->p_data->max_bank; bank++) {
  178. if (pin_num >= platdata->p_data->bank_min[bank] &&
  179. pin_num <= platdata->p_data->bank_max[bank]) {
  180. *bank_num = bank;
  181. *bank_pin_num = pin_num -
  182. platdata->p_data->bank_min[bank];
  183. return;
  184. }
  185. }
  186. if (bank >= platdata->p_data->max_bank) {
  187. printf("Invalid bank and pin num\n");
  188. *bank_num = 0;
  189. *bank_pin_num = 0;
  190. }
  191. }
  192. static int gpio_is_valid(unsigned gpio, struct udevice *dev)
  193. {
  194. struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
  195. return gpio < platdata->p_data->ngpio;
  196. }
  197. static int check_gpio(unsigned gpio, struct udevice *dev)
  198. {
  199. if (!gpio_is_valid(gpio, dev)) {
  200. printf("ERROR : check_gpio: invalid GPIO %d\n", gpio);
  201. return -1;
  202. }
  203. return 0;
  204. }
  205. static int zynq_gpio_get_value(struct udevice *dev, unsigned gpio)
  206. {
  207. u32 data;
  208. unsigned int bank_num, bank_pin_num;
  209. struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
  210. if (check_gpio(gpio, dev) < 0)
  211. return -1;
  212. zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
  213. data = readl(platdata->base +
  214. ZYNQ_GPIO_DATA_RO_OFFSET(bank_num));
  215. return (data >> bank_pin_num) & 1;
  216. }
  217. static int zynq_gpio_set_value(struct udevice *dev, unsigned gpio, int value)
  218. {
  219. unsigned int reg_offset, bank_num, bank_pin_num;
  220. struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
  221. if (check_gpio(gpio, dev) < 0)
  222. return -1;
  223. zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
  224. if (bank_pin_num >= ZYNQ_GPIO_MID_PIN_NUM) {
  225. /* only 16 data bits in bit maskable reg */
  226. bank_pin_num -= ZYNQ_GPIO_MID_PIN_NUM;
  227. reg_offset = ZYNQ_GPIO_DATA_MSW_OFFSET(bank_num);
  228. } else {
  229. reg_offset = ZYNQ_GPIO_DATA_LSW_OFFSET(bank_num);
  230. }
  231. /*
  232. * get the 32 bit value to be written to the mask/data register where
  233. * the upper 16 bits is the mask and lower 16 bits is the data
  234. */
  235. value = !!value;
  236. value = ~(1 << (bank_pin_num + ZYNQ_GPIO_MID_PIN_NUM)) &
  237. ((value << bank_pin_num) | ZYNQ_GPIO_UPPER_MASK);
  238. writel(value, platdata->base + reg_offset);
  239. return 0;
  240. }
  241. static int zynq_gpio_direction_input(struct udevice *dev, unsigned gpio)
  242. {
  243. u32 reg;
  244. unsigned int bank_num, bank_pin_num;
  245. struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
  246. if (check_gpio(gpio, dev) < 0)
  247. return -1;
  248. zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
  249. /* bank 0 pins 7 and 8 are special and cannot be used as inputs */
  250. if (bank_num == 0 && (bank_pin_num == 7 || bank_pin_num == 8))
  251. return -1;
  252. /* clear the bit in direction mode reg to set the pin as input */
  253. reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
  254. reg &= ~BIT(bank_pin_num);
  255. writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
  256. return 0;
  257. }
  258. static int zynq_gpio_direction_output(struct udevice *dev, unsigned gpio,
  259. int value)
  260. {
  261. u32 reg;
  262. unsigned int bank_num, bank_pin_num;
  263. struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
  264. if (check_gpio(gpio, dev) < 0)
  265. return -1;
  266. zynq_gpio_get_bank_pin(gpio, &bank_num, &bank_pin_num, dev);
  267. /* set the GPIO pin as output */
  268. reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
  269. reg |= BIT(bank_pin_num);
  270. writel(reg, platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
  271. /* configure the output enable reg for the pin */
  272. reg = readl(platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
  273. reg |= BIT(bank_pin_num);
  274. writel(reg, platdata->base + ZYNQ_GPIO_OUTEN_OFFSET(bank_num));
  275. /* set the state of the pin */
  276. zynq_gpio_set_value(dev, gpio, value);
  277. return 0;
  278. }
  279. static int zynq_gpio_get_function(struct udevice *dev, unsigned offset)
  280. {
  281. u32 reg;
  282. unsigned int bank_num, bank_pin_num;
  283. struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
  284. if (check_gpio(offset, dev) < 0)
  285. return -1;
  286. zynq_gpio_get_bank_pin(offset, &bank_num, &bank_pin_num, dev);
  287. /* set the GPIO pin as output */
  288. reg = readl(platdata->base + ZYNQ_GPIO_DIRM_OFFSET(bank_num));
  289. reg &= BIT(bank_pin_num);
  290. if (reg)
  291. return GPIOF_OUTPUT;
  292. else
  293. return GPIOF_INPUT;
  294. }
  295. static const struct dm_gpio_ops gpio_zynq_ops = {
  296. .direction_input = zynq_gpio_direction_input,
  297. .direction_output = zynq_gpio_direction_output,
  298. .get_value = zynq_gpio_get_value,
  299. .set_value = zynq_gpio_set_value,
  300. .get_function = zynq_gpio_get_function,
  301. };
  302. static const struct udevice_id zynq_gpio_ids[] = {
  303. { .compatible = "xlnx,zynq-gpio-1.0",
  304. .data = (ulong)&zynq_gpio_def},
  305. { .compatible = "xlnx,zynqmp-gpio-1.0",
  306. .data = (ulong)&zynqmp_gpio_def},
  307. { .compatible = "xlnx,versal-gpio-1.0",
  308. .data = (ulong)&versal_gpio_def},
  309. { .compatible = "xlnx,pmc-gpio-1.0",
  310. .data = (ulong)&pmc_gpio_def },
  311. { }
  312. };
  313. static int zynq_gpio_probe(struct udevice *dev)
  314. {
  315. struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
  316. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  317. const void *label_ptr;
  318. label_ptr = dev_read_prop(dev, "label", NULL);
  319. if (label_ptr) {
  320. uc_priv->bank_name = strdup(label_ptr);
  321. if (!uc_priv->bank_name)
  322. return -ENOMEM;
  323. } else {
  324. uc_priv->bank_name = dev->name;
  325. }
  326. if (platdata->p_data)
  327. uc_priv->gpio_count = platdata->p_data->ngpio;
  328. return 0;
  329. }
  330. static int zynq_gpio_ofdata_to_platdata(struct udevice *dev)
  331. {
  332. struct zynq_gpio_platdata *platdata = dev_get_platdata(dev);
  333. platdata->base = (phys_addr_t)dev_read_addr(dev);
  334. platdata->p_data =
  335. (struct zynq_platform_data *)dev_get_driver_data(dev);
  336. return 0;
  337. }
  338. U_BOOT_DRIVER(gpio_zynq) = {
  339. .name = "gpio_zynq",
  340. .id = UCLASS_GPIO,
  341. .ops = &gpio_zynq_ops,
  342. .of_match = zynq_gpio_ids,
  343. .ofdata_to_platdata = zynq_gpio_ofdata_to_platdata,
  344. .probe = zynq_gpio_probe,
  345. .platdata_auto_alloc_size = sizeof(struct zynq_gpio_platdata),
  346. };