tegra_gpio.c 9.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * NVIDIA Tegra20 GPIO handling.
  4. * (C) Copyright 2010-2012,2015
  5. * NVIDIA Corporation <www.nvidia.com>
  6. */
  7. /*
  8. * Based on (mostly copied from) kw_gpio.c based Linux 2.6 kernel driver.
  9. * Tom Warren (twarren@nvidia.com)
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <log.h>
  14. #include <malloc.h>
  15. #include <errno.h>
  16. #include <fdtdec.h>
  17. #include <asm/io.h>
  18. #include <asm/bitops.h>
  19. #include <asm/arch/tegra.h>
  20. #include <asm/gpio.h>
  21. #include <dm/device-internal.h>
  22. #include <dt-bindings/gpio/gpio.h>
  23. static const int CONFIG_SFIO = 0;
  24. static const int CONFIG_GPIO = 1;
  25. static const int DIRECTION_INPUT = 0;
  26. static const int DIRECTION_OUTPUT = 1;
  27. struct tegra_gpio_platdata {
  28. struct gpio_ctlr_bank *bank;
  29. const char *port_name; /* Name of port, e.g. "B" */
  30. int base_gpio; /* Port number for this port (0, 1,.., n-1) */
  31. };
  32. /* Information about each port at run-time */
  33. struct tegra_port_info {
  34. struct gpio_ctlr_bank *bank;
  35. int base_gpio; /* Port number for this port (0, 1,.., n-1) */
  36. };
  37. /* Return config of pin 'gpio' as GPIO (1) or SFIO (0) */
  38. static int get_config(unsigned gpio)
  39. {
  40. struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  41. struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  42. u32 u;
  43. int type;
  44. u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
  45. type = (u >> GPIO_BIT(gpio)) & 1;
  46. debug("get_config: port = %d, bit = %d is %s\n",
  47. GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
  48. return type ? CONFIG_GPIO : CONFIG_SFIO;
  49. }
  50. /* Config pin 'gpio' as GPIO or SFIO, based on 'type' */
  51. static void set_config(unsigned gpio, int type)
  52. {
  53. struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  54. struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  55. u32 u;
  56. debug("set_config: port = %d, bit = %d, %s\n",
  57. GPIO_FULLPORT(gpio), GPIO_BIT(gpio), type ? "GPIO" : "SFPIO");
  58. u = readl(&bank->gpio_config[GPIO_PORT(gpio)]);
  59. if (type != CONFIG_SFIO)
  60. u |= 1 << GPIO_BIT(gpio);
  61. else
  62. u &= ~(1 << GPIO_BIT(gpio));
  63. writel(u, &bank->gpio_config[GPIO_PORT(gpio)]);
  64. }
  65. /* Return GPIO pin 'gpio' direction - 0 = input or 1 = output */
  66. static int get_direction(unsigned gpio)
  67. {
  68. struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  69. struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  70. u32 u;
  71. int dir;
  72. u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
  73. dir = (u >> GPIO_BIT(gpio)) & 1;
  74. debug("get_direction: port = %d, bit = %d, %s\n",
  75. GPIO_FULLPORT(gpio), GPIO_BIT(gpio), dir ? "OUT" : "IN");
  76. return dir ? DIRECTION_OUTPUT : DIRECTION_INPUT;
  77. }
  78. /* Config GPIO pin 'gpio' as input or output (OE) as per 'output' */
  79. static void set_direction(unsigned gpio, int output)
  80. {
  81. struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  82. struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  83. u32 u;
  84. debug("set_direction: port = %d, bit = %d, %s\n",
  85. GPIO_FULLPORT(gpio), GPIO_BIT(gpio), output ? "OUT" : "IN");
  86. u = readl(&bank->gpio_dir_out[GPIO_PORT(gpio)]);
  87. if (output != DIRECTION_INPUT)
  88. u |= 1 << GPIO_BIT(gpio);
  89. else
  90. u &= ~(1 << GPIO_BIT(gpio));
  91. writel(u, &bank->gpio_dir_out[GPIO_PORT(gpio)]);
  92. }
  93. /* set GPIO pin 'gpio' output bit as 0 or 1 as per 'high' */
  94. static void set_level(unsigned gpio, int high)
  95. {
  96. struct gpio_ctlr *ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  97. struct gpio_ctlr_bank *bank = &ctlr->gpio_bank[GPIO_BANK(gpio)];
  98. u32 u;
  99. debug("set_level: port = %d, bit %d == %d\n",
  100. GPIO_FULLPORT(gpio), GPIO_BIT(gpio), high);
  101. u = readl(&bank->gpio_out[GPIO_PORT(gpio)]);
  102. if (high)
  103. u |= 1 << GPIO_BIT(gpio);
  104. else
  105. u &= ~(1 << GPIO_BIT(gpio));
  106. writel(u, &bank->gpio_out[GPIO_PORT(gpio)]);
  107. }
  108. /*
  109. * Generic_GPIO primitives.
  110. */
  111. /* set GPIO pin 'gpio' as an input */
  112. static int tegra_gpio_direction_input(struct udevice *dev, unsigned offset)
  113. {
  114. struct tegra_port_info *state = dev_get_priv(dev);
  115. /* Configure GPIO direction as input. */
  116. set_direction(state->base_gpio + offset, DIRECTION_INPUT);
  117. /* Enable the pin as a GPIO */
  118. set_config(state->base_gpio + offset, 1);
  119. return 0;
  120. }
  121. /* set GPIO pin 'gpio' as an output, with polarity 'value' */
  122. static int tegra_gpio_direction_output(struct udevice *dev, unsigned offset,
  123. int value)
  124. {
  125. struct tegra_port_info *state = dev_get_priv(dev);
  126. int gpio = state->base_gpio + offset;
  127. /* Configure GPIO output value. */
  128. set_level(gpio, value);
  129. /* Configure GPIO direction as output. */
  130. set_direction(gpio, DIRECTION_OUTPUT);
  131. /* Enable the pin as a GPIO */
  132. set_config(state->base_gpio + offset, 1);
  133. return 0;
  134. }
  135. /* read GPIO IN value of pin 'gpio' */
  136. static int tegra_gpio_get_value(struct udevice *dev, unsigned offset)
  137. {
  138. struct tegra_port_info *state = dev_get_priv(dev);
  139. int gpio = state->base_gpio + offset;
  140. int val;
  141. debug("%s: pin = %d (port %d:bit %d)\n", __func__,
  142. gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio));
  143. if (get_direction(gpio) == DIRECTION_INPUT)
  144. val = readl(&state->bank->gpio_in[GPIO_PORT(gpio)]);
  145. else
  146. val = readl(&state->bank->gpio_out[GPIO_PORT(gpio)]);
  147. return (val >> GPIO_BIT(gpio)) & 1;
  148. }
  149. /* write GPIO OUT value to pin 'gpio' */
  150. static int tegra_gpio_set_value(struct udevice *dev, unsigned offset, int value)
  151. {
  152. struct tegra_port_info *state = dev_get_priv(dev);
  153. int gpio = state->base_gpio + offset;
  154. debug("gpio_set_value: pin = %d (port %d:bit %d), value = %d\n",
  155. gpio, GPIO_FULLPORT(gpio), GPIO_BIT(gpio), value);
  156. /* Configure GPIO output value. */
  157. set_level(gpio, value);
  158. return 0;
  159. }
  160. void gpio_config_table(const struct tegra_gpio_config *config, int len)
  161. {
  162. int i;
  163. for (i = 0; i < len; i++) {
  164. switch (config[i].init) {
  165. case TEGRA_GPIO_INIT_IN:
  166. set_direction(config[i].gpio, DIRECTION_INPUT);
  167. break;
  168. case TEGRA_GPIO_INIT_OUT0:
  169. set_level(config[i].gpio, 0);
  170. set_direction(config[i].gpio, DIRECTION_OUTPUT);
  171. break;
  172. case TEGRA_GPIO_INIT_OUT1:
  173. set_level(config[i].gpio, 1);
  174. set_direction(config[i].gpio, DIRECTION_OUTPUT);
  175. break;
  176. }
  177. set_config(config[i].gpio, CONFIG_GPIO);
  178. }
  179. }
  180. static int tegra_gpio_get_function(struct udevice *dev, unsigned offset)
  181. {
  182. struct tegra_port_info *state = dev_get_priv(dev);
  183. int gpio = state->base_gpio + offset;
  184. if (!get_config(gpio))
  185. return GPIOF_FUNC;
  186. else if (get_direction(gpio))
  187. return GPIOF_OUTPUT;
  188. else
  189. return GPIOF_INPUT;
  190. }
  191. static int tegra_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,
  192. struct ofnode_phandle_args *args)
  193. {
  194. int gpio, port, ret;
  195. gpio = args->args[0];
  196. port = gpio / TEGRA_GPIOS_PER_PORT;
  197. ret = device_get_child(dev, port, &desc->dev);
  198. if (ret)
  199. return ret;
  200. desc->offset = gpio % TEGRA_GPIOS_PER_PORT;
  201. desc->flags = args->args[1] & GPIO_ACTIVE_LOW ? GPIOD_ACTIVE_LOW : 0;
  202. return 0;
  203. }
  204. static const struct dm_gpio_ops gpio_tegra_ops = {
  205. .direction_input = tegra_gpio_direction_input,
  206. .direction_output = tegra_gpio_direction_output,
  207. .get_value = tegra_gpio_get_value,
  208. .set_value = tegra_gpio_set_value,
  209. .get_function = tegra_gpio_get_function,
  210. .xlate = tegra_gpio_xlate,
  211. };
  212. /**
  213. * Returns the name of a GPIO port
  214. *
  215. * GPIOs are named A, B, C, ..., Z, AA, BB, CC, ...
  216. *
  217. * @base_port: Base port number (0, 1..n-1)
  218. * @return allocated string containing the name
  219. */
  220. static char *gpio_port_name(int base_port)
  221. {
  222. char *name, *s;
  223. name = malloc(3);
  224. if (name) {
  225. s = name;
  226. *s++ = 'A' + (base_port % 26);
  227. if (base_port >= 26)
  228. *s++ = *name;
  229. *s = '\0';
  230. }
  231. return name;
  232. }
  233. static const struct udevice_id tegra_gpio_ids[] = {
  234. { .compatible = "nvidia,tegra30-gpio" },
  235. { .compatible = "nvidia,tegra20-gpio" },
  236. { }
  237. };
  238. static int gpio_tegra_probe(struct udevice *dev)
  239. {
  240. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  241. struct tegra_port_info *priv = dev->priv;
  242. struct tegra_gpio_platdata *plat = dev->platdata;
  243. /* Only child devices have ports */
  244. if (!plat)
  245. return 0;
  246. priv->bank = plat->bank;
  247. priv->base_gpio = plat->base_gpio;
  248. uc_priv->gpio_count = TEGRA_GPIOS_PER_PORT;
  249. uc_priv->bank_name = plat->port_name;
  250. return 0;
  251. }
  252. /**
  253. * We have a top-level GPIO device with no actual GPIOs. It has a child
  254. * device for each Tegra port.
  255. */
  256. static int gpio_tegra_bind(struct udevice *parent)
  257. {
  258. struct tegra_gpio_platdata *plat = parent->platdata;
  259. struct gpio_ctlr *ctlr;
  260. int bank_count;
  261. int bank;
  262. int ret;
  263. /* If this is a child device, there is nothing to do here */
  264. if (plat)
  265. return 0;
  266. /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
  267. #ifdef CONFIG_SPL_BUILD
  268. ctlr = (struct gpio_ctlr *)NV_PA_GPIO_BASE;
  269. bank_count = TEGRA_GPIO_BANKS;
  270. #else
  271. {
  272. int len;
  273. /*
  274. * This driver does not make use of interrupts, other than to figure
  275. * out the number of GPIO banks
  276. */
  277. len = dev_read_size(parent, "interrupts");
  278. if (len < 0)
  279. return len;
  280. bank_count = len / 3 / sizeof(u32);
  281. ctlr = (struct gpio_ctlr *)dev_read_addr(parent);
  282. if ((ulong)ctlr == FDT_ADDR_T_NONE)
  283. return -EINVAL;
  284. }
  285. #endif
  286. for (bank = 0; bank < bank_count; bank++) {
  287. int port;
  288. for (port = 0; port < TEGRA_PORTS_PER_BANK; port++) {
  289. struct tegra_gpio_platdata *plat;
  290. struct udevice *dev;
  291. int base_port;
  292. plat = calloc(1, sizeof(*plat));
  293. if (!plat)
  294. return -ENOMEM;
  295. plat->bank = &ctlr->gpio_bank[bank];
  296. base_port = bank * TEGRA_PORTS_PER_BANK + port;
  297. plat->base_gpio = TEGRA_GPIOS_PER_PORT * base_port;
  298. plat->port_name = gpio_port_name(base_port);
  299. ret = device_bind(parent, parent->driver,
  300. plat->port_name, plat, -1, &dev);
  301. if (ret)
  302. return ret;
  303. dev_set_of_offset(dev, dev_of_offset(parent));
  304. }
  305. }
  306. return 0;
  307. }
  308. U_BOOT_DRIVER(gpio_tegra) = {
  309. .name = "gpio_tegra",
  310. .id = UCLASS_GPIO,
  311. .of_match = tegra_gpio_ids,
  312. .bind = gpio_tegra_bind,
  313. .probe = gpio_tegra_probe,
  314. .priv_auto_alloc_size = sizeof(struct tegra_port_info),
  315. .ops = &gpio_tegra_ops,
  316. };