pcf8575_gpio.c 4.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * PCF8575 I2C GPIO EXPANDER DRIVER
  4. *
  5. * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/
  6. *
  7. * Vignesh R <vigneshr@ti.com>
  8. *
  9. *
  10. * Driver for TI PCF-8575 16-bit I2C gpio expander. Based on
  11. * gpio-pcf857x Linux Kernel(v4.7) driver.
  12. *
  13. * Copyright (C) 2007 David Brownell
  14. *
  15. */
  16. /*
  17. * NOTE: The driver and devicetree bindings are borrowed from Linux
  18. * Kernel, but driver does not support all PCF857x devices. It currently
  19. * supports PCF8575 16-bit expander by TI and NXP.
  20. *
  21. * TODO(vigneshr@ti.com):
  22. * Support 8 bit PCF857x compatible expanders.
  23. */
  24. #include <common.h>
  25. #include <dm.h>
  26. #include <i2c.h>
  27. #include <log.h>
  28. #include <asm-generic/gpio.h>
  29. #include <linux/bitops.h>
  30. DECLARE_GLOBAL_DATA_PTR;
  31. struct pcf8575_chip {
  32. int gpio_count; /* No. GPIOs supported by the chip */
  33. /* NOTE: these chips have strange "quasi-bidirectional" I/O pins.
  34. * We can't actually know whether a pin is configured (a) as output
  35. * and driving the signal low, or (b) as input and reporting a low
  36. * value ... without knowing the last value written since the chip
  37. * came out of reset (if any). We can't read the latched output.
  38. * In short, the only reliable solution for setting up pin direction
  39. * is to do it explicitly.
  40. *
  41. * Using "out" avoids that trouble. When left initialized to zero,
  42. * our software copy of the "latch" then matches the chip's all-ones
  43. * reset state. Otherwise it flags pins to be driven low.
  44. */
  45. unsigned int out; /* software latch */
  46. const char *bank_name; /* Name of the expander bank */
  47. };
  48. /* Read/Write to 16-bit I/O expander */
  49. static int pcf8575_i2c_write_le16(struct udevice *dev, unsigned int word)
  50. {
  51. struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
  52. u8 buf[2] = { word & 0xff, word >> 8, };
  53. int ret;
  54. ret = dm_i2c_write(dev, 0, buf, 2);
  55. if (ret)
  56. printf("%s i2c write failed to addr %x\n", __func__,
  57. chip->chip_addr);
  58. return ret;
  59. }
  60. static int pcf8575_i2c_read_le16(struct udevice *dev)
  61. {
  62. struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
  63. u8 buf[2];
  64. int ret;
  65. ret = dm_i2c_read(dev, 0, buf, 2);
  66. if (ret) {
  67. printf("%s i2c read failed from addr %x\n", __func__,
  68. chip->chip_addr);
  69. return ret;
  70. }
  71. return (buf[1] << 8) | buf[0];
  72. }
  73. static int pcf8575_direction_input(struct udevice *dev, unsigned offset)
  74. {
  75. struct pcf8575_chip *plat = dev_get_platdata(dev);
  76. int status;
  77. plat->out |= BIT(offset);
  78. status = pcf8575_i2c_write_le16(dev, plat->out);
  79. return status;
  80. }
  81. static int pcf8575_direction_output(struct udevice *dev,
  82. unsigned int offset, int value)
  83. {
  84. struct pcf8575_chip *plat = dev_get_platdata(dev);
  85. int ret;
  86. if (value)
  87. plat->out |= BIT(offset);
  88. else
  89. plat->out &= ~BIT(offset);
  90. ret = pcf8575_i2c_write_le16(dev, plat->out);
  91. return ret;
  92. }
  93. static int pcf8575_get_value(struct udevice *dev, unsigned int offset)
  94. {
  95. int value;
  96. value = pcf8575_i2c_read_le16(dev);
  97. return (value < 0) ? value : ((value & BIT(offset)) >> offset);
  98. }
  99. static int pcf8575_set_value(struct udevice *dev, unsigned int offset,
  100. int value)
  101. {
  102. return pcf8575_direction_output(dev, offset, value);
  103. }
  104. static int pcf8575_ofdata_platdata(struct udevice *dev)
  105. {
  106. struct pcf8575_chip *plat = dev_get_platdata(dev);
  107. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  108. int n_latch;
  109. uc_priv->gpio_count = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),
  110. "gpio-count", 16);
  111. uc_priv->bank_name = fdt_getprop(gd->fdt_blob, dev_of_offset(dev),
  112. "gpio-bank-name", NULL);
  113. if (!uc_priv->bank_name)
  114. uc_priv->bank_name = fdt_get_name(gd->fdt_blob,
  115. dev_of_offset(dev), NULL);
  116. n_latch = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev),
  117. "lines-initial-states", 0);
  118. plat->out = ~n_latch;
  119. return 0;
  120. }
  121. static int pcf8575_gpio_probe(struct udevice *dev)
  122. {
  123. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  124. debug("%s GPIO controller with %d gpios probed\n",
  125. uc_priv->bank_name, uc_priv->gpio_count);
  126. return 0;
  127. }
  128. static const struct dm_gpio_ops pcf8575_gpio_ops = {
  129. .direction_input = pcf8575_direction_input,
  130. .direction_output = pcf8575_direction_output,
  131. .get_value = pcf8575_get_value,
  132. .set_value = pcf8575_set_value,
  133. };
  134. static const struct udevice_id pcf8575_gpio_ids[] = {
  135. { .compatible = "nxp,pcf8575" },
  136. { .compatible = "ti,pcf8575" },
  137. { }
  138. };
  139. U_BOOT_DRIVER(gpio_pcf8575) = {
  140. .name = "gpio_pcf8575",
  141. .id = UCLASS_GPIO,
  142. .ops = &pcf8575_gpio_ops,
  143. .of_match = pcf8575_gpio_ids,
  144. .ofdata_to_platdata = pcf8575_ofdata_platdata,
  145. .probe = pcf8575_gpio_probe,
  146. .platdata_auto_alloc_size = sizeof(struct pcf8575_chip),
  147. };