mpc8xxx_gpio.c 5.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016
  4. * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
  5. *
  6. * based on arch/powerpc/include/asm/mpc85xx_gpio.h, which is
  7. *
  8. * Copyright 2010 eXMeritus, A Boeing Company
  9. */
  10. #include <common.h>
  11. #include <dm.h>
  12. #include <mapmem.h>
  13. #include <asm/gpio.h>
  14. struct ccsr_gpio {
  15. u32 gpdir;
  16. u32 gpodr;
  17. u32 gpdat;
  18. u32 gpier;
  19. u32 gpimr;
  20. u32 gpicr;
  21. };
  22. struct mpc8xxx_gpio_data {
  23. /* The bank's register base in memory */
  24. struct ccsr_gpio __iomem *base;
  25. /* The address of the registers; used to identify the bank */
  26. ulong addr;
  27. /* The GPIO count of the bank */
  28. uint gpio_count;
  29. /* The GPDAT register cannot be used to determine the value of output
  30. * pins on MPC8572/MPC8536, so we shadow it and use the shadowed value
  31. * for output pins
  32. */
  33. u32 dat_shadow;
  34. ulong type;
  35. };
  36. enum {
  37. MPC8XXX_GPIO_TYPE,
  38. MPC5121_GPIO_TYPE,
  39. };
  40. inline u32 gpio_mask(uint gpio)
  41. {
  42. return (1U << (31 - (gpio)));
  43. }
  44. static inline u32 mpc8xxx_gpio_get_val(struct ccsr_gpio *base, u32 mask)
  45. {
  46. return in_be32(&base->gpdat) & mask;
  47. }
  48. static inline u32 mpc8xxx_gpio_get_dir(struct ccsr_gpio *base, u32 mask)
  49. {
  50. return in_be32(&base->gpdir) & mask;
  51. }
  52. static inline int mpc8xxx_gpio_open_drain_val(struct ccsr_gpio *base, u32 mask)
  53. {
  54. return in_be32(&base->gpodr) & mask;
  55. }
  56. static inline void mpc8xxx_gpio_open_drain_on(struct ccsr_gpio *base, u32
  57. gpios)
  58. {
  59. /* GPODR register 1 -> open drain on */
  60. setbits_be32(&base->gpodr, gpios);
  61. }
  62. static inline void mpc8xxx_gpio_open_drain_off(struct ccsr_gpio *base,
  63. u32 gpios)
  64. {
  65. /* GPODR register 0 -> open drain off (actively driven) */
  66. clrbits_be32(&base->gpodr, gpios);
  67. }
  68. static int mpc8xxx_gpio_direction_input(struct udevice *dev, uint gpio)
  69. {
  70. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  71. u32 mask = gpio_mask(gpio);
  72. /* GPDIR register 0 -> input */
  73. clrbits_be32(&data->base->gpdir, mask);
  74. return 0;
  75. }
  76. static int mpc8xxx_gpio_set_value(struct udevice *dev, uint gpio, int value)
  77. {
  78. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  79. struct ccsr_gpio *base = data->base;
  80. u32 mask = gpio_mask(gpio);
  81. u32 gpdir;
  82. if (value) {
  83. data->dat_shadow |= mask;
  84. } else {
  85. data->dat_shadow &= ~mask;
  86. }
  87. gpdir = in_be32(&base->gpdir);
  88. gpdir |= gpio_mask(gpio);
  89. out_be32(&base->gpdat, gpdir & data->dat_shadow);
  90. out_be32(&base->gpdir, gpdir);
  91. return 0;
  92. }
  93. static int mpc8xxx_gpio_direction_output(struct udevice *dev, uint gpio,
  94. int value)
  95. {
  96. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  97. /* GPIO 28..31 are input only on MPC5121 */
  98. if (data->type == MPC5121_GPIO_TYPE && gpio >= 28)
  99. return -EINVAL;
  100. return mpc8xxx_gpio_set_value(dev, gpio, value);
  101. }
  102. static int mpc8xxx_gpio_get_value(struct udevice *dev, uint gpio)
  103. {
  104. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  105. if (!!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio))) {
  106. /* Output -> use shadowed value */
  107. return !!(data->dat_shadow & gpio_mask(gpio));
  108. }
  109. /* Input -> read value from GPDAT register */
  110. return !!mpc8xxx_gpio_get_val(data->base, gpio_mask(gpio));
  111. }
  112. static int mpc8xxx_gpio_get_function(struct udevice *dev, uint gpio)
  113. {
  114. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  115. int dir;
  116. dir = !!mpc8xxx_gpio_get_dir(data->base, gpio_mask(gpio));
  117. return dir ? GPIOF_OUTPUT : GPIOF_INPUT;
  118. }
  119. #if CONFIG_IS_ENABLED(OF_CONTROL)
  120. static int mpc8xxx_gpio_ofdata_to_platdata(struct udevice *dev)
  121. {
  122. struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
  123. fdt_addr_t addr;
  124. u32 reg[2];
  125. dev_read_u32_array(dev, "reg", reg, 2);
  126. addr = dev_translate_address(dev, reg);
  127. plat->addr = addr;
  128. plat->size = reg[1];
  129. plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
  130. return 0;
  131. }
  132. #endif
  133. static int mpc8xxx_gpio_platdata_to_priv(struct udevice *dev)
  134. {
  135. struct mpc8xxx_gpio_data *priv = dev_get_priv(dev);
  136. struct mpc8xxx_gpio_plat *plat = dev_get_platdata(dev);
  137. unsigned long size = plat->size;
  138. ulong driver_data = dev_get_driver_data(dev);
  139. if (size == 0)
  140. size = 0x100;
  141. priv->addr = plat->addr;
  142. priv->base = map_sysmem(plat->addr, size);
  143. if (!priv->base)
  144. return -ENOMEM;
  145. priv->gpio_count = plat->ngpios;
  146. priv->dat_shadow = 0;
  147. priv->type = driver_data;
  148. return 0;
  149. }
  150. static int mpc8xxx_gpio_probe(struct udevice *dev)
  151. {
  152. struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  153. struct mpc8xxx_gpio_data *data = dev_get_priv(dev);
  154. char name[32], *str;
  155. mpc8xxx_gpio_platdata_to_priv(dev);
  156. snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
  157. str = strdup(name);
  158. if (!str)
  159. return -ENOMEM;
  160. uc_priv->bank_name = str;
  161. uc_priv->gpio_count = data->gpio_count;
  162. return 0;
  163. }
  164. static const struct dm_gpio_ops gpio_mpc8xxx_ops = {
  165. .direction_input = mpc8xxx_gpio_direction_input,
  166. .direction_output = mpc8xxx_gpio_direction_output,
  167. .get_value = mpc8xxx_gpio_get_value,
  168. .set_value = mpc8xxx_gpio_set_value,
  169. .get_function = mpc8xxx_gpio_get_function,
  170. };
  171. static const struct udevice_id mpc8xxx_gpio_ids[] = {
  172. { .compatible = "fsl,pq3-gpio", .data = MPC8XXX_GPIO_TYPE },
  173. { .compatible = "fsl,mpc8308-gpio", .data = MPC8XXX_GPIO_TYPE },
  174. { .compatible = "fsl,mpc8349-gpio", .data = MPC8XXX_GPIO_TYPE },
  175. { .compatible = "fsl,mpc8572-gpio", .data = MPC8XXX_GPIO_TYPE},
  176. { .compatible = "fsl,mpc8610-gpio", .data = MPC8XXX_GPIO_TYPE},
  177. { .compatible = "fsl,mpc5121-gpio", .data = MPC5121_GPIO_TYPE, },
  178. { .compatible = "fsl,qoriq-gpio", .data = MPC8XXX_GPIO_TYPE },
  179. { /* sentinel */ }
  180. };
  181. U_BOOT_DRIVER(gpio_mpc8xxx) = {
  182. .name = "gpio_mpc8xxx",
  183. .id = UCLASS_GPIO,
  184. .ops = &gpio_mpc8xxx_ops,
  185. #if CONFIG_IS_ENABLED(OF_CONTROL)
  186. .ofdata_to_platdata = mpc8xxx_gpio_ofdata_to_platdata,
  187. .platdata_auto_alloc_size = sizeof(struct mpc8xxx_gpio_plat),
  188. .of_match = mpc8xxx_gpio_ids,
  189. #endif
  190. .probe = mpc8xxx_gpio_probe,
  191. .priv_auto_alloc_size = sizeof(struct mpc8xxx_gpio_data),
  192. };