keystone_nav.c 7.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Multicore Navigator driver for TI Keystone 2 devices.
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/ti-common/keystone_nav.h>
  11. #include <linux/delay.h>
  12. struct qm_config qm_memmap = {
  13. .stat_cfg = CONFIG_KSNAV_QM_QUEUE_STATUS_BASE,
  14. .queue = (void *)CONFIG_KSNAV_QM_MANAGER_QUEUES_BASE,
  15. .mngr_vbusm = CONFIG_KSNAV_QM_BASE_ADDRESS,
  16. .i_lram = CONFIG_KSNAV_QM_LINK_RAM_BASE,
  17. .proxy = (void *)CONFIG_KSNAV_QM_MANAGER_Q_PROXY_BASE,
  18. .status_ram = CONFIG_KSNAV_QM_STATUS_RAM_BASE,
  19. .mngr_cfg = (void *)CONFIG_KSNAV_QM_CONF_BASE,
  20. .intd_cfg = CONFIG_KSNAV_QM_INTD_CONF_BASE,
  21. .desc_mem = (void *)CONFIG_KSNAV_QM_DESC_SETUP_BASE,
  22. .region_num = CONFIG_KSNAV_QM_REGION_NUM,
  23. .pdsp_cmd = CONFIG_KSNAV_QM_PDSP1_CMD_BASE,
  24. .pdsp_ctl = CONFIG_KSNAV_QM_PDSP1_CTRL_BASE,
  25. .pdsp_iram = CONFIG_KSNAV_QM_PDSP1_IRAM_BASE,
  26. .qpool_num = CONFIG_KSNAV_QM_QPOOL_NUM,
  27. };
  28. /*
  29. * We are going to use only one type of descriptors - host packet
  30. * descriptors. We staticaly allocate memory for them here
  31. */
  32. struct qm_host_desc desc_pool[HDESC_NUM] __aligned(sizeof(struct qm_host_desc));
  33. static struct qm_config *qm_cfg;
  34. inline int num_of_desc_to_reg(int num_descr)
  35. {
  36. int j, num;
  37. for (j = 0, num = 32; j < 15; j++, num *= 2) {
  38. if (num_descr <= num)
  39. return j;
  40. }
  41. return 15;
  42. }
  43. int _qm_init(struct qm_config *cfg)
  44. {
  45. u32 j;
  46. qm_cfg = cfg;
  47. qm_cfg->mngr_cfg->link_ram_base0 = qm_cfg->i_lram;
  48. qm_cfg->mngr_cfg->link_ram_size0 = HDESC_NUM * 8 - 1;
  49. qm_cfg->mngr_cfg->link_ram_base1 = 0;
  50. qm_cfg->mngr_cfg->link_ram_size1 = 0;
  51. qm_cfg->mngr_cfg->link_ram_base2 = 0;
  52. qm_cfg->desc_mem[0].base_addr = (u32)desc_pool;
  53. qm_cfg->desc_mem[0].start_idx = 0;
  54. qm_cfg->desc_mem[0].desc_reg_size =
  55. (((sizeof(struct qm_host_desc) >> 4) - 1) << 16) |
  56. num_of_desc_to_reg(HDESC_NUM);
  57. memset(desc_pool, 0, sizeof(desc_pool));
  58. for (j = 0; j < HDESC_NUM; j++)
  59. qm_push(&desc_pool[j], qm_cfg->qpool_num);
  60. return QM_OK;
  61. }
  62. int qm_init(void)
  63. {
  64. return _qm_init(&qm_memmap);
  65. }
  66. void qm_close(void)
  67. {
  68. u32 j;
  69. queue_close(qm_cfg->qpool_num);
  70. qm_cfg->mngr_cfg->link_ram_base0 = 0;
  71. qm_cfg->mngr_cfg->link_ram_size0 = 0;
  72. qm_cfg->mngr_cfg->link_ram_base1 = 0;
  73. qm_cfg->mngr_cfg->link_ram_size1 = 0;
  74. qm_cfg->mngr_cfg->link_ram_base2 = 0;
  75. for (j = 0; j < qm_cfg->region_num; j++) {
  76. qm_cfg->desc_mem[j].base_addr = 0;
  77. qm_cfg->desc_mem[j].start_idx = 0;
  78. qm_cfg->desc_mem[j].desc_reg_size = 0;
  79. }
  80. qm_cfg = NULL;
  81. }
  82. void qm_push(struct qm_host_desc *hd, u32 qnum)
  83. {
  84. u32 regd;
  85. cpu_to_bus((u32 *)hd, sizeof(struct qm_host_desc)/4);
  86. regd = (u32)hd | ((sizeof(struct qm_host_desc) >> 4) - 1);
  87. writel(regd, &qm_cfg->queue[qnum].ptr_size_thresh);
  88. }
  89. void qm_buff_push(struct qm_host_desc *hd, u32 qnum,
  90. void *buff_ptr, u32 buff_len)
  91. {
  92. hd->orig_buff_len = buff_len;
  93. hd->buff_len = buff_len;
  94. hd->orig_buff_ptr = (u32)buff_ptr;
  95. hd->buff_ptr = (u32)buff_ptr;
  96. qm_push(hd, qnum);
  97. }
  98. struct qm_host_desc *qm_pop(u32 qnum)
  99. {
  100. u32 uhd;
  101. uhd = readl(&qm_cfg->queue[qnum].ptr_size_thresh) & ~0xf;
  102. if (uhd)
  103. cpu_to_bus((u32 *)uhd, sizeof(struct qm_host_desc)/4);
  104. return (struct qm_host_desc *)uhd;
  105. }
  106. struct qm_host_desc *qm_pop_from_free_pool(void)
  107. {
  108. return qm_pop(qm_cfg->qpool_num);
  109. }
  110. void queue_close(u32 qnum)
  111. {
  112. struct qm_host_desc *hd;
  113. while ((hd = qm_pop(qnum)))
  114. ;
  115. }
  116. /**
  117. * DMA API
  118. */
  119. static int ksnav_rx_disable(struct pktdma_cfg *pktdma)
  120. {
  121. u32 j, v, k;
  122. for (j = 0; j < pktdma->rx_ch_num; j++) {
  123. v = readl(&pktdma->rx_ch[j].cfg_a);
  124. if (!(v & CPDMA_CHAN_A_ENABLE))
  125. continue;
  126. writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->rx_ch[j].cfg_a);
  127. for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
  128. udelay(100);
  129. v = readl(&pktdma->rx_ch[j].cfg_a);
  130. if (!(v & CPDMA_CHAN_A_ENABLE))
  131. continue;
  132. }
  133. /* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
  134. }
  135. /* Clear all of the flow registers */
  136. for (j = 0; j < pktdma->rx_flow_num; j++) {
  137. writel(0, &pktdma->rx_flows[j].control);
  138. writel(0, &pktdma->rx_flows[j].tags);
  139. writel(0, &pktdma->rx_flows[j].tag_sel);
  140. writel(0, &pktdma->rx_flows[j].fdq_sel[0]);
  141. writel(0, &pktdma->rx_flows[j].fdq_sel[1]);
  142. writel(0, &pktdma->rx_flows[j].thresh[0]);
  143. writel(0, &pktdma->rx_flows[j].thresh[1]);
  144. writel(0, &pktdma->rx_flows[j].thresh[2]);
  145. }
  146. return QM_OK;
  147. }
  148. static int ksnav_tx_disable(struct pktdma_cfg *pktdma)
  149. {
  150. u32 j, v, k;
  151. for (j = 0; j < pktdma->tx_ch_num; j++) {
  152. v = readl(&pktdma->tx_ch[j].cfg_a);
  153. if (!(v & CPDMA_CHAN_A_ENABLE))
  154. continue;
  155. writel(v | CPDMA_CHAN_A_TDOWN, &pktdma->tx_ch[j].cfg_a);
  156. for (k = 0; k < TDOWN_TIMEOUT_COUNT; k++) {
  157. udelay(100);
  158. v = readl(&pktdma->tx_ch[j].cfg_a);
  159. if (!(v & CPDMA_CHAN_A_ENABLE))
  160. continue;
  161. }
  162. /* TODO: teardown error on if TDOWN_TIMEOUT_COUNT is reached */
  163. }
  164. return QM_OK;
  165. }
  166. int ksnav_init(struct pktdma_cfg *pktdma, struct rx_buff_desc *rx_buffers)
  167. {
  168. u32 j, v;
  169. struct qm_host_desc *hd;
  170. u8 *rx_ptr;
  171. if (pktdma == NULL || rx_buffers == NULL ||
  172. rx_buffers->buff_ptr == NULL || qm_cfg == NULL)
  173. return QM_ERR;
  174. pktdma->rx_flow = rx_buffers->rx_flow;
  175. /* init rx queue */
  176. rx_ptr = rx_buffers->buff_ptr;
  177. for (j = 0; j < rx_buffers->num_buffs; j++) {
  178. hd = qm_pop(qm_cfg->qpool_num);
  179. if (hd == NULL)
  180. return QM_ERR;
  181. qm_buff_push(hd, pktdma->rx_free_q,
  182. rx_ptr, rx_buffers->buff_len);
  183. rx_ptr += rx_buffers->buff_len;
  184. }
  185. ksnav_rx_disable(pktdma);
  186. /* configure rx channels */
  187. v = CPDMA_REG_VAL_MAKE_RX_FLOW_A(1, 1, 0, 0, 0, 0, 0, pktdma->rx_rcv_q);
  188. writel(v, &pktdma->rx_flows[pktdma->rx_flow].control);
  189. writel(0, &pktdma->rx_flows[pktdma->rx_flow].tags);
  190. writel(0, &pktdma->rx_flows[pktdma->rx_flow].tag_sel);
  191. v = CPDMA_REG_VAL_MAKE_RX_FLOW_D(0, pktdma->rx_free_q, 0,
  192. pktdma->rx_free_q);
  193. writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[0]);
  194. writel(v, &pktdma->rx_flows[pktdma->rx_flow].fdq_sel[1]);
  195. writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[0]);
  196. writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[1]);
  197. writel(0, &pktdma->rx_flows[pktdma->rx_flow].thresh[2]);
  198. for (j = 0; j < pktdma->rx_ch_num; j++)
  199. writel(CPDMA_CHAN_A_ENABLE, &pktdma->rx_ch[j].cfg_a);
  200. /* configure tx channels */
  201. /* Disable loopback in the tx direction */
  202. writel(0, &pktdma->global->emulation_control);
  203. /* Set QM base address, only for K2x devices */
  204. writel(CONFIG_KSNAV_QM_BASE_ADDRESS, &pktdma->global->qm_base_addr[0]);
  205. /* Enable all channels. The current state isn't important */
  206. for (j = 0; j < pktdma->tx_ch_num; j++) {
  207. writel(0, &pktdma->tx_ch[j].cfg_b);
  208. writel(CPDMA_CHAN_A_ENABLE, &pktdma->tx_ch[j].cfg_a);
  209. }
  210. return QM_OK;
  211. }
  212. int ksnav_close(struct pktdma_cfg *pktdma)
  213. {
  214. if (!pktdma)
  215. return QM_ERR;
  216. ksnav_tx_disable(pktdma);
  217. ksnav_rx_disable(pktdma);
  218. queue_close(pktdma->rx_free_q);
  219. queue_close(pktdma->rx_rcv_q);
  220. queue_close(pktdma->tx_snd_q);
  221. return QM_OK;
  222. }
  223. int ksnav_send(struct pktdma_cfg *pktdma, u32 *pkt, int num_bytes, u32 swinfo2)
  224. {
  225. struct qm_host_desc *hd;
  226. hd = qm_pop(qm_cfg->qpool_num);
  227. if (hd == NULL)
  228. return QM_ERR;
  229. hd->desc_info = num_bytes;
  230. hd->swinfo[2] = swinfo2;
  231. hd->packet_info = qm_cfg->qpool_num;
  232. qm_buff_push(hd, pktdma->tx_snd_q, pkt, num_bytes);
  233. return QM_OK;
  234. }
  235. void *ksnav_recv(struct pktdma_cfg *pktdma, u32 **pkt, int *num_bytes)
  236. {
  237. struct qm_host_desc *hd;
  238. hd = qm_pop(pktdma->rx_rcv_q);
  239. if (!hd)
  240. return NULL;
  241. *pkt = (u32 *)hd->buff_ptr;
  242. *num_bytes = hd->desc_info & 0x3fffff;
  243. return hd;
  244. }
  245. void ksnav_release_rxhd(struct pktdma_cfg *pktdma, void *hd)
  246. {
  247. struct qm_host_desc *_hd = (struct qm_host_desc *)hd;
  248. _hd->buff_len = _hd->orig_buff_len;
  249. _hd->buff_ptr = _hd->orig_buff_ptr;
  250. qm_push(_hd, pktdma->rx_free_q);
  251. }