ddr2_regs.h 3.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (c) 2015 Purna Chandra Mandal <purna.mandal@microchip.com>
  4. *
  5. */
  6. #ifndef __MICROCHIP_DDR2_REGS_H
  7. #define __MICROCHIP_DDR2_REGS_H
  8. #include <linux/bitops.h>
  9. /* DDR2 Controller */
  10. struct ddr2_ctrl_regs {
  11. u32 tsel;
  12. u32 minlim;
  13. u32 reqprd;
  14. u32 mincmd;
  15. u32 memcon;
  16. u32 memcfg0;
  17. u32 memcfg1;
  18. u32 memcfg2;
  19. u32 memcfg3;
  20. u32 memcfg4;
  21. u32 refcfg;
  22. u32 pwrcfg;
  23. u32 dlycfg0;
  24. u32 dlycfg1;
  25. u32 dlycfg2;
  26. u32 dlycfg3;
  27. u32 odtcfg;
  28. u32 xfercfg;
  29. u32 cmdissue;
  30. u32 odtencfg;
  31. u32 memwidth;
  32. u32 unused[11];
  33. u32 cmd10[16];
  34. u32 cmd20[16];
  35. };
  36. /* Arbiter Config */
  37. #define MIN_LIM_WIDTH 5
  38. #define RQST_PERIOD_WIDTH 8
  39. #define MIN_CMDACPT_WIDTH 8
  40. /* Refresh Config */
  41. #define REFCNT_CLK(x) (x)
  42. #define REFDLY_CLK(x) ((x) << 16)
  43. #define MAX_PEND_REF(x) ((x) << 24)
  44. /* Power Config */
  45. #define PRECH_PWR_DN_ONLY(x) ((x) << 22)
  46. #define SELF_REF_DLY(x) ((x) << 12)
  47. #define PWR_DN_DLY(x) ((x) << 4)
  48. #define EN_AUTO_SELF_REF(x) ((x) << 3)
  49. #define EN_AUTO_PWR_DN(x) ((x) << 2)
  50. #define ERR_CORR_EN(x) ((x) << 1)
  51. #define ECC_EN(x) (x)
  52. /* Memory Width */
  53. #define HALF_RATE_MODE BIT(3)
  54. /* Delay Config */
  55. #define ODTWLEN(x) ((x) << 20)
  56. #define ODTRLEN(x) ((x) << 16)
  57. #define ODTWDLY(x) ((x) << 12)
  58. #define ODTRDLY(x) ((x) << 8)
  59. /* Xfer Config */
  60. #define BIG_ENDIAN(x) ((x) << 31)
  61. #define MAX_BURST(x) ((x) << 24)
  62. #define RDATENDLY(x) ((x) << 16)
  63. #define NXDATAVDLY(x) ((x) << 4)
  64. #define NXTDATRQDLY(x) ((x) << 0)
  65. /* Host Commands */
  66. #define IDLE_NOP 0x00ffffff
  67. #define PRECH_ALL_CMD 0x00fff401
  68. #define REF_CMD 0x00fff801
  69. #define LOAD_MODE_CMD 0x00fff001
  70. #define CKE_LOW 0x00ffeffe
  71. #define NUM_HOST_CMDS 12
  72. /* Host CMD Issue */
  73. #define CMD_VALID BIT(4)
  74. #define NUMHOSTCMD(x) (x)
  75. /* Memory Control */
  76. #define INIT_DONE BIT(1)
  77. #define INIT_START BIT(0)
  78. /* Address Control */
  79. #define EN_AUTO_PRECH 0
  80. #define SB_PRI 1
  81. /* DDR2 Phy Register */
  82. struct ddr2_phy_regs {
  83. u32 scl_start;
  84. u32 unused1[2];
  85. u32 scl_latency;
  86. u32 unused2[2];
  87. u32 scl_config_1;
  88. u32 scl_config_2;
  89. u32 pad_ctrl;
  90. u32 dll_recalib;
  91. };
  92. /* PHY PAD CONTROL */
  93. #define ODT_SEL BIT(0)
  94. #define ODT_EN BIT(1)
  95. #define DRIVE_SEL(x) ((x) << 2)
  96. #define ODT_PULLDOWN(x) ((x) << 4)
  97. #define ODT_PULLUP(x) ((x) << 6)
  98. #define EXTRA_OEN_CLK(x) ((x) << 8)
  99. #define NOEXT_DLL BIT(9)
  100. #define DLR_DFT_WRCMD BIT(13)
  101. #define HALF_RATE BIT(14)
  102. #define DRVSTR_PFET(x) ((x) << 16)
  103. #define DRVSTR_NFET(x) ((x) << 20)
  104. #define RCVR_EN BIT(28)
  105. #define PREAMBLE_DLY(x) ((x) << 29)
  106. /* PHY DLL RECALIBRATE */
  107. #define RECALIB_CNT(x) ((x) << 8)
  108. #define DISABLE_RECALIB(x) ((x) << 26)
  109. #define DELAY_START_VAL(x) ((x) << 28)
  110. /* PHY SCL CONFIG1 */
  111. #define SCL_BURST8 BIT(0)
  112. #define SCL_DDR_CONNECTED BIT(1)
  113. #define SCL_RCAS_LAT(x) ((x) << 4)
  114. #define SCL_ODTCSWW BIT(24)
  115. /* PHY SCL CONFIG2 */
  116. #define SCL_CSEN BIT(0)
  117. #define SCL_WCAS_LAT(x) ((x) << 8)
  118. /* PHY SCL Latency */
  119. #define SCL_CAPCLKDLY(x) ((x) << 0)
  120. #define SCL_DDRCLKDLY(x) ((x) << 4)
  121. /* PHY SCL START */
  122. #define SCL_START BIT(28)
  123. #define SCL_EN BIT(26)
  124. #define SCL_LUBPASS (BIT(1) | BIT(0))
  125. #endif /* __MICROCHIP_DDR2_REGS_H */