ddr2.c 8.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (c) 2015 Paul Thacker <paul.thacker@microchip.com>
  4. *
  5. */
  6. #include <common.h>
  7. #include <wait_bit.h>
  8. #include <linux/kernel.h>
  9. #include <linux/bitops.h>
  10. #include <mach/pic32.h>
  11. #include <mach/ddr.h>
  12. #include "ddr2_regs.h"
  13. #include "ddr2_timing.h"
  14. /* init DDR2 Phy */
  15. void ddr2_phy_init(void)
  16. {
  17. struct ddr2_phy_regs *ddr2_phy;
  18. u32 pad_ctl;
  19. ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy));
  20. /* PHY_DLL_RECALIB */
  21. writel(DELAY_START_VAL(3) | DISABLE_RECALIB(0) |
  22. RECALIB_CNT(0x10), &ddr2_phy->dll_recalib);
  23. /* PHY_PAD_CTRL */
  24. pad_ctl = ODT_SEL | ODT_EN | DRIVE_SEL(0) |
  25. ODT_PULLDOWN(2) | ODT_PULLUP(3) |
  26. EXTRA_OEN_CLK(0) | NOEXT_DLL |
  27. DLR_DFT_WRCMD | HALF_RATE |
  28. DRVSTR_PFET(0xe) | DRVSTR_NFET(0xe) |
  29. RCVR_EN | PREAMBLE_DLY(2);
  30. writel(pad_ctl, &ddr2_phy->pad_ctrl);
  31. /* SCL_CONFIG_0 */
  32. writel(SCL_BURST8 | SCL_DDR_CONNECTED | SCL_RCAS_LAT(RL) |
  33. SCL_ODTCSWW, &ddr2_phy->scl_config_1);
  34. /* SCL_CONFIG_1 */
  35. writel(SCL_CSEN | SCL_WCAS_LAT(WL), &ddr2_phy->scl_config_2);
  36. /* SCL_LAT */
  37. writel(SCL_CAPCLKDLY(3) | SCL_DDRCLKDLY(4), &ddr2_phy->scl_latency);
  38. }
  39. /* start phy self calibration logic */
  40. static int ddr2_phy_calib_start(void)
  41. {
  42. struct ddr2_phy_regs *ddr2_phy;
  43. ddr2_phy = ioremap(PIC32_DDR2P_BASE, sizeof(*ddr2_phy));
  44. /* DDR Phy SCL Start */
  45. writel(SCL_START | SCL_EN, &ddr2_phy->scl_start);
  46. /* Wait for SCL for data byte to pass */
  47. return wait_for_bit_le32(&ddr2_phy->scl_start, SCL_LUBPASS,
  48. true, CONFIG_SYS_HZ, false);
  49. }
  50. /* DDR2 Controller initialization */
  51. /* Target Agent Arbiter */
  52. static void ddr_set_arbiter(struct ddr2_ctrl_regs *ctrl,
  53. const struct ddr2_arbiter_params *const param)
  54. {
  55. int i;
  56. for (i = 0; i < NUM_AGENTS; i++) {
  57. /* set min burst size */
  58. writel(i * MIN_LIM_WIDTH, &ctrl->tsel);
  59. writel(param->min_limit, &ctrl->minlim);
  60. /* set request period (4 * req_period clocks) */
  61. writel(i * RQST_PERIOD_WIDTH, &ctrl->tsel);
  62. writel(param->req_period, &ctrl->reqprd);
  63. /* set number of burst accepted */
  64. writel(i * MIN_CMDACPT_WIDTH, &ctrl->tsel);
  65. writel(param->min_cmd_acpt, &ctrl->mincmd);
  66. }
  67. }
  68. const struct ddr2_arbiter_params *__weak board_get_ddr_arbiter_params(void)
  69. {
  70. /* default arbiter parameters */
  71. static const struct ddr2_arbiter_params arb_params[] = {
  72. { .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x04,},
  73. { .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x10,},
  74. { .min_limit = 0x1f, .req_period = 0xff, .min_cmd_acpt = 0x10,},
  75. { .min_limit = 0x04, .req_period = 0xff, .min_cmd_acpt = 0x04,},
  76. { .min_limit = 0x04, .req_period = 0xff, .min_cmd_acpt = 0x04,},
  77. };
  78. return &arb_params[0];
  79. }
  80. static void host_load_cmd(struct ddr2_ctrl_regs *ctrl, u32 cmd_idx,
  81. u32 hostcmd2, u32 hostcmd1, u32 delay)
  82. {
  83. u32 hc_delay;
  84. hc_delay = max_t(u32, DIV_ROUND_UP(delay, T_CK), 2) - 2;
  85. writel(hostcmd1, &ctrl->cmd10[cmd_idx]);
  86. writel((hostcmd2 & 0x7ff) | (hc_delay << 11), &ctrl->cmd20[cmd_idx]);
  87. }
  88. /* init DDR2 Controller */
  89. void ddr2_ctrl_init(void)
  90. {
  91. u32 wr2prech, rd2prech, wr2rd, wr2rd_cs;
  92. u32 ras2ras, ras2cas, prech2ras, temp;
  93. const struct ddr2_arbiter_params *arb_params;
  94. struct ddr2_ctrl_regs *ctrl;
  95. ctrl = ioremap(PIC32_DDR2C_BASE, sizeof(*ctrl));
  96. /* PIC32 DDR2 controller always work in HALF_RATE */
  97. writel(HALF_RATE_MODE, &ctrl->memwidth);
  98. /* Set arbiter configuration per target */
  99. arb_params = board_get_ddr_arbiter_params();
  100. ddr_set_arbiter(ctrl, arb_params);
  101. /* Address Configuration, model {CS, ROW, BA, COL} */
  102. writel((ROW_ADDR_RSHIFT | (BA_RSHFT << 8) | (CS_ADDR_RSHIFT << 16) |
  103. (COL_HI_RSHFT << 24) | (SB_PRI << 29) |
  104. (EN_AUTO_PRECH << 30)), &ctrl->memcfg0);
  105. writel(ROW_ADDR_MASK, &ctrl->memcfg1);
  106. writel(COL_HI_MASK, &ctrl->memcfg2);
  107. writel(COL_LO_MASK, &ctrl->memcfg3);
  108. writel(BA_MASK | (CS_ADDR_MASK << 8), &ctrl->memcfg4);
  109. /* Refresh Config */
  110. writel(REFCNT_CLK(DIV_ROUND_UP(T_RFI, T_CK_CTRL) - 2) |
  111. REFDLY_CLK(DIV_ROUND_UP(T_RFC_MIN, T_CK_CTRL) - 2) |
  112. MAX_PEND_REF(7),
  113. &ctrl->refcfg);
  114. /* Power Config */
  115. writel(ECC_EN(0) | ERR_CORR_EN(0) | EN_AUTO_PWR_DN(0) |
  116. EN_AUTO_SELF_REF(3) | PWR_DN_DLY(8) |
  117. SELF_REF_DLY(17) | PRECH_PWR_DN_ONLY(0),
  118. &ctrl->pwrcfg);
  119. /* Delay Config */
  120. wr2rd = max_t(u32, DIV_ROUND_UP(T_WTR, T_CK_CTRL),
  121. DIV_ROUND_UP(T_WTR_TCK, 2)) + WL + BL;
  122. wr2rd_cs = max_t(u32, wr2rd - 1, 3);
  123. wr2prech = DIV_ROUND_UP(T_WR, T_CK_CTRL) + WL + BL;
  124. rd2prech = max_t(u32, DIV_ROUND_UP(T_RTP, T_CK_CTRL),
  125. DIV_ROUND_UP(T_RTP_TCK, 2)) + BL - 2;
  126. ras2ras = max_t(u32, DIV_ROUND_UP(T_RRD, T_CK_CTRL),
  127. DIV_ROUND_UP(T_RRD_TCK, 2)) - 1;
  128. ras2cas = DIV_ROUND_UP(T_RCD, T_CK_CTRL) - 1;
  129. prech2ras = DIV_ROUND_UP(T_RP, T_CK_CTRL) - 1;
  130. writel(((wr2rd & 0x0f) |
  131. ((wr2rd_cs & 0x0f) << 4) |
  132. ((BL - 1) << 8) |
  133. (BL << 12) |
  134. ((BL - 1) << 16) |
  135. ((BL - 1) << 20) |
  136. ((BL + 2) << 24) |
  137. ((RL - WL + 3) << 28)), &ctrl->dlycfg0);
  138. writel(((T_CKE_TCK - 1) |
  139. (((DIV_ROUND_UP(T_DLLK, 2) - 2) & 0xff) << 8) |
  140. ((T_CKE_TCK - 1) << 16) |
  141. ((max_t(u32, T_XP_TCK, T_CKE_TCK) - 1) << 20) |
  142. ((wr2prech >> 4) << 26) |
  143. ((wr2rd >> 4) << 27) |
  144. ((wr2rd_cs >> 4) << 28) |
  145. (((RL + 5) >> 4) << 29) |
  146. ((DIV_ROUND_UP(T_DLLK, 2) >> 8) << 30)), &ctrl->dlycfg1);
  147. writel((DIV_ROUND_UP(T_RP, T_CK_CTRL) |
  148. (rd2prech << 8) |
  149. ((wr2prech & 0x0f) << 12) |
  150. (ras2ras << 16) |
  151. (ras2cas << 20) |
  152. (prech2ras << 24) |
  153. ((RL + 3) << 28)), &ctrl->dlycfg2);
  154. writel(((DIV_ROUND_UP(T_RAS_MIN, T_CK_CTRL) - 1) |
  155. ((DIV_ROUND_UP(T_RC, T_CK_CTRL) - 1) << 8) |
  156. ((DIV_ROUND_UP(T_FAW, T_CK_CTRL) - 1) << 16)),
  157. &ctrl->dlycfg3);
  158. /* ODT Config */
  159. writel(0x0, &ctrl->odtcfg);
  160. writel(BIT(16), &ctrl->odtencfg);
  161. writel(ODTRDLY(RL - 3) | ODTWDLY(WL - 3) | ODTRLEN(2) | ODTWLEN(3),
  162. &ctrl->odtcfg);
  163. /* Transfer Configuration */
  164. writel(NXTDATRQDLY(2) | NXDATAVDLY(4) | RDATENDLY(2) |
  165. MAX_BURST(3) | (7 << 28) | BIG_ENDIAN(0),
  166. &ctrl->xfercfg);
  167. /* DRAM Initialization */
  168. /* CKE high after reset and wait 400 nsec */
  169. host_load_cmd(ctrl, 0, 0, IDLE_NOP, 400000);
  170. /* issue precharge all command */
  171. host_load_cmd(ctrl, 1, 0x04, PRECH_ALL_CMD, T_RP + T_CK);
  172. /* initialize EMR2 */
  173. host_load_cmd(ctrl, 2, 0x200, LOAD_MODE_CMD, T_MRD_TCK * T_CK);
  174. /* initialize EMR3 */
  175. host_load_cmd(ctrl, 3, 0x300, LOAD_MODE_CMD, T_MRD_TCK * T_CK);
  176. /*
  177. * RDQS disable, DQSB enable, OCD exit, 150 ohm termination,
  178. * AL=0, DLL enable
  179. */
  180. host_load_cmd(ctrl, 4, 0x100,
  181. LOAD_MODE_CMD | (0x40 << 24), T_MRD_TCK * T_CK);
  182. /*
  183. * PD fast exit, WR REC = T_WR in clocks -1,
  184. * DLL reset, CAS = RL, burst = 4
  185. */
  186. temp = ((DIV_ROUND_UP(T_WR, T_CK) - 1) << 1) | 1;
  187. host_load_cmd(ctrl, 5, temp, LOAD_MODE_CMD | (RL << 28) | (2 << 24),
  188. T_MRD_TCK * T_CK);
  189. /* issue precharge all command */
  190. host_load_cmd(ctrl, 6, 4, PRECH_ALL_CMD, T_RP + T_CK);
  191. /* issue refresh command */
  192. host_load_cmd(ctrl, 7, 0, REF_CMD, T_RFC_MIN);
  193. /* issue refresh command */
  194. host_load_cmd(ctrl, 8, 0, REF_CMD, T_RFC_MIN);
  195. /* Mode register programming as before without DLL reset */
  196. host_load_cmd(ctrl, 9, temp, LOAD_MODE_CMD | (RL << 28) | (3 << 24),
  197. T_MRD_TCK * T_CK);
  198. /* extended mode register same as before with OCD default */
  199. host_load_cmd(ctrl, 10, 0x103, LOAD_MODE_CMD | (0xc << 24),
  200. T_MRD_TCK * T_CK);
  201. /* extended mode register same as before with OCD exit */
  202. host_load_cmd(ctrl, 11, 0x100, LOAD_MODE_CMD | (0x4 << 28),
  203. 140 * T_CK);
  204. writel(CMD_VALID | NUMHOSTCMD(11), &ctrl->cmdissue);
  205. /* start memory initialization */
  206. writel(INIT_START, &ctrl->memcon);
  207. /* wait for all host cmds to be transmitted */
  208. wait_for_bit_le32(&ctrl->cmdissue, CMD_VALID, false,
  209. CONFIG_SYS_HZ, false);
  210. /* inform all cmds issued, ready for normal operation */
  211. writel(INIT_START | INIT_DONE, &ctrl->memcon);
  212. /* perform phy caliberation */
  213. if (ddr2_phy_calib_start())
  214. printf("ddr2: phy calib failed\n");
  215. }
  216. phys_size_t ddr2_calculate_size(void)
  217. {
  218. u32 temp;
  219. temp = 1 << (COL_BITS + BA_BITS + ROW_BITS);
  220. /* 16-bit data width between controller and DIMM */
  221. temp = temp * CS_BITS * (16 / 8);
  222. return (phys_size_t)temp;
  223. }