ace_sha.c 5.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Advanced Crypto Engine - SHA Firmware
  4. * Copyright (c) 2012 Samsung Electronics
  5. */
  6. #include <common.h>
  7. #include "ace_sha.h"
  8. #include <log.h>
  9. #include <rand.h>
  10. #ifdef CONFIG_SHA_HW_ACCEL
  11. #include <u-boot/sha256.h>
  12. #include <u-boot/sha1.h>
  13. #include <linux/errno.h>
  14. /* SHA1 value for the message of zero length */
  15. static const unsigned char sha1_digest_emptymsg[SHA1_SUM_LEN] = {
  16. 0xDA, 0x39, 0xA3, 0xEE, 0x5E, 0x6B, 0x4B, 0x0D,
  17. 0x32, 0x55, 0xBF, 0xFF, 0x95, 0x60, 0x18, 0x90,
  18. 0xAF, 0xD8, 0x07, 0x09};
  19. /* SHA256 value for the message of zero length */
  20. static const unsigned char sha256_digest_emptymsg[SHA256_SUM_LEN] = {
  21. 0xE3, 0xB0, 0xC4, 0x42, 0x98, 0xFC, 0x1C, 0x14,
  22. 0x9A, 0xFB, 0xF4, 0xC8, 0x99, 0x6F, 0xB9, 0x24,
  23. 0x27, 0xAE, 0x41, 0xE4, 0x64, 0x9B, 0x93, 0x4C,
  24. 0xA4, 0x95, 0x99, 0x1B, 0x78, 0x52, 0xB8, 0x55};
  25. int ace_sha_hash_digest(const unsigned char *pbuf, unsigned int buf_len,
  26. unsigned char *pout, unsigned int hash_type)
  27. {
  28. unsigned int i, reg, len;
  29. unsigned int *pdigest;
  30. struct exynos_ace_sfr *ace_sha_reg =
  31. (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
  32. if (buf_len == 0) {
  33. /* ACE H/W cannot compute hash value for empty string */
  34. if (hash_type == ACE_SHA_TYPE_SHA1)
  35. memcpy(pout, sha1_digest_emptymsg, SHA1_SUM_LEN);
  36. else
  37. memcpy(pout, sha256_digest_emptymsg, SHA256_SUM_LEN);
  38. return 0;
  39. }
  40. /* Flush HRDMA */
  41. writel(ACE_FC_HRDMACFLUSH_ON, &ace_sha_reg->fc_hrdmac);
  42. writel(ACE_FC_HRDMACFLUSH_OFF, &ace_sha_reg->fc_hrdmac);
  43. /* Set byte swap of data in */
  44. writel(ACE_HASH_SWAPDI_ON | ACE_HASH_SWAPDO_ON | ACE_HASH_SWAPIV_ON,
  45. &ace_sha_reg->hash_byteswap);
  46. /* Select Hash input mux as external source */
  47. reg = readl(&ace_sha_reg->fc_fifoctrl);
  48. reg = (reg & ~ACE_FC_SELHASH_MASK) | ACE_FC_SELHASH_EXOUT;
  49. writel(reg, &ace_sha_reg->fc_fifoctrl);
  50. /* Set Hash as SHA1 or SHA256 and start Hash engine */
  51. reg = (hash_type == ACE_SHA_TYPE_SHA1) ?
  52. ACE_HASH_ENGSEL_SHA1HASH : ACE_HASH_ENGSEL_SHA256HASH;
  53. reg |= ACE_HASH_STARTBIT_ON;
  54. writel(reg, &ace_sha_reg->hash_control);
  55. /* Enable FIFO mode */
  56. writel(ACE_HASH_FIFO_ON, &ace_sha_reg->hash_fifo_mode);
  57. /* Set message length */
  58. writel(buf_len, &ace_sha_reg->hash_msgsize_low);
  59. writel(0, &ace_sha_reg->hash_msgsize_high);
  60. /* Set HRDMA */
  61. writel((unsigned int)pbuf, &ace_sha_reg->fc_hrdmas);
  62. writel(buf_len, &ace_sha_reg->fc_hrdmal);
  63. while ((readl(&ace_sha_reg->hash_status) & ACE_HASH_MSGDONE_MASK) ==
  64. ACE_HASH_MSGDONE_OFF) {
  65. /*
  66. * PRNG error bit goes HIGH if a PRNG request occurs without
  67. * a complete seed setup. We are using this bit to check h/w
  68. * fault because proper setup is not expected in that case.
  69. */
  70. if ((readl(&ace_sha_reg->hash_status)
  71. & ACE_HASH_PRNGERROR_MASK) == ACE_HASH_PRNGERROR_ON)
  72. return -EBUSY;
  73. }
  74. /* Clear MSG_DONE bit */
  75. writel(ACE_HASH_MSGDONE_ON, &ace_sha_reg->hash_status);
  76. /* Read hash result */
  77. pdigest = (unsigned int *)pout;
  78. len = (hash_type == ACE_SHA_TYPE_SHA1) ? SHA1_SUM_LEN : SHA256_SUM_LEN;
  79. for (i = 0; i < len / 4; i++)
  80. pdigest[i] = readl(&ace_sha_reg->hash_result[i]);
  81. /* Clear HRDMA pending bit */
  82. writel(ACE_FC_HRDMA, &ace_sha_reg->fc_intpend);
  83. return 0;
  84. }
  85. void hw_sha256(const unsigned char *pbuf, unsigned int buf_len,
  86. unsigned char *pout, unsigned int chunk_size)
  87. {
  88. if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA256))
  89. debug("ACE was not setup properly or it is faulty\n");
  90. }
  91. void hw_sha1(const unsigned char *pbuf, unsigned int buf_len,
  92. unsigned char *pout, unsigned int chunk_size)
  93. {
  94. if (ace_sha_hash_digest(pbuf, buf_len, pout, ACE_SHA_TYPE_SHA1))
  95. debug("ACE was not setup properly or it is faulty\n");
  96. }
  97. #endif /* CONFIG_SHA_HW_ACCEL */
  98. #ifdef CONFIG_LIB_HW_RAND
  99. static unsigned int seed_done;
  100. void srand(unsigned int seed)
  101. {
  102. struct exynos_ace_sfr *reg =
  103. (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
  104. int i, status;
  105. /* Seed data */
  106. for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
  107. writel(seed << i, &reg->hash_seed[i]);
  108. /* Wait for seed setup done */
  109. while (1) {
  110. status = readl(&reg->hash_status);
  111. if ((status & ACE_HASH_SEEDSETTING_MASK) ||
  112. (status & ACE_HASH_PRNGERROR_MASK))
  113. break;
  114. }
  115. seed_done = 1;
  116. }
  117. unsigned int rand(void)
  118. {
  119. struct exynos_ace_sfr *reg =
  120. (struct exynos_ace_sfr *)samsung_get_base_ace_sfr();
  121. int i, status;
  122. unsigned int seed = (unsigned int)&status;
  123. unsigned int ret = 0;
  124. if (!seed_done)
  125. srand(seed);
  126. /* Start PRNG */
  127. writel(ACE_HASH_ENGSEL_PRNG | ACE_HASH_STARTBIT_ON, &reg->hash_control);
  128. /* Wait for PRNG done */
  129. while (1) {
  130. status = readl(&reg->hash_status);
  131. if (status & ACE_HASH_PRNGDONE_MASK)
  132. break;
  133. if (status & ACE_HASH_PRNGERROR_MASK) {
  134. seed_done = 0;
  135. return 0;
  136. }
  137. }
  138. /* Clear Done IRQ */
  139. writel(ACE_HASH_PRNGDONE_MASK, &reg->hash_status);
  140. /* Read a PRNG result */
  141. for (i = 0; i < ACE_HASH_PRNG_REG_NUM; i++)
  142. ret += readl(&reg->hash_prng[i]);
  143. seed_done = 0;
  144. return ret;
  145. }
  146. unsigned int rand_r(unsigned int *seedp)
  147. {
  148. srand(*seedp);
  149. return rand();
  150. }
  151. #endif /* CONFIG_LIB_HW_RAND */