tegra-car-clk.c 2.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2016, NVIDIA CORPORATION.
  4. */
  5. #include <common.h>
  6. #include <clk-uclass.h>
  7. #include <dm.h>
  8. #include <log.h>
  9. #include <malloc.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/arch-tegra/clk_rst.h>
  12. static int tegra_car_clk_request(struct clk *clk)
  13. {
  14. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  15. clk->id);
  16. /*
  17. * Note that the first PERIPH_ID_COUNT clock IDs (where the value
  18. * varies per SoC) are the peripheral clocks, which use a numbering
  19. * scheme that matches HW registers 1:1. There are other clock IDs
  20. * beyond this that are assigned arbitrarily by the Tegra CAR DT
  21. * binding. Due to the implementation of this driver, it currently
  22. * only supports the peripheral IDs.
  23. */
  24. if (clk->id >= PERIPH_ID_COUNT)
  25. return -EINVAL;
  26. return 0;
  27. }
  28. static int tegra_car_clk_free(struct clk *clk)
  29. {
  30. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  31. clk->id);
  32. return 0;
  33. }
  34. static ulong tegra_car_clk_get_rate(struct clk *clk)
  35. {
  36. enum clock_id parent;
  37. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  38. clk->id);
  39. parent = clock_get_periph_parent(clk->id);
  40. return clock_get_periph_rate(clk->id, parent);
  41. }
  42. static ulong tegra_car_clk_set_rate(struct clk *clk, ulong rate)
  43. {
  44. enum clock_id parent;
  45. debug("%s(clk=%p, rate=%lu) (dev=%p, id=%lu)\n", __func__, clk, rate,
  46. clk->dev, clk->id);
  47. parent = clock_get_periph_parent(clk->id);
  48. return clock_adjust_periph_pll_div(clk->id, parent, rate, NULL);
  49. }
  50. static int tegra_car_clk_enable(struct clk *clk)
  51. {
  52. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  53. clk->id);
  54. clock_enable(clk->id);
  55. return 0;
  56. }
  57. static int tegra_car_clk_disable(struct clk *clk)
  58. {
  59. debug("%s(clk=%p) (dev=%p, id=%lu)\n", __func__, clk, clk->dev,
  60. clk->id);
  61. clock_disable(clk->id);
  62. return 0;
  63. }
  64. static struct clk_ops tegra_car_clk_ops = {
  65. .request = tegra_car_clk_request,
  66. .rfree = tegra_car_clk_free,
  67. .get_rate = tegra_car_clk_get_rate,
  68. .set_rate = tegra_car_clk_set_rate,
  69. .enable = tegra_car_clk_enable,
  70. .disable = tegra_car_clk_disable,
  71. };
  72. static int tegra_car_clk_probe(struct udevice *dev)
  73. {
  74. debug("%s(dev=%p)\n", __func__, dev);
  75. return 0;
  76. }
  77. U_BOOT_DRIVER(tegra_car_clk) = {
  78. .name = "tegra_car_clk",
  79. .id = UCLASS_CLK,
  80. .probe = tegra_car_clk_probe,
  81. .ops = &tegra_car_clk_ops,
  82. };