clk_owl.h 1.5 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Actions Semi SoCs Clock Definitions
  4. *
  5. * Copyright (C) 2015 Actions Semi Co., Ltd.
  6. * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  7. *
  8. */
  9. #ifndef _OWL_CLK_H_
  10. #define _OWL_CLK_H_
  11. #include <clk-uclass.h>
  12. #ifndef __ASSEMBLY__
  13. #include <linux/bitops.h>
  14. #endif
  15. enum owl_soc {
  16. S700,
  17. S900,
  18. };
  19. struct owl_clk_priv {
  20. phys_addr_t base;
  21. };
  22. /* BUSCLK register definitions */
  23. #define CMU_PDBGDIV_8 7
  24. #define CMU_PDBGDIV_SHIFT 26
  25. #define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
  26. #define CMU_PERDIV_8 7
  27. #define CMU_PERDIV_SHIFT 20
  28. #define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
  29. #define CMU_NOCDIV_2 1
  30. #define CMU_NOCDIV_SHIFT 19
  31. #define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
  32. #define CMU_DMMCLK_SRC_APLL 2
  33. #define CMU_DMMCLK_SRC_SHIFT 10
  34. #define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT)
  35. #define CMU_APBCLK_DIV BIT(8)
  36. #define CMU_NOCCLK_SRC BIT(7)
  37. #define CMU_AHBCLK_DIV BIT(4)
  38. #define CMU_CORECLK_MASK 3
  39. #define CMU_CORECLK_CPLL BIT(1)
  40. #define CMU_CORECLK_HOSC BIT(0)
  41. /* COREPLL register definitions */
  42. #define CMU_COREPLL_EN BIT(9)
  43. #define CMU_COREPLL_HOSC_EN BIT(8)
  44. #define CMU_COREPLL_OUT (1104 / 24)
  45. /* DEVPLL register definitions */
  46. #define CMU_DEVPLL_CLK BIT(12)
  47. #define CMU_DEVPLL_EN BIT(8)
  48. #define CMU_DEVPLL_OUT (660 / 6)
  49. /* UARTCLK register definitions */
  50. #define CMU_UARTCLK_SRC_DEVPLL BIT(16)
  51. #define PLL_STABILITY_WAIT_US 50
  52. #define CMU_DEVCLKEN1_UART5 BIT(21)
  53. #define CMU_DEVCLKEN1_UART3 BIT(11)
  54. #endif